[core] now support rebuild configuarable children for ccff submodules
This commit is contained in:
tangxifan
parent
a1b13b8e12
commit
d3aa4c53d0
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@ -1320,6 +1320,15 @@ void ModuleManager::clear_io_children(const ModuleId& parent_module) {
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io_child_coordinates_[parent_module].clear();
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}
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void ModuleManager::clear_module_net_sinks(const ModuleId& parent_module,
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const ModuleNetId& net) {
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VTR_ASSERT(valid_module_net_id(parent_module, net));
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net_sink_ids_[parent_module][net].clear();
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net_sink_terminal_ids_[parent_module][net].clear();
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net_sink_instance_ids_[parent_module][net].clear();
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net_sink_pin_ids_[parent_module][net].clear();
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}
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/******************************************************************************
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* Private validators/invalidators
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******************************************************************************/
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@ -469,6 +469,10 @@ class ModuleManager {
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*/
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void clear_io_children(const ModuleId& parent_module);
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/* Remove all the sinks for a given net under a module */
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void clear_module_net_sinks(const ModuleId& parent_module,
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const ModuleNetId& net);
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public: /* Public validators/invalidators */
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bool valid_module_id(const ModuleId& module) const;
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bool valid_module_port_id(const ModuleId& module,
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@ -2652,6 +2652,334 @@ static bool update_submodule_memory_modules_from_fabric_key(
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return CMD_EXEC_SUCCESS;
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}
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/********************************************************************
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* Remove the nets around the configuration chain (ccff_head and ccff_tails)
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*******************************************************************/
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static int remove_submodule_nets_cmos_memory_chain_config_bus(
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ModuleManager& module_manager, const ModuleId& parent_module,
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const e_config_protocol_type& sram_orgz_type) {
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for (size_t mem_index = 0;
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mem_index < module_manager.configurable_children(parent_module).size();
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++mem_index) {
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ModuleId net_src_module_id;
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size_t net_src_instance_id;
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ModulePortId net_src_port_id;
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if (0 == mem_index) {
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/* Find the port name of configuration chain head */
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std::string src_port_name =
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generate_sram_port_name(sram_orgz_type, CIRCUIT_MODEL_PORT_INPUT);
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net_src_module_id = parent_module;
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net_src_instance_id = 0;
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net_src_port_id =
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module_manager.find_module_port(net_src_module_id, src_port_name);
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} else {
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/* Find the port name of previous memory module */
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std::string src_port_name = generate_configuration_chain_tail_name();
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net_src_module_id =
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module_manager.configurable_children(parent_module)[mem_index - 1];
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net_src_instance_id = module_manager.configurable_child_instances(
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parent_module)[mem_index - 1];
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net_src_port_id =
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module_manager.find_module_port(net_src_module_id, src_port_name);
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}
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/* Get the pin id for source port */
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BasicPort net_src_port =
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module_manager.module_port(net_src_module_id, net_src_port_id);
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/* Create a net for each pin */
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for (size_t pin_id = 0; pin_id < net_src_port.pins().size(); ++pin_id) {
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/* Find the net from which the source node is driving */
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ModuleNetId net = module_manager.module_instance_port_net(
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parent_module, net_src_module_id, net_src_instance_id, net_src_port_id,
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net_src_port.pins()[pin_id]);
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/* Remove the net including sources and sinks */
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module_manager.clear_module_net_sinks(parent_module, net);
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}
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}
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/* For the last memory module:
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* net source is the configuration chain tail of the previous memory module
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* net sink is the configuration chain tail of the primitive module
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*/
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/* Find the port name of previous memory module */
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std::string src_port_name = generate_configuration_chain_tail_name();
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ModuleId net_src_module_id =
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module_manager.configurable_children(parent_module).back();
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size_t net_src_instance_id =
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module_manager.configurable_child_instances(parent_module).back();
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ModulePortId net_src_port_id =
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module_manager.find_module_port(net_src_module_id, src_port_name);
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/* Get the pin id for source port */
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BasicPort net_src_port =
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module_manager.module_port(net_src_module_id, net_src_port_id);
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/* Create a net for each pin */
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for (size_t pin_id = 0; pin_id < net_src_port.pins().size(); ++pin_id) {
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/* Find the net from which the source node is driving */
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ModuleNetId net = module_manager.module_instance_port_net(
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parent_module, net_src_module_id, net_src_instance_id,
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net_src_port_id, net_src_port.pins()[pin_id]);
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/* Remove the net including sources and sinks */
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module_manager.clear_module_net_sinks(parent_module, net);
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}
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}
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/********************************************************************
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* Remove the nets around the configurable children for a given module which
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*should be in CMOS type
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*******************************************************************/
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static int remove_submodule_nets_cmos_memory_config_bus(
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ModuleManager& module_manager, const ModuleId& module_id,
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const e_config_protocol_type& sram_orgz_type) {
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switch (sram_orgz_type) {
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case CONFIG_MEM_SCAN_CHAIN: {
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remove_submodule_nets_cmos_memory_chain_config_bus(module_manager, module_id,
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sram_orgz_type);
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break;
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}
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case CONFIG_MEM_STANDALONE:
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case CONFIG_MEM_QL_MEMORY_BANK:
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/* TODO:
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add_module_nets_cmos_memory_bank_bl_config_bus(
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module_manager, parent_module, sram_orgz_type, CIRCUIT_MODEL_PORT_BL);
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add_module_nets_cmos_memory_bank_wl_config_bus(
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module_manager, parent_module, sram_orgz_type, CIRCUIT_MODEL_PORT_WL);
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add_module_nets_cmos_memory_bank_wl_config_bus(
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module_manager, parent_module, sram_orgz_type, CIRCUIT_MODEL_PORT_WLR);
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*/
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break;
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case CONFIG_MEM_MEMORY_BANK:
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/* TODO:
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add_module_nets_cmos_flatten_memory_config_bus(
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module_manager, parent_module, sram_orgz_type, CIRCUIT_MODEL_PORT_BL);
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add_module_nets_cmos_flatten_memory_config_bus(
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module_manager, parent_module, sram_orgz_type, CIRCUIT_MODEL_PORT_WL);
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*/
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break;
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case CONFIG_MEM_FRAME_BASED:
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/* TODO:
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add_module_nets_cmos_memory_frame_config_bus(module_manager, decoder_lib,
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parent_module);
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*/
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break;
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default:
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VTR_LOGF_ERROR(__FILE__, __LINE__,
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"Invalid type of SRAM organization!\n");
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exit(1);
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}
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}
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/********************************************************************
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* Remove the nets around the configurable children for a given module
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*******************************************************************/
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static int remove_submodule_configurable_children_nets(
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ModuleManager& module_manager, const ModuleId& module_id,
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const CircuitLibrary& circuit_lib, const ConfigProtocol& config_protocol) {
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switch (circuit_lib.design_tech_type(config_protocol.memory_model())) {
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case CIRCUIT_MODEL_DESIGN_CMOS:
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remove_submodule_nets_cmos_memory_config_bus(module_manager, module_id,
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config_protocol.type());
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break;
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case CIRCUIT_MODEL_DESIGN_RRAM:
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/* TODO: */
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break;
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default:
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VTR_LOGF_ERROR(__FILE__, __LINE__,
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"Invalid type of memory design technology!\n");
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exit(1);
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}
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}
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/********************************************************************
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* Rebuild the nets(only sinks) around the configuration chain (ccff_head and
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*ccff_tails)
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*******************************************************************/
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static int rebuild_submodule_nets_cmos_memory_chain_config_bus(
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ModuleManager& module_manager, const ModuleId& parent_module,
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const e_config_protocol_type& sram_orgz_type) {
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for (size_t mem_index = 0;
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mem_index < module_manager.configurable_children(parent_module).size();
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++mem_index) {
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ModuleId net_src_module_id;
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size_t net_src_instance_id;
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ModulePortId net_src_port_id;
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ModuleId net_sink_module_id;
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size_t net_sink_instance_id;
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ModulePortId net_sink_port_id;
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if (0 == mem_index) {
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/* Find the port name of configuration chain head */
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std::string src_port_name =
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generate_sram_port_name(sram_orgz_type, CIRCUIT_MODEL_PORT_INPUT);
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net_src_module_id = parent_module;
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net_src_instance_id = 0;
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net_src_port_id =
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module_manager.find_module_port(net_src_module_id, src_port_name);
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/* Find the port name of next memory module */
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std::string sink_port_name = generate_configuration_chain_head_name();
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net_sink_module_id =
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module_manager.configurable_children(parent_module)[mem_index];
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net_sink_instance_id =
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module_manager.configurable_child_instances(parent_module)[mem_index];
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net_sink_port_id =
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module_manager.find_module_port(net_sink_module_id, sink_port_name);
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} else {
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/* Find the port name of previous memory module */
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std::string src_port_name = generate_configuration_chain_tail_name();
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net_src_module_id =
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module_manager.configurable_children(parent_module)[mem_index - 1];
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net_src_instance_id = module_manager.configurable_child_instances(
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parent_module)[mem_index - 1];
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net_src_port_id =
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module_manager.find_module_port(net_src_module_id, src_port_name);
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/* Find the port name of next memory module */
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std::string sink_port_name = generate_configuration_chain_head_name();
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net_sink_module_id =
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module_manager.configurable_children(parent_module)[mem_index];
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net_sink_instance_id =
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module_manager.configurable_child_instances(parent_module)[mem_index];
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net_sink_port_id =
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module_manager.find_module_port(net_sink_module_id, sink_port_name);
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}
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/* Get the pin id for source port */
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BasicPort net_src_port =
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module_manager.module_port(net_src_module_id, net_src_port_id);
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/* Get the pin id for sink port */
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BasicPort net_sink_port =
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module_manager.module_port(net_sink_module_id, net_sink_port_id);
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/* Port sizes of source and sink should match */
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VTR_ASSERT(net_src_port.get_width() == net_sink_port.get_width());
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/* Create a net for each pin */
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for (size_t pin_id = 0; pin_id < net_src_port.pins().size(); ++pin_id) {
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/* Create a net and add source and sink to it */
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ModuleNetId net = create_module_source_pin_net(
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module_manager, parent_module, net_src_module_id, net_src_instance_id,
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net_src_port_id, net_src_port.pins()[pin_id]);
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/* Add net sink */
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module_manager.add_module_net_sink(parent_module, net, net_sink_module_id,
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net_sink_instance_id, net_sink_port_id,
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net_sink_port.pins()[pin_id]);
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}
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}
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/* For the last memory module:
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* net source is the configuration chain tail of the previous memory module
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* net sink is the configuration chain tail of the primitive module
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*/
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/* Find the port name of previous memory module */
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std::string src_port_name = generate_configuration_chain_tail_name();
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ModuleId net_src_module_id =
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module_manager.configurable_children(parent_module).back();
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size_t net_src_instance_id =
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module_manager.configurable_child_instances(parent_module).back();
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ModulePortId net_src_port_id =
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module_manager.find_module_port(net_src_module_id, src_port_name);
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/* Find the port name of next memory module */
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std::string sink_port_name =
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generate_sram_port_name(sram_orgz_type, CIRCUIT_MODEL_PORT_OUTPUT);
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ModuleId net_sink_module_id = parent_module;
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size_t net_sink_instance_id = 0;
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ModulePortId net_sink_port_id =
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module_manager.find_module_port(net_sink_module_id, sink_port_name);
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/* Get the pin id for source port */
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BasicPort net_src_port =
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module_manager.module_port(net_src_module_id, net_src_port_id);
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/* Get the pin id for sink port */
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BasicPort net_sink_port =
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module_manager.module_port(net_sink_module_id, net_sink_port_id);
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/* Port sizes of source and sink should match */
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VTR_ASSERT(net_src_port.get_width() == net_sink_port.get_width());
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/* Create a net for each pin */
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for (size_t pin_id = 0; pin_id < net_src_port.pins().size(); ++pin_id) {
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/* Create a net and add source and sink to it */
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ModuleNetId net = create_module_source_pin_net(
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module_manager, parent_module, net_src_module_id, net_src_instance_id,
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net_src_port_id, net_src_port.pins()[pin_id]);
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/* Add net sink */
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module_manager.add_module_net_sink(parent_module, net, net_sink_module_id,
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net_sink_instance_id, net_sink_port_id,
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net_sink_port.pins()[pin_id]);
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}
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}
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/********************************************************************
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* Rebuild the nets around the configurable children for a given module which
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*should be in CMOS type
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*******************************************************************/
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static int rebuild_submodule_nets_cmos_memory_config_bus(
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ModuleManager& module_manager, const ModuleId& module_id,
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const e_config_protocol_type& sram_orgz_type) {
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switch (sram_orgz_type) {
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case CONFIG_MEM_SCAN_CHAIN: {
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rebuild_submodule_nets_cmos_memory_chain_config_bus(
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module_manager, module_id, sram_orgz_type);
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break;
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}
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case CONFIG_MEM_STANDALONE:
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case CONFIG_MEM_QL_MEMORY_BANK:
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/* TODO:
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add_module_nets_cmos_memory_bank_bl_config_bus(
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module_manager, parent_module, sram_orgz_type, CIRCUIT_MODEL_PORT_BL);
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add_module_nets_cmos_memory_bank_wl_config_bus(
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module_manager, parent_module, sram_orgz_type, CIRCUIT_MODEL_PORT_WL);
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add_module_nets_cmos_memory_bank_wl_config_bus(
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module_manager, parent_module, sram_orgz_type, CIRCUIT_MODEL_PORT_WLR);
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*/
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break;
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case CONFIG_MEM_MEMORY_BANK:
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/* TODO:
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add_module_nets_cmos_flatten_memory_config_bus(
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module_manager, parent_module, sram_orgz_type, CIRCUIT_MODEL_PORT_BL);
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add_module_nets_cmos_flatten_memory_config_bus(
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module_manager, parent_module, sram_orgz_type, CIRCUIT_MODEL_PORT_WL);
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*/
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break;
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case CONFIG_MEM_FRAME_BASED:
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/* TODO:
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add_module_nets_cmos_memory_frame_config_bus(module_manager, decoder_lib,
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parent_module);
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*/
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break;
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default:
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VTR_LOGF_ERROR(__FILE__, __LINE__,
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"Invalid type of SRAM organization!\n");
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exit(1);
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}
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}
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/********************************************************************
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* Rebuild the nets(only sinks) around the configurable children for a given
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*module
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*******************************************************************/
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static int rebuild_submodule_configurable_children_nets(
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ModuleManager& module_manager, const ModuleId& module_id,
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const CircuitLibrary& circuit_lib, const ConfigProtocol& config_protocol) {
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switch (circuit_lib.design_tech_type(config_protocol.memory_model())) {
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case CIRCUIT_MODEL_DESIGN_CMOS:
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rebuild_submodule_nets_cmos_memory_config_bus(module_manager, module_id,
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config_protocol.type());
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break;
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case CIRCUIT_MODEL_DESIGN_RRAM:
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/* TODO: */
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break;
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default:
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VTR_LOGF_ERROR(__FILE__, __LINE__,
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"Invalid type of memory design technology!\n");
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exit(1);
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}
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}
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/********************************************************************
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* Load and update the configurable children of a given module (not a top-level
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*module) Compare the configurable children list with fabric sub-keys.
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@ -2671,8 +2999,12 @@ static int load_and_update_submodule_memory_modules_from_fabric_key(
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fabric_key, key_module_id)) {
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return CMD_EXEC_SUCCESS;
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}
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/* TODO: Do not match, now remove all the nets for the configurable children
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*/
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/* Do not match, now remove all the nets for the configurable children */
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status = remove_submodule_configurable_children_nets(
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module_manager, module_id, circuit_lib, config_protocol);
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if (status == CMD_EXEC_FATAL_ERROR) {
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return status;
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}
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/* Overwrite the configurable children list */
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status = update_submodule_memory_modules_from_fabric_key(
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module_manager, module_id, circuit_lib, config_protocol, fabric_key,
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@ -2681,6 +3013,11 @@ static int load_and_update_submodule_memory_modules_from_fabric_key(
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return status;
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}
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/* TODO: Create the nets for the new list of configurable children */
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status = rebuild_submodule_configurable_children_nets(
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module_manager, module_id, circuit_lib, config_protocol);
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if (status == CMD_EXEC_FATAL_ERROR) {
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return status;
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}
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return status;
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}
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