e60777d23e
Use Bitstream Setting XML
2024-07-26 01:36:49 -07:00
2ef362d53d
Init support overwriting bitstream
2024-07-25 17:40:46 -07:00
1513ea749b
[core] supporting clk spine on the same direction
2024-07-16 22:12:51 -07:00
18d12109fb
[core] fixed a critical bug where cb port name using index is not considered on clock network entry
2024-07-16 17:42:21 -07:00
c1f46c448a
[core] fixed a critical bug where clock network entry is on a CHANY
2024-07-16 17:04:44 -07:00
cbd10e1222
[core] fixed a bug where tile module's global port is not derived from dedicated clock network
2024-07-16 16:58:21 -07:00
f607987386
[core] patch the out-of-range in clock rr nodes
2024-07-16 16:45:55 -07:00
c96f899c53
[core] code format
2024-07-10 15:07:26 -07:00
a4538fb25b
[core] now supports to_pin in building clock network for internal driver
2024-07-10 15:01:18 -07:00
215de8eb93
[core] code format
2024-07-10 14:17:22 -07:00
f5ba43e392
[core] fixed a bug where rst internal net is used to wire global ports of fpga fabric in verilog testbench
2024-07-10 14:16:24 -07:00
213914e4ac
[core] code format
2024-07-10 12:23:57 -07:00
48e159dd8d
[core] fixed a bug where internal clock will be wired to fpga input pins in verilog testbenches
2024-07-10 12:23:15 -07:00
c6dd33a965
[core] fixed a bug when annotating global nets on OPIN
2024-07-10 11:59:25 -07:00
96bdcc8b35
[core] code format
2024-07-09 22:54:55 -07:00
27e29f949c
[core] fixed a bug where the pin idx of global net on rr graph is not well annotated
2024-07-09 22:53:12 -07:00
092b8b038f
[core] remove verbose out
2024-07-08 22:23:37 -07:00
04504e4d5d
[core] code format
2024-07-08 22:22:59 -07:00
1cdb1c5995
[core] fixed a bug on calculating subtile pins
2024-07-08 22:22:08 -07:00
fe06c2f2b1
[core] code format
2024-07-08 16:18:58 -07:00
db459b0e87
[core] add verbose outputs
2024-07-08 16:18:32 -07:00
e8f9deeeaf
[core] fixed a critical bug on computing pin index for subtile in clock taps
2024-07-08 16:12:20 -07:00
6dde383a7f
[core] debugging
2024-07-08 16:00:18 -07:00
8bca3d79be
[core] fixed a bug where tap points of clock network cannot reach perimeter cb
2024-07-08 15:17:24 -07:00
7bd60f5f7d
[core] support perimeter cb when identify pins of I/Os tiles
2024-07-08 12:39:54 -07:00
5c9c4d93c5
[core] typo
2024-07-08 10:46:47 -07:00
cdd477ad80
[core] remove restrictions on cb clock nodes
2024-07-08 10:14:39 -07:00
8449da0143
[core] typo
2024-07-07 23:36:13 -07:00
7996de3fe6
[core] now support perimeter cb in programmable clock network arch
2024-07-07 14:57:05 -07:00
703cbddc9e
[core] code format
2024-07-06 12:14:57 -07:00
6024e35f89
[core] fixed a bug
2024-07-05 18:50:14 -07:00
1f7fbfef64
[core] fixed a bug on inter-tile connections in top module
2024-07-05 18:19:22 -07:00
e95b264965
[core] debugging
2024-07-05 18:08:48 -07:00
cca9fb4756
[core] fixed a bug on bottom left tile organization
2024-07-05 17:55:19 -07:00
46d916f0a0
[core] fixed the bugs in fabric tile build-up
2024-07-05 16:59:08 -07:00
a41f437109
[core] now netlist look ok
2024-07-05 12:36:47 -07:00
283aa3a1c9
[core] debug
2024-07-05 12:21:17 -07:00
46e3b4b071
[core] debug
2024-07-05 11:50:41 -07:00
fdbc427f70
[core] debug
2024-07-05 11:17:05 -07:00
f6adca1545
[core] fixed a bug
2024-07-05 11:02:01 -07:00
1dc602a849
[core] syntax
2024-07-05 10:38:26 -07:00
266c2686d4
[core] adapt new gsb coordinate system
2024-07-05 10:32:33 -07:00
1f8c2436ef
[core] now constant_undriven_inputs are force to enable when perimeter_cb is selected
2024-07-04 20:46:38 -07:00
72ee39f178
[core] add new command line option 'constant_undriven_inputs'
2024-07-04 20:39:02 -07:00
4e21bbb3f1
[core] now support constant undriven local wires in verilog writer
2024-07-04 20:32:56 -07:00
1dd03d0fdd
[core] on a new feature to connect undriven pins to ground
2024-07-04 18:34:39 -07:00
6d798897fd
[lib] update vtr
2024-07-04 14:46:57 -07:00
f560fb8381
[core] more verbose
2024-07-04 14:27:17 -07:00
a8850d4f0f
[core] now verbose mode is applicable to more build top module cb instances
2024-07-04 14:22:30 -07:00
4b53e57c92
[core] fixed a bug
2024-07-04 13:33:04 -07:00
d2a68ff9c5
[core] now corner tile are considered as config child
2024-07-04 13:25:57 -07:00
b80ed8d15c
[core] fixed a bug
2024-07-04 12:58:16 -07:00
a3723b33b3
[core] fixed a minor bug
2024-07-04 12:52:29 -07:00
a717882304
[core] now when perimeter_cb is on, I/O pins can access three sides of routing tracks
2024-07-04 12:44:48 -07:00
724c14d1f7
[core] fixed a bug on build top module connections on perimeter gsb when cbs occur
2024-07-04 11:09:01 -07:00
550ce0c390
[core] fixed the bug on build gsb when cbs are on perimeters
2024-07-04 10:58:44 -07:00
bc94e08c77
[lib] update vtr and fixing some bugs in annotate gsb when perimeter_cb is enabled
2024-07-03 22:28:22 -07:00
a27325d987
[core] code format
2024-07-03 17:05:27 -07:00
f681c6a903
[core] update API call due to vtr upgrade
2024-07-03 17:04:06 -07:00
a85a6f1674
[core] code format
2024-07-01 17:57:10 -07:00
70428fd969
[lib] add sanity checks on global port name and clock network's global port name
2024-07-01 17:56:29 -07:00
3afb92d6a5
[core] code format
2024-06-30 22:48:15 -07:00
1fd974d544
[core] fixed a bug where clock network size cannot impact global port on top module
2024-06-29 17:35:47 -07:00
4f787a5cfc
[core] add more debugging message
2024-06-29 10:54:08 -07:00
5fa674be24
[core] fixed the bug on matching global net from pcf
2024-06-29 10:51:45 -07:00
8bc37080fa
[core] debuggging
2024-06-28 23:06:21 -07:00
1c69365938
[core] debugging
2024-06-28 18:17:38 -07:00
0de3ff3eb8
[core] debugging
2024-06-28 17:16:33 -07:00
e0b9f7860b
[core] fixed a bug where counter for gnets are not activated
2024-06-28 14:10:14 -07:00
5cfd23747b
[core] code format
2024-06-28 13:47:03 -07:00
f5b6774eb0
[core] add code comments and fixed some bugs
2024-06-28 12:21:33 -07:00
53ba2f0c29
[core] fixed a critical bug where some switching points are missing
2024-06-27 15:53:17 -07:00
5a7f618f29
[core] debugging
2024-06-27 15:44:17 -07:00
f4f487099d
[core] syntax
2024-06-27 15:07:48 -07:00
4185235a69
[core] now clock routing is based on tree expansion. Unused part can be disconnected
2024-06-27 15:02:20 -07:00
e75fd57af2
[core] refactor codes
2024-06-27 12:39:18 -07:00
7892c2340c
[core] add a new option 'disable_unused_trees' to route clock rr graph
2024-06-27 12:01:54 -07:00
6fceb81110
[core] code format
2024-06-27 10:19:40 -07:00
64a7a4ce26
[core] syntax
2024-06-27 10:19:14 -07:00
9ce552495a
[core] now internal drivers can be routed in dedicated clock network
2024-06-27 10:17:08 -07:00
ac1ad52795
[core] code format
2024-06-26 22:47:29 -07:00
5d0b0b9a8c
[core] now global nets mapping are applied to clock routing
2024-06-26 22:46:12 -07:00
d5d9531eec
[core] comment out buggy codes where global net mapping is not annotated in OpenFPGA
2024-06-26 21:52:45 -07:00
59be95b227
[core] code format
2024-06-26 17:58:26 -07:00
59404e5487
[core] add verbose output
2024-06-26 17:55:23 -07:00
576a861b8d
[core] now skip routing any unused clock tree. Only connect to desired clock pin at programmable blocks
2024-06-26 17:54:31 -07:00
3efa97b84e
[core] support coordinate on clock taps
2024-06-26 17:40:11 -07:00
fbece49047
[core] fixed a bug where unexpected OPINs are added as internal drivers
2024-06-25 12:07:19 -07:00
7bcbd8a88b
[core] code format
2024-06-25 11:44:50 -07:00
3b2c13402a
[core] syntax
2024-06-25 11:44:25 -07:00
31d4b4c402
[core] now support add internal drivers to clock tree
2024-06-25 11:27:22 -07:00
d2053db21c
[core] removing the restrictions on only 1 clock tree is supported in programmable clock network
2024-06-21 19:00:01 -07:00
2193f108ee
[core] add debugging messages
2024-06-21 18:42:35 -07:00
3f08b83b3a
[core] remove restrictions on 1 clock tree definition
2024-06-21 17:12:10 -07:00
ecd31955b1
[core] code format
2024-06-21 17:11:32 -07:00
486cd01c15
[core] now clock graph builder supports two types of switches
2024-06-21 16:54:22 -07:00
ad8ad25250
[core] format
2024-05-31 19:44:40 -07:00
93ebbef851
[core] fixed a bug
2024-05-31 19:42:50 -07:00
514ec2f02e
[core] code format
2024-05-31 18:02:46 -07:00
2d10be9edb
[core] code comments
2024-05-31 18:00:24 -07:00
f9cd01636d
[core] fixed the bug where there is only 1 routing trace for a net which should be ignored (due to treated as global). This net should not be ignored unless there are >1 routing traces on the top-level pb. Then we can merge one.
2024-05-31 17:57:36 -07:00
212abecc27
[core] syntax
2024-05-31 17:41:49 -07:00
348d474bfd
[core] more debuggin messages
2024-05-31 17:40:19 -07:00
c565264e7d
[core] more debuggin messages
2024-05-31 17:14:42 -07:00
6dc31bf892
[core] fixed a bug on missing net sync up during repack
2024-05-31 16:53:59 -07:00
5b35f567d2
[core] detailed messages to trace why some nets are no sync
2024-05-31 16:00:10 -07:00
5adc1be204
[core] syntax
2024-05-31 15:50:27 -07:00
a9ccc277bd
[core] more debugging message
2024-05-31 15:49:34 -07:00
937e279c59
[core] adding more debugging messages
2024-05-31 15:43:51 -07:00
7a7fc679a8
[core] enable more debugging message in repacker
2024-05-31 14:52:59 -07:00
edb50f1b4d
[core] update debug messages
2024-05-31 14:37:46 -07:00
48c0b4b219
[core] fixed a bug where net name is not shown correctly on wire LUTs
2024-05-31 12:45:12 -07:00
74e94b855e
[core] fixed a bug where gsb OPIN name does not match the switch block module
2024-05-29 10:27:10 -07:00
52ae484a7c
[core] fixed a bug on messed up wire connections for OPINs
2024-05-20 13:50:31 -07:00
ca6e2f9831
[core] code format
2024-05-20 13:41:35 -07:00
4a791249bf
[core] fixed a bug on requirement wire model for direction connection which is part of a cb
2024-05-20 12:52:07 -07:00
b554a3d855
[core] code format
2024-05-19 17:24:38 -07:00
56aaa6a1f4
[core] sytax
2024-05-19 17:23:48 -07:00
065d77c679
[core] supporting opin connection to cb in tiles
2024-05-19 17:04:24 -07:00
9079056871
[core] now connect OPIN to CB in top-level module
2024-05-19 14:27:36 -07:00
918bf79ca3
[core] update vtr and developing caches for OPIN lists just for connection blocks
2024-05-19 14:10:00 -07:00
772da3006b
[core] code format
2024-05-18 22:19:17 -07:00
304f34525e
[core] syntax
2024-05-18 22:17:52 -07:00
b533ea4060
[core] now cb module include OPIN nodes
2024-05-18 22:00:02 -07:00
926b9e9739
[core] code format
2024-05-18 12:33:19 -07:00
3b93bea3d1
[core] syntax
2024-05-18 12:29:38 -07:00
0d8c21ca84
[core] add new type 'part_of_cb' for tile direct connections
2024-05-17 18:59:53 -07:00
7848bdaeac
[core] code format
2024-05-09 22:50:49 -07:00
5f37d63061
[core] fixed a bug where incoming edges are not built after loading rr_graph in vpr
2024-05-09 19:38:26 -07:00
7dc2c4951c
[core] add missing header required by clang-11+
2024-05-05 21:56:56 -07:00
3d8107487c
[core] code format
2024-05-03 10:21:39 -07:00
c7501cb9b7
[core] fixed the bugs when there are module renaming
2024-05-03 10:20:19 -07:00
f41a5e8b89
[core] fixed some bugs
2024-05-02 22:49:06 -07:00
c557b0104a
[core] avoid unwanted tab
2024-05-02 21:34:12 -07:00
b85ec28eb8
[core] code format
2024-05-02 21:17:17 -07:00
d3b1e562ad
[core] fixed some bugs on format
2024-05-02 21:11:20 -07:00
bf24382f19
[core] code format
2024-05-02 18:33:07 -07:00
a2fb84dfa9
[core] add fabric hierarchy writer
2024-05-02 18:30:20 -07:00
4d3447f773
[core] rework fabric hierarchy writer
2024-05-02 18:05:38 -07:00
dd577e37e0
LUTRAM Support ( #1595 )
...
* BRAM preload data - generic way to extract data from design
* Add docs and support special __layout__ case
* Add test
* Fix warning
* Change none-fabric to non-fabric
* LUTRAM Support Phase 1
* Add Test
* Add more protocol checking to enable LUTRAM feature
* Move the config setting under config protocol
* Revert any changes
---------
Co-authored-by: chungshien-chai <chungshien.chai@gmail.com>
2024-04-19 14:46:38 -07:00
08bd6d00d3
[core] code format
2024-04-11 15:04:08 -07:00
79970719b4
[core] fixed a bug where regex breaks
2024-04-11 14:59:14 -07:00
f63ea06c4e
[core] now support regular expression in module name for fabric pin physical location output
2024-04-11 14:30:27 -07:00
5960cc14aa
[core] fixed a bug
2024-04-11 13:04:47 -07:00
6f94399767
[core] code format
2024-04-10 22:53:52 -07:00
971f0e8838
[core] add a new option '--show_invalid_side'
2024-04-10 22:52:36 -07:00
58708ff727
[core] syntax
2024-04-10 20:08:02 -07:00
435e83c530
[core] add port side to tile ports
2024-04-10 17:38:02 -07:00
f9f7d42d93
[core] add port side attribute and set them when buidling grid/cb/sb modules
2024-04-10 17:10:06 -07:00
d156de060e
[core] adding pin side attribute to module manager
2024-04-10 16:19:28 -07:00
chungshien-chai
tangxifan
chungshien