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[core] fixed a bug where internal clock will be wired to fpga input pins in verilog testbenches

This commit is contained in:
tangxifan 2024-07-10 12:23:15 -07:00
parent c6dd33a965
commit 48e159dd8d
4 changed files with 21 additions and 3 deletions
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4
openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp
View File

@ -65,6 +65,8 @@ static void print_verilog_preconfig_top_module_ports(
/* The block may be renamed as it contains special characters which violate
* Verilog syntax */
if (true == netlist_annotation.is_block_renamed(atom_blk)) {
VTR_LOG("Replace pin name '%s' with '%s' as it is renamed to comply verilog syntax\n", block_name.c_str(),
netlist_annotation.block_name(atom_blk).c_str());
block_name = netlist_annotation.block_name(atom_blk);
}
/* For output block, remove the prefix which is added by VPR */
@ -445,7 +447,7 @@ int print_verilog_preconfig_top_module(
/* Connect FPGA top module global ports to constant or benchmark global
* signals! */
status = print_verilog_preconfig_top_module_connect_global_ports(
fp, module_manager, core_module, pin_constraints, global_ports,
fp, module_manager, core_module, pin_constraints, atom_ctx, netlist_annotation, global_ports,
benchmark_clock_port_names,
std::string(FORMAL_VERIFICATION_TOP_MODULE_PORT_POSTFIX));
if (CMD_EXEC_FATAL_ERROR == status) {

16
openfpga/src/fpga_verilog/verilog_preconfig_top_module_utils.cpp
View File

@ -57,6 +57,8 @@ void print_verilog_preconfig_top_module_internal_wires(
int print_verilog_preconfig_top_module_connect_global_ports(
std::fstream &fp, const ModuleManager &module_manager,
const ModuleId &top_module, const PinConstraints &pin_constraints,
const AtomContext& atom_ctx,
const VprNetlistAnnotation &netlist_annotation,
const FabricGlobalPortInfo &fabric_global_ports,
const std::vector<std::string> &benchmark_clock_port_names,
const std::string &port_postfix) {
@ -121,7 +123,19 @@ int print_verilog_preconfig_top_module_connect_global_ports(
}
clock_name_to_connect = benchmark_clock_port_names[pin_id];
}
/* The clock name must be a valid primary input. Otherwise, it could be a signal generated by internal logics, e.g., clb */
AtomBlockId atom_blk = atom_ctx.nlist.find_block(clock_name_to_connect);
if ((AtomBlockType::INPAD != atom_ctx.nlist.block_type(atom_blk))) {
VTR_LOG("Global net '%s' is not a primary input of the netlist (which could a signal generated by internal logic). Will not wire it to any FPGA primary input pin\n", clock_name_to_connect.c_str());
continue;
}
/* The block may be renamed as it contains special characters which violate
* Verilog syntax */
if (true == netlist_annotation.is_block_renamed(atom_blk)) {
VTR_LOG("Replace pin name '%s' with '%s' as it is renamed to comply verilog syntax\n", clock_name_to_connect.c_str(),
netlist_annotation.block_name(atom_blk).c_str());
clock_name_to_connect = netlist_annotation.block_name(atom_blk);
}
BasicPort benchmark_clock_pin(clock_name_to_connect, 1);
print_verilog_wire_connection(fp, module_clock_pin, benchmark_clock_pin,
false);

2
openfpga/src/fpga_verilog/verilog_preconfig_top_module_utils.h
View File

@ -35,6 +35,8 @@ void print_verilog_preconfig_top_module_internal_wires(
int print_verilog_preconfig_top_module_connect_global_ports(
std::fstream &fp, const ModuleManager &module_manager,
const ModuleId &top_module, const PinConstraints &pin_constraints,
const AtomContext& atom_ctx,
const VprNetlistAnnotation &netlist_annotation,
const FabricGlobalPortInfo &fabric_global_ports,
const std::vector<std::string> &benchmark_clock_port_names,
const std::string &port_postfix);

2
openfpga/src/fpga_verilog/verilog_testbench_io_connection.cpp
View File

@ -90,7 +90,7 @@ int print_verilog_testbench_io_connection(
/* Connect FPGA top module global ports to constant or benchmark global
* signals! */
status = print_verilog_preconfig_top_module_connect_global_ports(
fp, module_manager, core_module, pin_constraints, global_ports,
fp, module_manager, core_module, pin_constraints, atom_ctx, netlist_annotation, global_ports,
benchmark_clock_port_names, std::string());
if (CMD_EXEC_FATAL_ERROR == status) {
return status;