diff --git a/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp b/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp
index 5c1c703e2..8e4a14170 100644
--- a/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp
+++ b/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp
@@ -65,6 +65,8 @@ static void print_verilog_preconfig_top_module_ports(
     /* The block may be renamed as it contains special characters which violate
      * Verilog syntax */
     if (true == netlist_annotation.is_block_renamed(atom_blk)) {
+      VTR_LOG("Replace pin name '%s' with '%s' as it is renamed to comply verilog syntax\n", block_name.c_str(),
+              netlist_annotation.block_name(atom_blk).c_str());
       block_name = netlist_annotation.block_name(atom_blk);
     }
     /* For output block, remove the prefix which is added by VPR */
@@ -445,7 +447,7 @@ int print_verilog_preconfig_top_module(
   /* Connect FPGA top module global ports to constant or benchmark global
    * signals! */
   status = print_verilog_preconfig_top_module_connect_global_ports(
-    fp, module_manager, core_module, pin_constraints, global_ports,
+    fp, module_manager, core_module, pin_constraints, atom_ctx, netlist_annotation, global_ports,
     benchmark_clock_port_names,
     std::string(FORMAL_VERIFICATION_TOP_MODULE_PORT_POSTFIX));
   if (CMD_EXEC_FATAL_ERROR == status) {
diff --git a/openfpga/src/fpga_verilog/verilog_preconfig_top_module_utils.cpp b/openfpga/src/fpga_verilog/verilog_preconfig_top_module_utils.cpp
index 944506c89..2649c2c64 100644
--- a/openfpga/src/fpga_verilog/verilog_preconfig_top_module_utils.cpp
+++ b/openfpga/src/fpga_verilog/verilog_preconfig_top_module_utils.cpp
@@ -57,6 +57,8 @@ void print_verilog_preconfig_top_module_internal_wires(
 int print_verilog_preconfig_top_module_connect_global_ports(
   std::fstream &fp, const ModuleManager &module_manager,
   const ModuleId &top_module, const PinConstraints &pin_constraints,
+  const AtomContext& atom_ctx,
+  const VprNetlistAnnotation &netlist_annotation,
   const FabricGlobalPortInfo &fabric_global_ports,
   const std::vector<std::string> &benchmark_clock_port_names,
   const std::string &port_postfix) {
@@ -121,7 +123,19 @@ int print_verilog_preconfig_top_module_connect_global_ports(
           }
           clock_name_to_connect = benchmark_clock_port_names[pin_id];
         }
-
+        /* The clock name must be a valid primary input. Otherwise, it could be a signal generated by internal logics, e.g., clb */
+        AtomBlockId atom_blk = atom_ctx.nlist.find_block(clock_name_to_connect);
+        if ((AtomBlockType::INPAD != atom_ctx.nlist.block_type(atom_blk))) {
+          VTR_LOG("Global net '%s' is not a primary input of the netlist (which could a signal generated by internal logic). Will not wire it to any FPGA primary input pin\n", clock_name_to_connect.c_str());
+          continue;
+        }
+        /* The block may be renamed as it contains special characters which violate
+         * Verilog syntax */
+        if (true == netlist_annotation.is_block_renamed(atom_blk)) {
+          VTR_LOG("Replace pin name '%s' with '%s' as it is renamed to comply verilog syntax\n", clock_name_to_connect.c_str(),
+                  netlist_annotation.block_name(atom_blk).c_str());
+          clock_name_to_connect = netlist_annotation.block_name(atom_blk);
+        }
         BasicPort benchmark_clock_pin(clock_name_to_connect, 1);
         print_verilog_wire_connection(fp, module_clock_pin, benchmark_clock_pin,
                                       false);
diff --git a/openfpga/src/fpga_verilog/verilog_preconfig_top_module_utils.h b/openfpga/src/fpga_verilog/verilog_preconfig_top_module_utils.h
index 55c85eadd..a0eb1616f 100644
--- a/openfpga/src/fpga_verilog/verilog_preconfig_top_module_utils.h
+++ b/openfpga/src/fpga_verilog/verilog_preconfig_top_module_utils.h
@@ -35,6 +35,8 @@ void print_verilog_preconfig_top_module_internal_wires(
 int print_verilog_preconfig_top_module_connect_global_ports(
   std::fstream &fp, const ModuleManager &module_manager,
   const ModuleId &top_module, const PinConstraints &pin_constraints,
+  const AtomContext& atom_ctx,
+  const VprNetlistAnnotation &netlist_annotation,
   const FabricGlobalPortInfo &fabric_global_ports,
   const std::vector<std::string> &benchmark_clock_port_names,
   const std::string &port_postfix);
diff --git a/openfpga/src/fpga_verilog/verilog_testbench_io_connection.cpp b/openfpga/src/fpga_verilog/verilog_testbench_io_connection.cpp
index 30018e400..41ce502c8 100644
--- a/openfpga/src/fpga_verilog/verilog_testbench_io_connection.cpp
+++ b/openfpga/src/fpga_verilog/verilog_testbench_io_connection.cpp
@@ -90,7 +90,7 @@ int print_verilog_testbench_io_connection(
   /* Connect FPGA top module global ports to constant or benchmark global
    * signals! */
   status = print_verilog_preconfig_top_module_connect_global_ports(
-    fp, module_manager, core_module, pin_constraints, global_ports,
+    fp, module_manager, core_module, pin_constraints, atom_ctx, netlist_annotation, global_ports,
     benchmark_clock_port_names, std::string());
   if (CMD_EXEC_FATAL_ERROR == status) {
     return status;