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[core] code format

This commit is contained in:
tangxifan 2024-07-03 17:05:27 -07:00
parent f681c6a903
commit a27325d987
1 changed files with 12 additions and 15 deletions
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27
openfpga/src/annotation/append_clock_rr_graph.cpp
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@ -152,9 +152,7 @@ static void add_rr_graph_block_clock_nodes(
static void add_rr_graph_clock_nodes(
RRGraphBuilder& rr_graph_builder, RRClockSpatialLookup& clk_rr_lookup,
const RRGraphView& rr_graph_view, const DeviceGrid& grids,
const size_t& layer,
const bool& perimeter_cb,
const bool& through_channel,
const size_t& layer, const bool& perimeter_cb, const bool& through_channel,
const ClockNetwork& clk_ntwk, const bool& verbose) {
/* Pre-allocate memory: Must do otherwise data will be messed up! */
clk_rr_lookup.reserve_nodes(grids.width(), grids.height(),
@ -732,10 +730,9 @@ static int add_rr_graph_opin2clk_edges(
static void add_rr_graph_clock_edges(
RRGraphBuilder& rr_graph_builder, size_t& num_edges_to_create,
const RRClockSpatialLookup& clk_rr_lookup, const RRGraphView& rr_graph_view,
const DeviceGrid& grids, const size_t& layer,
const bool& perimeter_cb,
const bool& through_channel,
const ClockNetwork& clk_ntwk, const bool& verbose) {
const DeviceGrid& grids, const size_t& layer, const bool& perimeter_cb,
const bool& through_channel, const ClockNetwork& clk_ntwk,
const bool& verbose) {
/* Add edges which is driven by X-direction clock routing tracks */
for (size_t iy = 0; iy < grids.height() - 1; ++iy) {
for (size_t ix = 1; ix < grids.width() - 1; ++ix) {
@ -798,7 +795,8 @@ int append_clock_rr_graph(DeviceContext& vpr_device_ctx,
/* Estimate the number of nodes and pre-allocate */
size_t orig_num_nodes = vpr_device_ctx.rr_graph.num_nodes();
size_t num_clock_nodes = estimate_clock_rr_graph_num_nodes(
vpr_device_ctx.grid, 0, vpr_device_ctx.arch->perimeter_cb, vpr_device_ctx.arch->through_channel, clk_ntwk);
vpr_device_ctx.grid, 0, vpr_device_ctx.arch->perimeter_cb,
vpr_device_ctx.arch->through_channel, clk_ntwk);
vpr_device_ctx.rr_graph_builder.unlock_storage();
vpr_device_ctx.rr_graph_builder.reserve_nodes(num_clock_nodes +
orig_num_nodes);
@ -808,11 +806,10 @@ int append_clock_rr_graph(DeviceContext& vpr_device_ctx,
num_clock_nodes, (float)(num_clock_nodes / orig_num_nodes));
/* Add clock nodes */
add_rr_graph_clock_nodes(vpr_device_ctx.rr_graph_builder, clk_rr_lookup,
vpr_device_ctx.rr_graph, vpr_device_ctx.grid, 0,
vpr_device_ctx.arch->perimeter_cb,
vpr_device_ctx.arch->through_channel, clk_ntwk,
verbose);
add_rr_graph_clock_nodes(
vpr_device_ctx.rr_graph_builder, clk_rr_lookup, vpr_device_ctx.rr_graph,
vpr_device_ctx.grid, 0, vpr_device_ctx.arch->perimeter_cb,
vpr_device_ctx.arch->through_channel, clk_ntwk, verbose);
VTR_LOGV(verbose,
"Added %lu clock nodes to routing "
"resource graph.\n",
@ -826,8 +823,8 @@ int append_clock_rr_graph(DeviceContext& vpr_device_ctx,
vpr_device_ctx.rr_graph_builder, num_clock_edges,
static_cast<const RRClockSpatialLookup&>(clk_rr_lookup),
vpr_device_ctx.rr_graph, vpr_device_ctx.grid, 0,
vpr_device_ctx.arch->perimeter_cb,
vpr_device_ctx.arch->through_channel, clk_ntwk, verbose);
vpr_device_ctx.arch->perimeter_cb, vpr_device_ctx.arch->through_channel,
clk_ntwk, verbose);
VTR_LOGV(verbose,
"Added %lu clock edges to routing "
"resource graph.\n",