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[core] fixed a bug on requirement wire model for direction connection which is part of a cb

This commit is contained in:
tangxifan 2024-05-20 12:52:07 -07:00
parent b15e169490
commit 4a791249bf
1 changed files with 10 additions and 1 deletions
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11
openfpga/src/annotation/annotate_rr_graph.cpp
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@ -704,7 +704,7 @@ static void annotate_direct_circuit_models(
}
/* Check the circuit model type */
if (CIRCUIT_MODEL_WIRE !=
if (openfpga_arch.arch_direct.type(direct_id) != e_direct_type::PART_OF_CB && CIRCUIT_MODEL_WIRE !=
openfpga_arch.circuit_lib.model_type(circuit_model)) {
VTR_LOG_ERROR(
"Require circuit model type '%s' for a direct connection '%s'!\nPlease "
@ -712,6 +712,15 @@ static void annotate_direct_circuit_models(
CIRCUIT_MODEL_TYPE_STRING[CIRCUIT_MODEL_WIRE], direct_name.c_str());
exit(1);
}
if (openfpga_arch.arch_direct.type(direct_id) == e_direct_type::PART_OF_CB && CIRCUIT_MODEL_MUX !=
openfpga_arch.circuit_lib.model_type(circuit_model)) {
VTR_LOG_ERROR(
"Require circuit model type '%s' for a direct connection '%s'!\nPlease "
"check your OpenFPGA architecture XML!\n",
CIRCUIT_MODEL_TYPE_STRING[CIRCUIT_MODEL_MUX], direct_name.c_str());
exit(1);
}
/* Now update the device annotation */
vpr_device_annotation.add_direct_annotation(idirect, direct_id);