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[core] now supports to_pin in building clock network for internal driver

This commit is contained in:
tangxifan 2024-07-10 15:01:18 -07:00
parent b2fc47a12a
commit a4538fb25b
4 changed files with 36 additions and 14 deletions
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30
libs/libclkarchopenfpga/src/base/clock_network.cpp
View File

@ -366,7 +366,7 @@ std::string ClockNetwork::internal_driver_from_pin(
return internal_driver_from_pins_[int_driver_id];
}
std::string ClockNetwork::internal_driver_to_pin(
BasicPort ClockNetwork::internal_driver_to_pin(
const ClockInternalDriverId& int_driver_id) const {
VTR_ASSERT(valid_internal_driver_id(int_driver_id));
return internal_driver_to_pins_[int_driver_id];
@ -530,9 +530,25 @@ std::vector<std::string> ClockNetwork::tree_flatten_tap_to_ports(
}
std::vector<std::string> ClockNetwork::flatten_internal_driver_from_pin(
const ClockInternalDriverId& int_driver_id) const {
const ClockInternalDriverId& int_driver_id,
const ClockTreePinId& clk_pin_id) const {
std::vector<std::string> flatten_taps;
std::string tap_name = internal_driver_port(int_driver_id);
BasicPort des_pin = internal_driver_to_pin(int_driver_id);
if (!des_pin.is_valid()) {
VTR_LOG_ERROR("Invalid internal driver destination port name '%s' whose index is not valid\n",
des_pin.to_verilog_string().c_str());
exit(1);
}
if (des_pin.get_width() != 1) {
VTR_LOG_ERROR("Invalid internal driver destination port name '%s' whose width is not 1\n",
des_pin.to_verilog_string().c_str());
exit(1);
}
if (des_pin.get_lsb() != size_t(clk_pin_id)) {
return flatten_taps;
}
std::string tap_name = internal_driver_from_pin(int_driver_id);
StringToken tokenizer(tap_name);
std::vector<std::string> pin_tokens = tokenizer.split(".");
if (pin_tokens.size() != 2) {
@ -775,10 +791,12 @@ ClockInternalDriverId ClockNetwork::add_spine_switch_point_internal_driver(
const std::string& int_driver_to_port) {
VTR_ASSERT(valid_spine_id(spine_id));
VTR_ASSERT(valid_spine_switch_point_id(spine_id, switch_point_id));
/* Parse ports */
PortParser to_pin_parser(int_driver_to_port);
/* Find any existing id for the driver port */
for (ClockInternalDriverId int_driver_id : internal_driver_ids_) {
if (internal_driver_from_pins_[int_driver_id] == int_driver_from_port
&& internal_driver_to_pins_[int_driver_id] == int_driver_to_port) {
&& internal_driver_to_pins_[int_driver_id] == to_pin_parser.port()) {
spine_switch_internal_drivers_[spine_id][size_t(switch_point_id)]
.push_back(int_driver_id);
return int_driver_id;
@ -788,8 +806,8 @@ ClockInternalDriverId ClockNetwork::add_spine_switch_point_internal_driver(
ClockInternalDriverId int_driver_id =
ClockInternalDriverId(internal_driver_ids_.size());
internal_driver_ids_.push_back(int_driver_id);
internal_driver_from_pins_.push_back(int_driver_port_from_port);
internal_driver_to_pins_.push_back(int_driver_port_to_port);
internal_driver_from_pins_.push_back(int_driver_from_port);
internal_driver_to_pins_.push_back(to_pin_parser.port());
spine_switch_internal_drivers_[spine_id][size_t(switch_point_id)].push_back(
int_driver_id);
return int_driver_id;

7
libs/libclkarchopenfpga/src/base/clock_network.h
View File

@ -138,8 +138,9 @@ class ClockNetwork {
std::string internal_driver_from_pin(
const ClockInternalDriverId& int_driver_id) const;
std::vector<std::string> flatten_internal_driver_from_pin(
const ClockInternalDriverId& int_driver_id) const;
std::string internal_driver_to_pin(
const ClockInternalDriverId& int_driver_id,
const ClockTreePinId& clk_pin_id) const;
BasicPort internal_driver_to_pin(
const ClockInternalDriverId& int_driver_id) const;
/* Return the original list of tap pins that is in storage; useful for parsers
@ -320,7 +321,7 @@ class ClockNetwork {
vtr::vector<ClockInternalDriverId, ClockInternalDriverId>
internal_driver_ids_;
vtr::vector<ClockInternalDriverId, std::string> internal_driver_from_pins_;
vtr::vector<ClockInternalDriverId, std::string> internal_driver_to_pins_;
vtr::vector<ClockInternalDriverId, BasicPort> internal_driver_to_pins_;
/* Basic information about tap */
vtr::vector<ClockTapId, ClockTapId> tap_ids_;
vtr::vector<ClockTapId, BasicPort> tap_from_ports_;

2
libs/libclkarchopenfpga/src/io/write_xml_clock_network.cpp
View File

@ -130,7 +130,7 @@ static int write_xml_clock_spine_switch_point(
clk_ntwk.internal_driver_from_pin(int_driver_id).c_str());
write_xml_attribute(
fp, XML_CLOCK_SPINE_SWITCH_POINT_INTERNAL_DRIVER_ATTRIBUTE_TO_PIN,
clk_ntwk.internal_driver_to_pin(int_driver_id).c_str());
clk_ntwk.internal_driver_to_pin(int_driver_id).to_verilog_string().c_str());
fp << "/>"
<< "\n";
}

11
openfpga/src/annotation/append_clock_rr_graph.cpp
View File

@ -590,11 +590,13 @@ static void try_find_and_add_clock_opin2track_node(
std::vector<RRNodeId>& opin_nodes, const DeviceGrid& grids,
const RRGraphView& rr_graph_view, const size_t& layer,
const vtr::Point<int>& grid_coord, const e_side& pin_side,
const ClockNetwork& clk_ntwk, const ClockInternalDriverId& int_driver_id) {
const ClockNetwork& clk_ntwk,
const ClockTreePinId& clk_pin,
const ClockInternalDriverId& int_driver_id) {
t_physical_tile_type_ptr grid_type = grids.get_physical_type(
t_physical_tile_loc(grid_coord.x(), grid_coord.y(), layer));
for (std::string tap_pin_name :
clk_ntwk.flatten_internal_driver_port(int_driver_id)) {
clk_ntwk.flatten_internal_driver_from_pin(int_driver_id, clk_pin)) {
/* tap pin name could be 'io[5:5].a2f[0]' */
int grid_pin_idx = find_physical_tile_pin_index(grid_type, tap_pin_name);
if (grid_pin_idx == grid_type->num_pins) {
@ -636,6 +638,7 @@ static std::vector<RRNodeId> find_clock_opin2track_node(
const DeviceGrid& grids, const RRGraphView& rr_graph_view,
const size_t& layer, const vtr::Point<int>& sb_coord,
const ClockNetwork& clk_ntwk,
const ClockTreePinId& clk_pin,
const std::vector<ClockInternalDriverId>& int_driver_ids) {
std::vector<RRNodeId> opin_nodes;
/* Find opins from
@ -660,7 +663,7 @@ static std::vector<RRNodeId> find_clock_opin2track_node(
for (ClockInternalDriverId int_driver_id : int_driver_ids) {
try_find_and_add_clock_opin2track_node(opin_nodes, grids, rr_graph_view,
layer, grid_coord, grid_side,
clk_ntwk, int_driver_id);
clk_ntwk, clk_pin, int_driver_id);
}
}
}
@ -709,7 +712,7 @@ static int add_rr_graph_opin2clk_edges(
clk_ntwk.spine_switch_point_internal_drivers(ispine,
switch_point_id);
for (RRNodeId src_node : find_clock_opin2track_node(
grids, rr_graph_view, layer, src_coord, clk_ntwk,
grids, rr_graph_view, layer, src_coord, clk_ntwk, ipin,
int_driver_ids)) {
/* Create edges */
VTR_ASSERT(rr_graph_view.valid_node(des_node));