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[core] code format

This commit is contained in:
tangxifan 2024-07-10 14:17:22 -07:00
parent f5ba43e392
commit 215de8eb93
1 changed files with 1 additions and 1 deletions
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openfpga/src/fpga_verilog/verilog_preconfig_top_module_utils.cpp
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@ -191,7 +191,7 @@ int print_verilog_preconfig_top_module_connect_global_ports(
"verilog syntax\n",
constrained_net_name.c_str(),
netlist_annotation.block_name(atom_blk).c_str());
constrained_net_name = netlist_annotation.block_name(atom_blk);
constrained_net_name = netlist_annotation.block_name(atom_blk);
}
BasicPort benchmark_pin(constrained_net_name, 1);
print_verilog_wire_connection(fp, module_global_pin, benchmark_pin,