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[core] code format

This commit is contained in:
tangxifan 2024-06-26 17:58:26 -07:00
parent 59404e5487
commit 59be95b227
4 changed files with 115 additions and 82 deletions
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79
libs/libclkarchopenfpga/src/base/clock_network.cpp
View File

@ -363,7 +363,8 @@ std::string ClockNetwork::tap_to_port(const ClockTapId& tap_id) const {
return tap_to_ports_[tap_id];
}
ClockNetwork::e_tap_type ClockNetwork::tap_type(const ClockTapId& tap_id) const {
ClockNetwork::e_tap_type ClockNetwork::tap_type(
const ClockTapId& tap_id) const {
VTR_ASSERT(valid_tap_id(tap_id));
/* If not a region, it is a default type covering all the coordinates*/
if (tap_bbs_[tap_id] == empty_tap_bb_) {
@ -378,56 +379,62 @@ ClockNetwork::e_tap_type ClockNetwork::tap_type(const ClockTapId& tap_id) const
size_t ClockNetwork::tap_x(const ClockTapId& tap_id) const {
VTR_ASSERT(tap_type(tap_id) == ClockNetwork::e_tap_type::SINGLE);
return tap_bbs_[tap_id].xmin();
return tap_bbs_[tap_id].xmin();
}
size_t ClockNetwork::tap_y(const ClockTapId& tap_id) const {
VTR_ASSERT(tap_type(tap_id) == ClockNetwork::e_tap_type::SINGLE);
return tap_bbs_[tap_id].ymin();
return tap_bbs_[tap_id].ymin();
}
vtr::Rect<size_t> ClockNetwork::tap_bounding_box(const ClockTapId& tap_id) const {
vtr::Rect<size_t> ClockNetwork::tap_bounding_box(
const ClockTapId& tap_id) const {
VTR_ASSERT(tap_type(tap_id) == ClockNetwork::e_tap_type::REGION);
return tap_bbs_[tap_id];
return tap_bbs_[tap_id];
}
size_t ClockNetwork::tap_step_x(const ClockTapId& tap_id) const {
VTR_ASSERT(tap_type(tap_id) == ClockNetwork::e_tap_type::REGION);
return tap_bb_steps_[tap_id].x();
return tap_bb_steps_[tap_id].x();
}
size_t ClockNetwork::tap_step_y(const ClockTapId& tap_id) const {
VTR_ASSERT(tap_type(tap_id) == ClockNetwork::e_tap_type::REGION);
return tap_bb_steps_[tap_id].y();
return tap_bb_steps_[tap_id].y();
}
bool ClockNetwork::valid_tap_coord_in_bb(const ClockTapId& tap_id, const vtr::Point<size_t>& tap_coord) const {
bool ClockNetwork::valid_tap_coord_in_bb(
const ClockTapId& tap_id, const vtr::Point<size_t>& tap_coord) const {
VTR_ASSERT(valid_tap_id(tap_id));
if (tap_type(tap_id) == ClockNetwork::e_tap_type::ALL) {
return true;
}
if (tap_type(tap_id) == ClockNetwork::e_tap_type::SINGLE && tap_bbs_[tap_id].strictly_contains(tap_coord)) {
if (tap_type(tap_id) == ClockNetwork::e_tap_type::SINGLE &&
tap_bbs_[tap_id].strictly_contains(tap_coord)) {
return true;
}
if (tap_type(tap_id) == ClockNetwork::e_tap_type::REGION && tap_bbs_[tap_id].strictly_contains(tap_coord)) {
if (tap_type(tap_id) == ClockNetwork::e_tap_type::REGION &&
tap_bbs_[tap_id].strictly_contains(tap_coord)) {
/* Check if steps are considered, coords still matches */
bool x_in_bb = false;
for (size_t ix = tap_bbs_[tap_id].xmin(); ix < tap_bbs_[tap_id].xmax(); ix = ix + tap_bb_steps_[tap_id].x()) {
for (size_t ix = tap_bbs_[tap_id].xmin(); ix < tap_bbs_[tap_id].xmax();
ix = ix + tap_bb_steps_[tap_id].x()) {
if (tap_coord.x() == ix) {
x_in_bb = true;
break;
}
}
}
/* Early exit */
if (!x_in_bb) {
return false;
}
bool y_in_bb = false;
for (size_t iy = tap_bbs_[tap_id].ymin(); iy < tap_bbs_[tap_id].ymax(); iy = iy + tap_bb_steps_[tap_id].y()) {
for (size_t iy = tap_bbs_[tap_id].ymin(); iy < tap_bbs_[tap_id].ymax();
iy = iy + tap_bb_steps_[tap_id].y()) {
if (tap_coord.y() == iy) {
y_in_bb = true;
break;
}
}
}
if (y_in_bb && x_in_bb) {
return true;
@ -437,7 +444,8 @@ bool ClockNetwork::valid_tap_coord_in_bb(const ClockTapId& tap_id, const vtr::Po
}
std::vector<std::string> ClockNetwork::tree_flatten_tap_to_ports(
const ClockTreeId& tree_id, const ClockTreePinId& clk_pin_id, const vtr::Point<size_t>& tap_coord) const {
const ClockTreeId& tree_id, const ClockTreePinId& clk_pin_id,
const vtr::Point<size_t>& tap_coord) const {
VTR_ASSERT(valid_tree_id(tree_id));
std::vector<std::string> flatten_taps;
for (ClockTapId tap_id : tree_taps_[tree_id]) {
@ -459,7 +467,7 @@ std::vector<std::string> ClockNetwork::tree_flatten_tap_to_ports(
if (from_port.get_lsb() != size_t(clk_pin_id)) {
continue;
}
/* Filter out unmatched coordinates */
/* Filter out unmatched coordinates */
if (!valid_tap_coord_in_bb(tap_id, tap_coord)) {
continue;
}
@ -761,7 +769,8 @@ ClockTapId ClockNetwork::add_tree_tap(const ClockTreeId& tree_id,
const std::string& from_port,
const std::string& to_port) {
VTR_ASSERT(valid_tree_id(tree_id));
/* TODO: Consider find existing tap template and avoid duplication in storage */
/* TODO: Consider find existing tap template and avoid duplication in storage
*/
ClockTapId tap_id = ClockTapId(tap_ids_.size());
tap_ids_.push_back(tap_id);
tap_from_ports_.push_back(from_port);
@ -772,34 +781,46 @@ ClockTapId ClockNetwork::add_tree_tap(const ClockTreeId& tree_id,
return tap_id;
}
bool ClockNetwork::set_tap_bounding_box(const ClockTapId& tap_id, const vtr::Rect<size_t>& bb) {
bool ClockNetwork::set_tap_bounding_box(const ClockTapId& tap_id,
const vtr::Rect<size_t>& bb) {
VTR_ASSERT(valid_tap_id(tap_id));
/* Check the bounding box, ensure it must be valid */
if (bb.xmax() < bb.xmin() || bb.ymax() < bb.ymin()) {
VTR_LOG_ERROR("Invalid bounding box (xlow=%lu, ylow=%lu) -> (xhigh=%lu, yhigh=%lu)! Must follow: xlow <= xhigh, ylow <= yhigh!\n", bb.xmin(), bb.ymin(), bb.xmax(), bb.ymax());
return false;
VTR_LOG_ERROR(
"Invalid bounding box (xlow=%lu, ylow=%lu) -> (xhigh=%lu, yhigh=%lu)! "
"Must follow: xlow <= xhigh, ylow <= yhigh!\n",
bb.xmin(), bb.ymin(), bb.xmax(), bb.ymax());
return false;
}
tap_bbs_[tap_id] = bb;
return true;
}
bool ClockNetwork::set_tap_step_x(const ClockTapId& tap_id, const size_t& step) {
bool ClockNetwork::set_tap_step_x(const ClockTapId& tap_id,
const size_t& step) {
VTR_ASSERT(valid_tap_id(tap_id));
/* Must be a valid step >= 1 */
if (step == 0) {
VTR_LOG_ERROR("Invalid x-direction step (=%lu) for any bounding box! Expect an integer >= 1!\n", step);
return false;
VTR_LOG_ERROR(
"Invalid x-direction step (=%lu) for any bounding box! Expect an integer "
">= 1!\n",
step);
return false;
}
tap_bb_steps_[tap_id].set_x(step);
return true;
}
bool ClockNetwork::set_tap_step_y(const ClockTapId& tap_id, const size_t& step) {
bool ClockNetwork::set_tap_step_y(const ClockTapId& tap_id,
const size_t& step) {
VTR_ASSERT(valid_tap_id(tap_id));
/* Must be a valid step >= 1 */
if (step == 0) {
VTR_LOG_ERROR("Invalid y-direction step (=%lu) for any bounding box! Expect an integer >= 1!\n", step);
return false;
VTR_LOG_ERROR(
"Invalid y-direction step (=%lu) for any bounding box! Expect an integer "
">= 1!\n",
step);
return false;
}
tap_bb_steps_[tap_id].set_y(step);
return true;
@ -957,10 +978,8 @@ bool ClockNetwork::valid_internal_driver_id(
(int_driver_id == internal_driver_ids_[int_driver_id]);
}
bool ClockNetwork::valid_tap_id(
const ClockTapId& tap_id) const {
return (size_t(tap_id) < tap_ids_.size()) &&
(tap_id == tap_ids_[tap_id]);
bool ClockNetwork::valid_tap_id(const ClockTapId& tap_id) const {
return (size_t(tap_id) < tap_ids_.size()) && (tap_id == tap_ids_[tap_id]);
}
bool ClockNetwork::valid_level_id(const ClockTreeId& tree_id,

39
libs/libclkarchopenfpga/src/base/clock_network.h
View File

@ -49,12 +49,7 @@ class ClockNetwork {
typedef vtr::Range<clock_internal_driver_iterator>
clock_internal_driver_range;
/* Type of tap points */
enum class e_tap_type : unsigned char {
ALL = 0,
SINGLE,
REGION,
NUM_TYPES
};
enum class e_tap_type : unsigned char { ALL = 0, SINGLE, REGION, NUM_TYPES };
public: /* Constructors */
ClockNetwork();
@ -148,23 +143,25 @@ class ClockNetwork {
/* Find the type of tap point:
* all -> all coordinates in efpga are required to tap
* single -> only 1 coordinate is required to tap
* region -> coordinates in a region required to tap. Steps in region may be required
* region -> coordinates in a region required to tap. Steps in region may be
* required
*/
e_tap_type tap_type(const ClockTapId& tap_id) const;
/* Require the type of single */
size_t tap_x(const ClockTapId& tap_id) const;
size_t tap_y(const ClockTapId& tap_id) const;
size_t tap_x(const ClockTapId& tap_id) const;
size_t tap_y(const ClockTapId& tap_id) const;
/* Require the type of region */
vtr::Rect<size_t> tap_bounding_box(const ClockTapId& tap_id) const;
vtr::Rect<size_t> tap_bounding_box(const ClockTapId& tap_id) const;
/* Steps are only available when type is region */
size_t tap_step_x(const ClockTapId& tap_id) const;
size_t tap_step_y(const ClockTapId& tap_id) const;
size_t tap_step_x(const ClockTapId& tap_id) const;
size_t tap_step_y(const ClockTapId& tap_id) const;
/* Return the list of flatten tap pins. For example: clb[0:1].clk[2:2] is
* flatten to { clb[0].clk[2], clb[1].clk[2] } Useful to build clock routing
* resource graph Note that the clk_pin_id limits only 1 clock to be accessed
*/
std::vector<std::string> tree_flatten_tap_to_ports(
const ClockTreeId& tree_id, const ClockTreePinId& clk_pin_id, const vtr::Point<size_t>& tap_coord) const;
const ClockTreeId& tree_id, const ClockTreePinId& clk_pin_id,
const vtr::Point<size_t>& tap_coord) const;
/* Find a spine with a given name, if not found, return an valid id, otherwise
* return an invalid one */
ClockSpineId find_spine(const std::string& name) const;
@ -218,8 +215,11 @@ class ClockNetwork {
ClockInternalDriverId add_spine_switch_point_internal_driver(
const ClockSpineId& spine_id, const ClockSwitchPointId& switch_point_id,
const std::string& internal_driver_port);
ClockTapId add_tree_tap(const ClockTreeId& tree_id, const std::string& from_port, const std::string& to_port);
bool set_tap_bounding_box(const ClockTapId& tap_id, const vtr::Rect<size_t>& bb);
ClockTapId add_tree_tap(const ClockTreeId& tree_id,
const std::string& from_port,
const std::string& to_port);
bool set_tap_bounding_box(const ClockTapId& tap_id,
const vtr::Rect<size_t>& bb);
bool set_tap_step_x(const ClockTapId& tap_id, const size_t& step);
bool set_tap_step_y(const ClockTapId& tap_id, const size_t& step);
/* Build internal links between clock tree, spines etc. This is also an
@ -265,7 +265,8 @@ class ClockNetwork {
/* Show if the tap id is a valid for data queries */
bool valid_tap_id(const ClockTapId& tap_id) const;
/* Check if a given coordinate matches the requirements for a tap point */
bool valid_tap_coord_in_bb(const ClockTapId& tap_id, const vtr::Point<size_t>& tap_coord) const;
bool valid_tap_coord_in_bb(const ClockTapId& tap_id,
const vtr::Point<size_t>& tap_coord) const;
private: /* Private mutators */
/* Build internal links between spines under a given tree */
@ -312,8 +313,10 @@ class ClockNetwork {
vtr::vector<ClockTapId, ClockTapId> tap_ids_;
vtr::vector<ClockTapId, std::string> tap_from_ports_;
vtr::vector<ClockTapId, std::string> tap_to_ports_;
vtr::vector<ClockTapId, vtr::Rect<size_t>> tap_bbs_; /* Bounding box for tap points, (xlow, ylow) -> (xhigh, yhigh) */
vtr::vector<ClockTapId, vtr::Point<size_t>> tap_bb_steps_; /* x() -> x-direction step, y() -> y-direction step */
vtr::vector<ClockTapId, vtr::Rect<size_t>>
tap_bbs_; /* Bounding box for tap points, (xlow, ylow) -> (xhigh, yhigh) */
vtr::vector<ClockTapId, vtr::Point<size_t>>
tap_bb_steps_; /* x() -> x-direction step, y() -> y-direction step */
/* Default routing resource */
std::string default_segment_name_; /* The routing segment representing the

71
libs/libclkarchopenfpga/src/io/read_xml_clock_network.cpp
View File

@ -29,8 +29,8 @@ namespace openfpga { // Begin namespace openfpga
*******************************************************************/
static void read_xml_clock_tree_tap_type_all(pugi::xml_node& xml_tap,
const pugiutil::loc_data& loc_data,
ClockNetwork& clk_ntwk,
const ClockTreeId& tree_id) {
ClockNetwork& clk_ntwk,
const ClockTreeId& tree_id) {
if (!clk_ntwk.valid_tree_id(tree_id)) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(xml_tap),
"Invalid id of a clock tree!\n");
@ -48,10 +48,9 @@ static void read_xml_clock_tree_tap_type_all(pugi::xml_node& xml_tap,
/********************************************************************
* Parse XML codes of a <single> to an object of ClockNetwork
*******************************************************************/
static void read_xml_clock_tree_tap_type_single(pugi::xml_node& xml_tap,
const pugiutil::loc_data& loc_data,
ClockNetwork& clk_ntwk,
const ClockTreeId& tree_id) {
static void read_xml_clock_tree_tap_type_single(
pugi::xml_node& xml_tap, const pugiutil::loc_data& loc_data,
ClockNetwork& clk_ntwk, const ClockTreeId& tree_id) {
if (!clk_ntwk.valid_tree_id(tree_id)) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(xml_tap),
"Invalid id of a clock tree!\n");
@ -63,25 +62,26 @@ static void read_xml_clock_tree_tap_type_single(pugi::xml_node& xml_tap,
std::string to_pin_name =
get_attribute(xml_tap, XML_CLOCK_TREE_TAP_ATTRIBUTE_TO_PIN, loc_data)
.as_string();
ClockTapId tap_id = clk_ntwk.add_tree_tap(tree_id, from_pin_name, to_pin_name);
ClockTapId tap_id =
clk_ntwk.add_tree_tap(tree_id, from_pin_name, to_pin_name);
/* Single tap only require a coordinate */
size_t tap_x =
get_attribute(xml_tap, XML_CLOCK_TREE_TAP_ATTRIBUTE_X, loc_data, pugiutil::ReqOpt::REQUIRED)
.as_int();
size_t tap_y =
get_attribute(xml_tap, XML_CLOCK_TREE_TAP_ATTRIBUTE_Y, loc_data, pugiutil::ReqOpt::REQUIRED)
.as_int();
clk_ntwk.set_tap_bounding_box(tap_id, vtr::Rect<size_t>(tap_x, tap_y, tap_x, tap_y));
size_t tap_x = get_attribute(xml_tap, XML_CLOCK_TREE_TAP_ATTRIBUTE_X,
loc_data, pugiutil::ReqOpt::REQUIRED)
.as_int();
size_t tap_y = get_attribute(xml_tap, XML_CLOCK_TREE_TAP_ATTRIBUTE_Y,
loc_data, pugiutil::ReqOpt::REQUIRED)
.as_int();
clk_ntwk.set_tap_bounding_box(tap_id,
vtr::Rect<size_t>(tap_x, tap_y, tap_x, tap_y));
}
/********************************************************************
* Parse XML codes of a <region> to an object of ClockNetwork
*******************************************************************/
static void read_xml_clock_tree_tap_type_region(pugi::xml_node& xml_tap,
const pugiutil::loc_data& loc_data,
ClockNetwork& clk_ntwk,
const ClockTreeId& tree_id) {
static void read_xml_clock_tree_tap_type_region(
pugi::xml_node& xml_tap, const pugiutil::loc_data& loc_data,
ClockNetwork& clk_ntwk, const ClockTreeId& tree_id) {
if (!clk_ntwk.valid_tree_id(tree_id)) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(xml_tap),
"Invalid id of a clock tree!\n");
@ -93,22 +93,26 @@ static void read_xml_clock_tree_tap_type_region(pugi::xml_node& xml_tap,
std::string to_pin_name =
get_attribute(xml_tap, XML_CLOCK_TREE_TAP_ATTRIBUTE_TO_PIN, loc_data)
.as_string();
ClockTapId tap_id = clk_ntwk.add_tree_tap(tree_id, from_pin_name, to_pin_name);
ClockTapId tap_id =
clk_ntwk.add_tree_tap(tree_id, from_pin_name, to_pin_name);
/* Region require a bounding box */
size_t tap_start_x =
get_attribute(xml_tap, XML_CLOCK_TREE_TAP_ATTRIBUTE_STARTX, loc_data, pugiutil::ReqOpt::REQUIRED)
get_attribute(xml_tap, XML_CLOCK_TREE_TAP_ATTRIBUTE_STARTX, loc_data,
pugiutil::ReqOpt::REQUIRED)
.as_int();
size_t tap_start_y =
get_attribute(xml_tap, XML_CLOCK_TREE_TAP_ATTRIBUTE_STARTY, loc_data, pugiutil::ReqOpt::REQUIRED)
get_attribute(xml_tap, XML_CLOCK_TREE_TAP_ATTRIBUTE_STARTY, loc_data,
pugiutil::ReqOpt::REQUIRED)
.as_int();
size_t tap_end_x =
get_attribute(xml_tap, XML_CLOCK_TREE_TAP_ATTRIBUTE_ENDX, loc_data, pugiutil::ReqOpt::REQUIRED)
.as_int();
size_t tap_end_y =
get_attribute(xml_tap, XML_CLOCK_TREE_TAP_ATTRIBUTE_ENDY, loc_data, pugiutil::ReqOpt::REQUIRED)
.as_int();
clk_ntwk.set_tap_bounding_box(tap_id, vtr::Rect<size_t>(tap_start_x, tap_start_y, tap_end_x, tap_end_y));
size_t tap_end_x = get_attribute(xml_tap, XML_CLOCK_TREE_TAP_ATTRIBUTE_ENDX,
loc_data, pugiutil::ReqOpt::REQUIRED)
.as_int();
size_t tap_end_y = get_attribute(xml_tap, XML_CLOCK_TREE_TAP_ATTRIBUTE_ENDY,
loc_data, pugiutil::ReqOpt::REQUIRED)
.as_int();
clk_ntwk.set_tap_bounding_box(
tap_id, vtr::Rect<size_t>(tap_start_x, tap_start_y, tap_end_x, tap_end_y));
/* Default step is all 1 */
size_t tap_step_x =
@ -129,12 +133,17 @@ static void read_xml_clock_tree_taps(pugi::xml_node& xml_taps,
/* Error out if the XML child has an invalid name! */
if (xml_tap.name() == std::string(XML_CLOCK_TREE_TAP_ALL_NODE_NAME)) {
read_xml_clock_tree_tap_type_all(xml_tap, loc_data, clk_ntwk, tree_id);
} else if (xml_tap.name() == std::string(XML_CLOCK_TREE_TAP_REGION_NODE_NAME)) {
} else if (xml_tap.name() ==
std::string(XML_CLOCK_TREE_TAP_REGION_NODE_NAME)) {
read_xml_clock_tree_tap_type_region(xml_tap, loc_data, clk_ntwk, tree_id);
} else if (xml_tap.name() == std::string(XML_CLOCK_TREE_TAP_SINGLE_NODE_NAME)) {
} else if (xml_tap.name() ==
std::string(XML_CLOCK_TREE_TAP_SINGLE_NODE_NAME)) {
read_xml_clock_tree_tap_type_single(xml_tap, loc_data, clk_ntwk, tree_id);
} else {
bad_tag(xml_taps, loc_data, xml_tap, {XML_CLOCK_TREE_TAP_ALL_NODE_NAME, XML_CLOCK_TREE_TAP_REGION_NODE_NAME, XML_CLOCK_TREE_TAP_SINGLE_NODE_NAME});
bad_tag(
xml_taps, loc_data, xml_tap,
{XML_CLOCK_TREE_TAP_ALL_NODE_NAME, XML_CLOCK_TREE_TAP_REGION_NODE_NAME,
XML_CLOCK_TREE_TAP_SINGLE_NODE_NAME});
}
}
}

8
openfpga/src/annotation/route_clock_rr_graph.cpp
View File

@ -171,15 +171,17 @@ static int route_clock_tree_rr_graph(
for (RREdgeId edge : rr_graph.edge_range(src_node)) {
RRNodeId des_node = rr_graph.edge_sink_node(edge);
if (rr_graph.node_type(des_node) == IPIN) {
/* Check if the IPIN is mapped, if not, do not connect */
/* if the IPIN is mapped, only connect when net mapping is expected */
/* Check if the IPIN is mapped, if not, do not connect */
/* if the IPIN is mapped, only connect when net mapping is
* expected */
if (tree2clk_pin_map.find(ipin) == tree2clk_pin_map.end()) {
continue;
}
if (!vpr_routing_annotation.rr_node_net(des_node)) {
continue;
}
if (vpr_routing_annotation.rr_node_net(des_node) != tree2clk_pin_map.at(ipin)) {
if (vpr_routing_annotation.rr_node_net(des_node) !=
tree2clk_pin_map.at(ipin)) {
continue;
}
VTR_ASSERT(rr_graph.valid_node(src_node));