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[core] code format

This commit is contained in:
tangxifan 2024-07-09 22:54:55 -07:00
parent 63f2a07c86
commit 96bdcc8b35
5 changed files with 23 additions and 20 deletions
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29
openfpga/src/annotation/openfpga_annotate_routing.cpp
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@ -22,8 +22,7 @@ namespace openfpga {
vtr::vector<RRNodeId, ClusterNetId> annotate_rr_node_global_net(
const DeviceContext& device_ctx, const ClusteredNetlist& cluster_nlist,
const PlacementContext& placement_ctx,
const VprClusteringAnnotation& clustering_annotation,
const bool& verbose) {
const VprClusteringAnnotation& clustering_annotation, const bool& verbose) {
vtr::vector<RRNodeId, ClusterNetId> rr_node_nets;
size_t counter = 0;
@ -44,15 +43,18 @@ vtr::vector<RRNodeId, ClusterNetId> annotate_rr_node_global_net(
ClusterBlockId block_id = cluster_nlist.pin_block(pin_id);
t_block_loc blk_loc = get_block_loc(block_id, false);
int phy_pin = placement_ctx.physical_pins[pin_id];
t_physical_tile_type_ptr phy_tile = device_ctx.grid.get_physical_type(t_physical_tile_loc(blk_loc.loc.x, blk_loc.loc.y, 0));
t_physical_tile_type_ptr phy_tile = device_ctx.grid.get_physical_type(
t_physical_tile_loc(blk_loc.loc.x, blk_loc.loc.y, 0));
int node_pin_num = phy_tile->num_pins;
/* Note that the phy_pin may not reflect the actual pin index at the top-level physical tile type. It could be one of the random pin to the same pin class. So here, we have to find an exact match of the pin index from the clustering results! */
int subtile_idx = blk_loc.loc.sub_tile;
/* Note that the phy_pin may not reflect the actual pin index at the
* top-level physical tile type. It could be one of the random pin to the
* same pin class. So here, we have to find an exact match of the pin
* index from the clustering results! */
int subtile_idx = blk_loc.loc.sub_tile;
auto logical_block = cluster_nlist.block_type(block_id);
for (int j = 0; j < logical_block->pb_type->num_pins; j++) {
/* Find the net mapped to this pin in clustering results*/
ClusterNetId cluster_net_id =
cluster_nlist.block_net(block_id, j);
ClusterNetId cluster_net_id = cluster_nlist.block_net(block_id, j);
/* Get the actual net id because it may be renamed during routing */
if (true == clustering_annotation.is_net_renamed(block_id, j)) {
cluster_net_id = clustering_annotation.net(block_id, j);
@ -60,20 +62,23 @@ vtr::vector<RRNodeId, ClusterNetId> annotate_rr_node_global_net(
/* Bypass unmatched pins */
if (cluster_net_id != net_id) {
continue;
}
int curr_pin_num = get_physical_pin_at_sub_tile_location(phy_tile, logical_block, subtile_idx, j);
}
int curr_pin_num = get_physical_pin_at_sub_tile_location(
phy_tile, logical_block, subtile_idx, j);
if (phy_tile->pin_class[curr_pin_num] != phy_tile->pin_class[phy_pin]) {
continue;
}
node_pin_num = curr_pin_num;
break;
break;
}
VTR_ASSERT(node_pin_num < phy_tile->num_pins);
VTR_ASSERT(node_pin_num < phy_tile->num_pins);
std::vector<RRNodeId> curr_rr_nodes =
rr_graph.node_lookup().find_nodes_at_all_sides(
layer, blk_loc.loc.x, blk_loc.loc.y, IPIN, node_pin_num);
for (RRNodeId curr_rr_node : curr_rr_nodes) {
VTR_LOGV(verbose, "Annotate global net '%s' on '%s' pin '%d'\n", cluster_nlist.net_name(net_id).c_str(), phy_tile->name, node_pin_num);
VTR_LOGV(verbose, "Annotate global net '%s' on '%s' pin '%d'\n",
cluster_nlist.net_name(net_id).c_str(), phy_tile->name,
node_pin_num);
rr_node_nets[curr_rr_node] = net_id;
counter++;
}

5
openfpga/src/annotation/openfpga_annotate_routing.h
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@ -5,8 +5,8 @@
* Include header files that are required by function declaration
*******************************************************************/
#include "openfpga_context.h"
#include "vpr_context.h"
#include "vpr_clustering_annotation.h"
#include "vpr_context.h"
#include "vpr_routing_annotation.h"
/********************************************************************
@ -19,8 +19,7 @@ namespace openfpga {
vtr::vector<RRNodeId, ClusterNetId> annotate_rr_node_global_net(
const DeviceContext& device_ctx, const ClusteredNetlist& cluster_nlist,
const PlacementContext& placement_ctx,
const VprClusteringAnnotation& clustering_annotation,
const bool& verbose);
const VprClusteringAnnotation& clustering_annotation, const bool& verbose);
void annotate_vpr_rr_node_nets(const DeviceContext& device_ctx,
const ClusteringContext& clustering_ctx,

4
openfpga/src/annotation/route_clock_rr_graph.cpp
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@ -510,8 +510,8 @@ int route_clock_rr_graph(
/* Build rr_node-to-net mapping for global nets */
vtr::vector<RRNodeId, ClusterNetId> rr_node_gnets =
annotate_rr_node_global_net(vpr_device_ctx, cluster_nlist, vpr_place_ctx, vpr_clustering_annotation,
verbose);
annotate_rr_node_global_net(vpr_device_ctx, cluster_nlist, vpr_place_ctx,
vpr_clustering_annotation, verbose);
/* Route spines one by one */
for (auto itree : clk_ntwk.trees()) {

2
openfpga/src/annotation/route_clock_rr_graph.h
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@ -7,9 +7,9 @@
#include "clock_network.h"
#include "pin_constraints.h"
#include "rr_clock_spatial_lookup.h"
#include "vpr_clustering_annotation.h"
#include "vpr_context.h"
#include "vpr_routing_annotation.h"
#include "vpr_clustering_annotation.h"
/********************************************************************
* Function declaration

3
openfpga/src/base/openfpga_link_arch_template.h
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@ -233,8 +233,7 @@ int route_clock_rr_graph_template(T& openfpga_ctx, const Command& cmd,
return route_clock_rr_graph(
openfpga_ctx.mutable_vpr_routing_annotation(),
openfpga_ctx.vpr_clustering_annotation(),
g_vpr_ctx.device(),
openfpga_ctx.vpr_clustering_annotation(), g_vpr_ctx.device(),
g_vpr_ctx.clustering().clb_nlist, g_vpr_ctx.placement(),
openfpga_ctx.clock_rr_lookup(), openfpga_ctx.clock_arch(), pin_constraints,
cmd_context.option_enable(cmd, opt_disable_unused_trees),