[test] typo

openfpga_flow/benchmarks/micro_benchmark/rst_and_clk_on_lut/rst_and_clk_on_lut.v

@@ -4,7 +4,7 @@
 ////////////////////////////////////////
 `timescale 1ns / 1ps
 
-module rst_on_lut(a, b, c, q, out0, out1, clk, rst);
+module rst_and_clk_on_lut(a, b, c, q, out0, out1, clk, rst);
 
 input wire rst;
 input wire clk;