tangxifan
|
2bb87ea278
|
[core] code format
|
2024-09-20 19:23:14 -07:00 |
|
tangxifan
|
f87e095558
|
[core] support intermediate driver in clock routing
|
2024-09-20 19:22:39 -07:00 |
|
tangxifan
|
e8957b6fd8
|
[core] enable clock intermediate driver in rrgraph buildup
|
2024-09-20 19:07:16 -07:00 |
|
tangxifan
|
f6b645fd25
|
[core] code format
|
2024-09-18 17:44:55 -07:00 |
|
tangxifan
|
1673d9b919
|
[core] fixed a bug
|
2024-09-18 17:43:41 -07:00 |
|
tangxifan
|
82878063c1
|
[core] syntax
|
2024-09-18 17:32:04 -07:00 |
|
tangxifan
|
47e30c3e4b
|
[core] support last stage mux
|
2024-09-18 17:26:44 -07:00 |
Lin
|
41d38193d3
|
reformat code
|
2024-09-12 11:18:25 +08:00 |
|
Lin
|
5ccad723c4
|
add comments
|
2024-09-12 11:16:31 +08:00 |
|
Lin
|
55611dbfe7
|
rewrite write_xml function
|
2024-09-11 18:08:51 +08:00 |
|
Lin
|
b2a5bd8437
|
fix merge error
|
2024-09-11 14:35:24 +08:00 |
Jingrong Lin
|
77b188060b
|
Merge branch 'master' into preloading_clean
|
2024-09-11 11:08:49 +08:00 |
|
Lin
|
ae6a8cb604
|
fix bug
|
2024-09-10 14:34:42 +08:00 |
victorzh001
|
04a60ca4b5
|
Merge branch 'master' into victor_OpenFPGA_dbg
|
2024-09-10 11:01:47 +08:00 |
Victor
|
3ea830e168
|
Add the reference_file to the index.rst
|
2024-09-10 10:46:15 +08:00 |
|
tangxifan
|
7250a7d703
|
[core] code format
|
2024-09-09 12:46:46 -07:00 |
|
tangxifan
|
e3b99e88ff
|
[core] syntax
|
2024-09-09 12:46:23 -07:00 |
|
tangxifan
|
fc92ecea24
|
[core] typo
|
2024-09-09 12:43:38 -07:00 |
|
tangxifan
|
5f50e4623c
|
[core] add a new option map_global_net_to_msb for pb_pin_fixup
|
2024-09-09 12:21:09 -07:00 |
|
Lin
|
f1547bae8a
|
fix build error
|
2024-09-09 18:18:07 +08:00 |
|
tangxifan
|
37cac3d679
|
Merge branch 'master' into victor_OpenFPGA_dbg
|
2024-09-08 21:13:48 -07:00 |
|
Lin
|
41d0eb7736
|
modification on device_rr_gsb
|
2024-09-09 11:36:48 +08:00 |
|
Lin
|
af7201d4bb
|
fix is_compressed_ tag
|
2024-09-09 11:19:12 +08:00 |
rafljiarui
|
f7aaead513
|
Fixed typo in vpr-main.cpp
|
2024-09-06 13:14:59 -05:00 |
|
Victor
|
9a2fc86dcd
|
add dependency on build_fabric
|
2024-09-06 17:58:47 +08:00 |
|
Victor
|
7bacc781d0
|
update code according to code review comments
|
2024-09-06 15:39:08 +08:00 |
|
Victor
|
4aca4fda6f
|
fix issue in reg test
|
2024-09-05 10:43:53 +08:00 |
|
Victor
|
ba5c8a3364
|
update code format
|
2024-09-03 11:20:51 +08:00 |
|
Victor
|
0093d4b269
|
Add command report_reference
|
2024-09-02 15:21:50 +08:00 |
|
Lin
|
a2b290c83b
|
mod typo
|
2024-08-30 15:47:29 +08:00 |
|
Lin
|
94309c2a73
|
change to reference
|
2024-08-30 15:33:47 +08:00 |
|
Lin
|
adeb9ba7ea
|
fix typo
|
2024-08-30 12:55:44 +08:00 |
|
Lin
|
cb003f8833
|
mod prelod flag
|
2024-08-30 12:51:56 +08:00 |
|
Lin
|
9e491680e6
|
change file location
|
2024-08-30 11:02:09 +08:00 |
|
Lin
|
643e3a2dd1
|
fix build bug
|
2024-08-29 10:29:26 +08:00 |
|
Lin
|
8372eead6a
|
add preload flag to device_rr_gsb and revert change to build fabric
|
2024-08-28 18:14:33 +08:00 |
|
Lin
|
a23860a6a7
|
reformat code
|
2024-08-28 17:58:15 +08:00 |
|
Lin
|
352c9b49c9
|
add cmd dependency
|
2024-08-28 17:52:34 +08:00 |
|
Lin
|
df05c904db
|
make the read block coord and read instance coords clearer
|
2024-08-28 17:41:41 +08:00 |
|
Lin
|
0a14b2fa65
|
pass device_rr_gsb instead of openfpga_ctx
|
2024-08-28 17:26:50 +08:00 |
|
Lin
|
d4028b4e6f
|
modification no build warning now
|
2024-08-28 16:31:16 +08:00 |
|
Lin
|
cde4c8d34a
|
mod according to code review
|
2024-08-28 15:45:19 +08:00 |
|
Lin
|
1b0fcaee0f
|
reformat code
|
2024-08-27 17:05:13 +08:00 |
|
Lin
|
3c28f84727
|
build bug
|
2024-08-26 19:21:26 -07:00 |
|
Lin
|
9e283f383d
|
remove redundant include
|
2024-08-26 03:09:19 -07:00 |
|
Lin
|
67c7c2da66
|
mod comments
|
2024-08-26 03:07:06 -07:00 |
|
Lin
|
9c061e0ab5
|
Merge branch 'preloading' of github.com:lnis-uofu/OpenFPGA
|
2024-08-25 22:48:56 -07:00 |
|
Lin
|
968824c2dd
|
build unique blocks final version
|
2024-08-25 19:56:23 -07:00 |
|
Lin
|
913fdc043e
|
debuged
|
2024-08-23 03:52:16 -07:00 |
|
Lin
|
699131ad58
|
full flow with bugs
|
2024-08-19 01:18:06 -07:00 |