riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

[core] code format

This commit is contained in:
tangxifan 2024-09-09 12:46:46 -07:00
parent e3b99e88ff
commit 7250a7d703
3 changed files with 15 additions and 14 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

19
openfpga/src/base/openfpga_pb_pin_fixup.cpp
View File

@ -32,10 +32,8 @@ namespace openfpga {
static int update_cluster_pin_global_net_with_post_routing_results(
const ClusteringContext& clustering_ctx,
VprClusteringAnnotation& clustering_annotation, const ClusterBlockId& blk_id,
t_logical_block_type_ptr logical_block,
const bool& map_gnet2msb,
size_t& num_fixup,
const bool& verbose) {
t_logical_block_type_ptr logical_block, const bool& map_gnet2msb,
size_t& num_fixup, const bool& verbose) {
/* Reassign global nets to unused pins in the same port where they were mapped
* NO optimization is done here!!! First find first fit
*/
@ -144,8 +142,7 @@ static int update_cluster_pin_with_post_routing_results(
VprClusteringAnnotation& vpr_clustering_annotation, const size_t& layer,
const vtr::Point<size_t>& grid_coord, const ClusterBlockId& blk_id,
const e_side& border_side, const size_t& z, const bool& perimeter_cb,
const bool& map_gnet2msb,
size_t& num_fixup, const bool& verbose) {
const bool& map_gnet2msb, size_t& num_fixup, const bool& verbose) {
int status = CMD_EXEC_SUCCESS;
/* Handle each pin */
auto logical_block = clustering_ctx.clb_nlist.block_type(blk_id);
@ -343,8 +340,8 @@ static int update_cluster_pin_with_post_routing_results(
}
/* 2nd round of fixup: focus on global nets */
status = update_cluster_pin_global_net_with_post_routing_results(
clustering_ctx, vpr_clustering_annotation, blk_id, logical_block, map_gnet2msb, num_fixup,
verbose);
clustering_ctx, vpr_clustering_annotation, blk_id, logical_block,
map_gnet2msb, num_fixup, verbose);
return status;
}
@ -357,12 +354,12 @@ int update_pb_pin_with_post_routing_results(
const PlacementContext& placement_ctx,
const VprRoutingAnnotation& vpr_routing_annotation,
VprClusteringAnnotation& vpr_clustering_annotation, const bool& perimeter_cb,
const bool& map_gnet2msb,
const bool& verbose) {
const bool& map_gnet2msb, const bool& verbose) {
int status = CMD_EXEC_SUCCESS;
size_t num_fixup = 0;
/* Confirm options */
VTR_LOGV(verbose && map_gnet2msb, "User choose to map global net to the best fit MSB of input port\n");
VTR_LOGV(verbose && map_gnet2msb,
"User choose to map global net to the best fit MSB of input port\n");
/* Ensure a clean start: remove all the remapping results from VTR's
* post-routing clustering result sync-up */
vpr_clustering_annotation.clear_net_remapping();

3
openfpga/src/base/openfpga_pb_pin_fixup.h
View File

@ -19,8 +19,7 @@ int update_pb_pin_with_post_routing_results(
const PlacementContext& placement_ctx,
const VprRoutingAnnotation& vpr_routing_annotation,
VprClusteringAnnotation& vpr_clustering_annotation, const bool& perimeter_cb,
const bool& map_gnet2msb,
const bool& verbose);
const bool& map_gnet2msb, const bool& verbose);
} /* end namespace openfpga */

7
openfpga/src/base/openfpga_setup_command_template.h
View File

@ -325,7 +325,12 @@ ShellCommandId add_pb_pin_fixup_command_template(
Command shell_cmd("pb_pin_fixup");
/* Add an option '--map_global_net_to_msb' */
shell_cmd.add_option("map_global_net_to_msb", false, "If specified, any global net including clock, reset etc, will be mapped to a best-fit Most Significant Bit (MSB) of input ports of programmable blocks. If not specified, a best-fit Least Significant Bit (LSB) will be the default choice");
shell_cmd.add_option(
"map_global_net_to_msb", false,
"If specified, any global net including clock, reset etc, will be mapped "
"to a best-fit Most Significant Bit (MSB) of input ports of programmable "
"blocks. If not specified, a best-fit Least Significant Bit (LSB) will be "
"the default choice");
/* Add an option '--verbose' */
shell_cmd.add_option("verbose", false, "Show verbose outputs");