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[core] syntax

This commit is contained in:
tangxifan 2024-09-18 17:32:04 -07:00
parent 47e30c3e4b
commit 82878063c1
2 changed files with 3 additions and 2 deletions
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1
libs/libarchopenfpga/src/circuit_library.h
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@ -274,6 +274,7 @@ class CircuitLibrary {
CircuitModelId pass_gate_logic_model(const CircuitModelId& model_id) const;
CircuitModelId last_stage_pass_gate_logic_model(const CircuitModelId& model_id) const;
std::string pass_gate_logic_model_name(const CircuitModelId& model_id) const;
std::string last_stage_pass_gate_logic_model_name(const CircuitModelId& model_id) const;
enum e_circuit_model_pass_gate_logic_type pass_gate_logic_type(
const CircuitModelId& model_id) const;
float pass_gate_logic_pmos_size(const CircuitModelId& model_id) const;

4
openfpga/src/fabric/build_mux_modules.cpp
View File

@ -498,7 +498,7 @@ static void build_cmos_mux_module_mux2_multiplexing_structure(
VTR_ASSERT(1 == std_cell_module_output_port.get_width());
/* Find module information of the standard cell MUX2 */
CircuitModelId last_stage_std_cell_model = circuit_lib.model_last_stage_pass_gate_model(mux_model);
CircuitModelId last_stage_std_cell_model = circuit_lib.last_stage_pass_gate_logic_model(mux_model);
std::string last_stage_std_cell_module_name = circuit_lib.model_name(last_stage_std_cell_model);
/* Get the moduleId for the submodule */
ModuleId last_stage_std_cell_module_id =
@ -640,7 +640,7 @@ static void build_cmos_mux_module_mux2_multiplexing_structure(
} else {
module_manager.add_module_net_sink(
mux_module, mux_module_mem_nets[mem], last_stage_std_cell_module_id,
last_stage_std_cell_instance_id, last_stage_std_cell_module_mem,
std_cell_instance_id, last_stage_std_cell_module_mem,
last_stage_std_cell_module_mem_port.get_lsb());
}
}