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build unique blocks final version

This commit is contained in:
Lin 2024-08-25 19:56:23 -07:00
parent 913fdc043e
commit 968824c2dd
5 changed files with 72 additions and 79 deletions
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55
openfpga/src/annotation/device_rr_gsb.cpp
View File

@ -367,34 +367,7 @@ void DeviceRRGSB::build_gsb_unique_module() {
}
}
}
void DeviceRRGSB::print_txt() {
std::ofstream outFile(
"/home/linear/project/test_data/and2/config/output_read.txt");
outFile << "################# sb_unique_module_id_ #########" << "\n";
for (int i = 0; i < sb_unique_module_id_.size(); i++) {
for (int j = 0; j < sb_unique_module_id_[0].size(); j++) {
outFile << i << "," << j << ":" << sb_unique_module_id_[i][j] << "\n";
}
}
outFile << "################# cbx_unique_module_id_ #########" << "\n";
for (int i = 0; i < cbx_unique_module_id_.size(); i++) {
for (int j = 0; j < cbx_unique_module_id_[0].size(); j++) {
outFile << i << "," << j << ":" << cbx_unique_module_id_[i][j] << "\n";
}
}
outFile << "################# cby_unique_module_id_ #########" << "\n";
for (int i = 0; i < cby_unique_module_id_.size(); i++) {
for (int j = 0; j < cby_unique_module_id_[0].size(); j++) {
outFile << i << "," << j << ":" << cby_unique_module_id_[i][j] << "\n";
}
}
outFile << "################# gsb_unique_module_id_ #########" << "\n";
for (int i = 0; i < gsb_unique_module_id_.size(); i++) {
for (int j = 0; j < gsb_unique_module_id_[0].size(); j++) {
outFile << i << "," << j << ":" << gsb_unique_module_id_[i][j] << "\n";
}
}
}
void DeviceRRGSB::build_unique_module(const RRGraphView& rr_graph) {
build_sb_unique_module(rr_graph);
@ -402,32 +375,6 @@ void DeviceRRGSB::build_unique_module(const RRGraphView& rr_graph) {
build_cb_unique_module(rr_graph, CHANY);
build_gsb_unique_module();
std::ofstream outFile(
"/home/linear/project/test_data/and2/config/output.txt");
outFile << "################# sb_unique_module_id_ #########" << "\n";
for (int i = 0; i < sb_unique_module_id_.size(); i++) {
for (int j = 0; j < sb_unique_module_id_[0].size(); j++) {
outFile << i << "," << j << ":" << sb_unique_module_id_[i][j] << "\n";
}
}
outFile << "################# cbx_unique_module_id_ #########" << "\n";
for (int i = 0; i < cbx_unique_module_id_.size(); i++) {
for (int j = 0; j < cbx_unique_module_id_[0].size(); j++) {
outFile << i << "," << j << ":" << cbx_unique_module_id_[i][j] << "\n";
}
}
outFile << "################# cby_unique_module_id_ #########" << "\n";
for (int i = 0; i < cby_unique_module_id_.size(); i++) {
for (int j = 0; j < cby_unique_module_id_[0].size(); j++) {
outFile << i << "," << j << ":" << cby_unique_module_id_[i][j] << "\n";
}
}
outFile << "################# gsb_unique_module_id_ #########" << "\n";
for (int i = 0; i < gsb_unique_module_id_.size(); i++) {
for (int j = 0; j < gsb_unique_module_id_[0].size(); j++) {
outFile << i << "," << j << ":" << gsb_unique_module_id_[i][j] << "\n";
}
}
}
void DeviceRRGSB::add_gsb_unique_module(const vtr::Point<size_t>& coordinate) {

1
openfpga/src/annotation/device_rr_gsb.h
View File

@ -98,7 +98,6 @@ class DeviceRRGSB {
automatically identify and update the lists
of unique mirrors and rotatable mirrors */
void clear(); /* clean the content */
void print_txt();
void preload_unique_cbx_module(
const vtr::Point<size_t> block_coordinate,
const std::vector<vtr::Point<size_t>> instance_coords);

4
openfpga/src/base/openfpga_build_fabric_template.h
View File

@ -20,7 +20,7 @@
#include "read_xml_io_name_map.h"
#include "read_xml_module_name_map.h"
#include "read_xml_tile_config.h"
#include "read_xml_unique_blocks.h"
#include "read_write_xml_unique_blocks.h"
#include "rename_modules.h"
#include "vtr_log.h"
#include "vtr_time.h"
@ -101,7 +101,7 @@ int build_fabric_template(T& openfpga_ctx, const Command& cmd,
const CommandContext& cmd_context) {
CommandOptionId opt_frame_view = cmd.option("frame_view");
CommandOptionId opt_compress_routing = cmd.option("compress_routing");
CommandOptionId opt_preload = cmd.option("preload");
CommandOptionId opt_preload = cmd.option("preload_unique_blocks");
CommandOptionId opt_duplicate_grid_pin = cmd.option("duplicate_grid_pin");
CommandOptionId opt_gen_random_fabric_key =
cmd.option("generate_random_fabric_key");

4
openfpga/src/base/openfpga_setup_command_template.h
View File

@ -391,8 +391,8 @@ ShellCommandId add_build_fabric_command_template(
"Compress the number of unique routing modules by "
"identifying the unique GSBs");
/* Add an option '--preload' */
shell_cmd.add_option("preload", false,
/* Add an option '--preload_unique_blocks' */
shell_cmd.add_option("preload_unique_blocks", false,
"preload unique routing modules from user input xml file");
/* Add an option '--duplicate_grid_pin' */

87
openfpga/src/fabric/read_xml_unique_blocks.h → openfpga/src/fabric/read_write_xml_unique_blocks.h
View File

@ -1,5 +1,5 @@
#ifndef READ_XML_UNIQUE_BLOCKS_H
#define READ_XML_UNIQUE_BLOCKS_H
#ifndef READ_WRITE_XML_UNIQUE_BLOCKS_H
#define READ_WRITE_XML_UNIQUE_BLOCKS_H
/********************************************************************
* This file includes the top-level function of this library
@ -25,7 +25,7 @@
#include "arch_error.h"
#include "device_rr_gsb_utils.h"
#include "openfpga_digest.h"
#include "read_xml_unique_blocks.h"
#include "read_write_xml_unique_blocks.h"
#include "read_xml_util.h"
#include "rr_gsb.h"
#include "write_xml_utils.h"
@ -43,23 +43,16 @@ vtr::Point<size_t> read_xml_unique_instance_info(
}
template <class T>
void report_unique_module_status(T& openfpga_ctx, bool verbose_output) {
void report_unique_module_status_read(T& openfpga_ctx, bool verbose_output) {
/* Report the stats */
VTR_LOGV(
verbose_output,
"Detected %lu unique X-direction connection blocks from a total of %d "
"(compression rate=%.2f%)\n",
openfpga_ctx.device_rr_gsb().get_num_cb_unique_module(CHANX),
find_device_rr_gsb_num_cb_modules(openfpga_ctx.device_rr_gsb(), CHANX),
100. *
((float)find_device_rr_gsb_num_cb_modules(openfpga_ctx.device_rr_gsb(),
CHANX) /
(float)openfpga_ctx.device_rr_gsb().get_num_cb_unique_module(CHANX) -
1.));
"Read %lu unique X-direction connection blocks ",
openfpga_ctx.device_rr_gsb().get_num_cb_unique_module(CHANX));
VTR_LOGV(
verbose_output,
"Detected %lu unique Y-direction connection blocks from a total of %d "
"Read %lu unique Y-direction connection blocks from a total of %d "
"(compression rate=%.2f%)\n",
openfpga_ctx.device_rr_gsb().get_num_cb_unique_module(CHANY),
find_device_rr_gsb_num_cb_modules(openfpga_ctx.device_rr_gsb(), CHANY),
@ -71,7 +64,7 @@ void report_unique_module_status(T& openfpga_ctx, bool verbose_output) {
VTR_LOGV(
verbose_output,
"Detected %lu unique switch blocks from a total of %d (compression "
"Read %lu unique switch blocks from a total of %d (compression "
"rate=%.2f%)\n",
openfpga_ctx.device_rr_gsb().get_num_sb_unique_module(),
find_device_rr_gsb_num_sb_modules(openfpga_ctx.device_rr_gsb(),
@ -82,7 +75,60 @@ void report_unique_module_status(T& openfpga_ctx, bool verbose_output) {
1.));
VTR_LOG(
"Detected %lu unique general switch blocks from a total of %d "
"Read %lu unique general switch blocks from a total of %d "
"(compression "
"rate=%.2f%)\n",
openfpga_ctx.device_rr_gsb().get_num_gsb_unique_module(),
find_device_rr_gsb_num_gsb_modules(openfpga_ctx.device_rr_gsb(),
g_vpr_ctx.device().rr_graph),
100. * ((float)find_device_rr_gsb_num_gsb_modules(
openfpga_ctx.device_rr_gsb(), g_vpr_ctx.device().rr_graph) /
(float)openfpga_ctx.device_rr_gsb().get_num_gsb_unique_module() -
1.));
}
template <class T>
void report_unique_module_status_write(T& openfpga_ctx, bool verbose_output) {
/* Report the stats */
VTR_LOGV(
verbose_output,
"Write %lu unique X-direction connection blocks from a total of %d "
"(compression rate=%.2f%)\n",
openfpga_ctx.device_rr_gsb().get_num_cb_unique_module(CHANX),
find_device_rr_gsb_num_cb_modules(openfpga_ctx.device_rr_gsb(), CHANX),
100. *
((float)find_device_rr_gsb_num_cb_modules(openfpga_ctx.device_rr_gsb(),
CHANX) /
(float)openfpga_ctx.device_rr_gsb().get_num_cb_unique_module(CHANX) -
1.));
VTR_LOGV(
verbose_output,
"Write %lu unique Y-direction connection blocks from a total of %d "
"(compression rate=%.2f%)\n",
openfpga_ctx.device_rr_gsb().get_num_cb_unique_module(CHANY),
find_device_rr_gsb_num_cb_modules(openfpga_ctx.device_rr_gsb(), CHANY),
100. *
((float)find_device_rr_gsb_num_cb_modules(openfpga_ctx.device_rr_gsb(),
CHANY) /
(float)openfpga_ctx.device_rr_gsb().get_num_cb_unique_module(CHANY) -
1.));
VTR_LOGV(
verbose_output,
"Write %lu unique switch blocks from a total of %d (compression "
"rate=%.2f%)\n",
openfpga_ctx.device_rr_gsb().get_num_sb_unique_module(),
find_device_rr_gsb_num_sb_modules(openfpga_ctx.device_rr_gsb(),
g_vpr_ctx.device().rr_graph),
100. * ((float)find_device_rr_gsb_num_sb_modules(
openfpga_ctx.device_rr_gsb(), g_vpr_ctx.device().rr_graph) /
(float)openfpga_ctx.device_rr_gsb().get_num_sb_unique_module() -
1.));
VTR_LOG(
"Write %lu unique general switch blocks from a total of %d "
"(compression "
"rate=%.2f%)\n",
openfpga_ctx.device_rr_gsb().get_num_gsb_unique_module(),
@ -153,9 +199,8 @@ int read_xml_unique_blocks(T& openfpga_ctx, const char* file_name,
}
}
device_rr_gsb.build_gsb_unique_module();
device_rr_gsb.print_txt();
if (verbose_output) {
report_unique_module_status(openfpga_ctx, true);
report_unique_module_status_read(openfpga_ctx, true);
}
} catch (pugiutil::XmlError& e) {
archfpga_throw(file_name, e.line(), "%s", e.what());
@ -208,7 +253,7 @@ template <class T>
int write_xml_unique_blocks(const T& openfpga_ctx, const char* fname,
const char* file_type, bool verbose_output) {
vtr::ScopedStartFinishTimer timer("Write unique blocks...");
VTR_ASSERT(strcmp(file_type, "xml") == 0);
/* Create a file handler */
std::fstream fp;
/* Open the file stream */
@ -246,7 +291,9 @@ int write_xml_unique_blocks(const T& openfpga_ctx, const char* fname,
/* Close the file stream */
fp.close();
if (verbose_output) {
report_unique_module_status_write(openfpga_ctx, true);
}
return err_code;
}