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[core] add new type 'part_of_cb' for tile direct connections

This commit is contained in:
tangxifan 2024-05-17 18:59:53 -07:00
parent 16acaa004d
commit 0d8c21ca84
3 changed files with 26 additions and 17 deletions
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8
libs/libarchopenfpga/src/arch_direct.h
View File

@ -14,15 +14,15 @@
* These types are supplementary to the original VPR direct connections
* Here we extend to the cross-row and cross-column connections
********************************************************************/
enum e_direct_type {
INNER_COLUMN,
INNER_ROW,
enum class e_direct_type {
INNER_COLUMN_OR_ROW,
PART_OF_CB,
INTER_COLUMN,
INTER_ROW,
NUM_DIRECT_TYPES
};
constexpr std::array<const char*, NUM_DIRECT_TYPES> DIRECT_TYPE_STRING = {
{"inner_column", "inner_row", "inter_column", "inter_row"}};
{"inner_column_or_row", "part_of_cb", "inter_column", "inter_row"}};
enum e_direct_direction { POSITIVE_DIR, NEGATIVE_DIR, NUM_DIRECT_DIRECTIONS };
constexpr std::array<const char*, NUM_DIRECT_DIRECTIONS>

26
libs/libarchopenfpga/src/read_xml_routing_circuit.cpp
View File

@ -198,15 +198,20 @@ std::map<std::string, CircuitModelId> read_xml_routing_segment_circuit(
* Convert string to the enumerate of direct type
*******************************************************************/
static e_direct_type string_to_direct_type(const std::string& type_string) {
if (std::string("part_of_cb") == type_string) {
return e_direct_type::PART_OF_CB;
}
if (std::string("inner_column_or_row") == type_string) {
return e_direct_type::INNER_COLUMN_OR_ROW;
}
if (std::string("column") == type_string) {
return INTER_COLUMN;
return e_direct_type::INTER_COLUMN;
}
if (std::string("row") == type_string) {
return INTER_ROW;
return e_direct_type::INTER_ROW;
}
return NUM_DIRECT_TYPES;
return e_direct_type::NUM_DIRECT_TYPES;
}
/********************************************************************
@ -274,23 +279,24 @@ ArchDirect read_xml_direct_circuit(pugi::xml_node& Node,
/* Add more information*/
std::string direct_type_name =
get_attribute(xml_direct, "type", loc_data, pugiutil::ReqOpt::OPTIONAL)
.as_string("none");
/* If not defined, we go to the next */
if (std::string("none") == direct_type_name) {
continue;
}
.as_string(DIRECT_TYPE_STRING[e_direct_type::INNER_COLUMN_OR_ROW]);
e_direct_type direct_type = string_to_direct_type(direct_type_name);
if (NUM_DIRECT_TYPES == direct_type) {
archfpga_throw(
loc_data.filename_c_str(), loc_data.line(xml_direct),
"Direct type '%s' is not support! Acceptable values are [column|row]\n",
"Direct type '%s' is not support! Acceptable values are [inner_column_or_row|part_of_cb|column|row]\n",
direct_type_name.c_str());
}
arch_direct.set_type(direct, direct_type);
/* The following syntax is only available for inter-column/row */
if (arch_direct.type(direct) != INTER_COLUMN && arch_direct.type(direct) != INTER_ROW) {
continue;
}
std::string x_dir_name =
get_attribute(xml_direct, "x_dir", loc_data).as_string();
std::string y_dir_name =

9
openfpga/src/tile_direct/build_tile_direct.cpp
View File

@ -804,9 +804,12 @@ TileDirect build_device_tile_direct(const DeviceContext& device_ctx,
exit(1);
}
/* Build from original VPR arch definition */
build_inner_column_row_tile_direct(tile_direct,
device_ctx.arch->Directs[idirect],
device_ctx, arch_direct_id, verbose);
if((INNER_COLUMN_OR_ROW == arch_direct.type(arch_direct_id)) {
build_inner_column_row_tile_direct(tile_direct,
device_ctx.arch->Directs[idirect],
device_ctx, arch_direct_id, verbose);
/* Skip those direct connections which belong part of a connection block */
}
/* Build from OpenFPGA arch definition */
build_inter_column_row_tile_direct(
tile_direct, device_ctx.arch->Directs[idirect], device_ctx, arch_direct,