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[core] now support constant undriven local wires in verilog writer

This commit is contained in:
tangxifan 2024-07-04 20:32:56 -07:00
parent 1dd03d0fdd
commit 4e21bbb3f1
12 changed files with 51 additions and 2 deletions
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7
openfpga/src/fpga_verilog/fabric_verilog_options.cpp
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@ -21,6 +21,7 @@ FabricVerilogOption::FabricVerilogOption() {
default_net_type_ = VERILOG_DEFAULT_NET_TYPE_NONE;
time_stamp_ = true;
use_relative_path_ = false;
constant_undriven_inputs_ = false;
verbose_output_ = false;
}
@ -53,6 +54,8 @@ e_verilog_default_net_type FabricVerilogOption::default_net_type() const {
return default_net_type_;
}
bool FabricVerilogOption::constant_undriven_inputs() const { return constant_undriven_inputs_; }
bool FabricVerilogOption::verbose_output() const { return verbose_output_; }
/******************************************************************************
@ -106,6 +109,10 @@ void FabricVerilogOption::set_default_net_type(
}
}
void FabricVerilogOption::set_constant_undriven_inputs(const bool& enabled) {
constant_undriven_inputs_ = enabled;
}
void FabricVerilogOption::set_verbose_output(const bool& enabled) {
verbose_output_ = enabled;
}

3
openfpga/src/fpga_verilog/fabric_verilog_options.h
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@ -28,6 +28,7 @@ class FabricVerilogOption {
bool compress_routing() const;
e_verilog_default_net_type default_net_type() const;
bool print_user_defined_template() const;
bool constant_undriven_inputs() const;
bool verbose_output() const;
public: /* Public mutators */
@ -39,6 +40,7 @@ class FabricVerilogOption {
void set_compress_routing(const bool& enabled);
void set_print_user_defined_template(const bool& enabled);
void set_default_net_type(const std::string& default_net_type);
void set_constant_undriven_inputs(const bool& enabled);
void set_verbose_output(const bool& enabled);
private: /* Internal Data */
@ -50,6 +52,7 @@ class FabricVerilogOption {
e_verilog_default_net_type default_net_type_;
bool time_stamp_;
bool use_relative_path_;
bool constant_undriven_inputs_;
bool verbose_output_;
};

3
openfpga/src/fpga_verilog/verilog_grid.cpp
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@ -114,6 +114,7 @@ static void print_verilog_primitive_block(
/* Write the verilog module */
write_verilog_module_to_file(fp, module_manager, primitive_module, true,
options.constant_undriven_inputs(),
options.default_net_type());
/* Close file handler */
@ -234,6 +235,7 @@ static void rec_print_verilog_logical_tile(
/* Write the verilog module */
write_verilog_module_to_file(fp, module_manager, pb_module,
options.explicit_port_mapping(),
options.constant_undriven_inputs(),
options.default_net_type());
print_verilog_comment(
@ -348,6 +350,7 @@ static void print_verilog_physical_tile_netlist(
module_manager.module_name(grid_module) + " -----"));
write_verilog_module_to_file(fp, module_manager, grid_module,
options.explicit_port_mapping(),
options.constant_undriven_inputs(),
options.default_net_type());
print_verilog_comment(

1
openfpga/src/fpga_verilog/verilog_lut.cpp
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@ -63,6 +63,7 @@ void print_verilog_submodule_luts(const ModuleManager& module_manager,
fp, module_manager, lut_module,
options.explicit_port_mapping() ||
circuit_lib.dump_explicit_port_map(lut_model),
options.constant_undriven_inputs(),
options.default_net_type());
}

5
openfpga/src/fpga_verilog/verilog_memory.cpp
View File

@ -61,6 +61,7 @@ static void print_verilog_mux_memory_module(
fp, module_manager, mem_module,
options.explicit_port_mapping() ||
circuit_lib.dump_explicit_port_map(mux_model),
options.constant_undriven_inputs(),
options.default_net_type());
/* Add an empty line as a splitter */
@ -84,6 +85,7 @@ static void print_verilog_mux_memory_module(
fp, module_manager, feedthru_mem_module,
options.explicit_port_mapping() ||
circuit_lib.dump_explicit_port_map(mux_model),
options.constant_undriven_inputs(),
options.default_net_type());
/* Add an empty line as a splitter */
@ -208,6 +210,7 @@ void print_verilog_submodule_memories(
write_verilog_module_to_file(fp, module_manager, mem_module,
options.explicit_port_mapping() ||
circuit_lib.dump_explicit_port_map(model),
options.constant_undriven_inputs(),
options.default_net_type());
/* Add an empty line as a splitter */
@ -228,6 +231,7 @@ void print_verilog_submodule_memories(
write_verilog_module_to_file(fp, module_manager, feedthru_mem_module,
options.explicit_port_mapping() ||
circuit_lib.dump_explicit_port_map(model),
options.constant_undriven_inputs(),
options.default_net_type());
/* Add an empty line as a splitter */
@ -241,6 +245,7 @@ void print_verilog_submodule_memories(
/* Write the module content in Verilog format */
write_verilog_module_to_file(fp, module_manager, mem_group_module,
options.explicit_port_mapping(),
options.constant_undriven_inputs(),
options.default_net_type());
/* Add an empty line as a splitter */

24
openfpga/src/fpga_verilog/verilog_module_writer.cpp
View File

@ -147,7 +147,7 @@ static BasicPort generate_verilog_port_for_module_net(
*******************************************************************/
static void
find_verilog_module_local_undriven_wires(
std::map<std::string, std::vector<BasicPort>>& local_wires;
std::map<std::string, std::vector<BasicPort>>& local_wires,
const ModuleManager& module_manager,
const ModuleId& module_id,
const std::vector<ModuleManager::e_module_port_type>& port_type_blacklist) {
@ -572,6 +572,7 @@ static void write_verilog_instance_to_file(std::fstream& fp,
void write_verilog_module_to_file(
std::fstream& fp, const ModuleManager& module_manager,
const ModuleId& module_id, const bool& use_explicit_port_map,
const bool& constant_local_undriven_wires,
const e_verilog_default_net_type& default_net_type) {
VTR_ASSERT(true == valid_file_stream(fp));
@ -603,7 +604,26 @@ void write_verilog_module_to_file(
}
/* Use constant to drive undriven local wires */
find_verilog_module_local_undriven_wires(local_wires, module_manager, module_id, std::vector<ModuleManager::e_module_port_type>());
if (constant_local_undriven_wires) {
std::vector<ModuleManager::e_module_port_type> blacklist = {
ModuleManager::e_module_port_type::MODULE_GLOBAL_PORT,
ModuleManager::e_module_port_type::MODULE_GPIN_PORT,
ModuleManager::e_module_port_type::MODULE_GPOUT_PORT,
ModuleManager::e_module_port_type::MODULE_GPIO_PORT,
ModuleManager::e_module_port_type::MODULE_INOUT_PORT,
ModuleManager::e_module_port_type::MODULE_OUTPUT_PORT,
ModuleManager::e_module_port_type::MODULE_CLOCK_PORT
};
std::map<std::string, std::vector<BasicPort>> local_undriven_wires;
find_verilog_module_local_undriven_wires(local_undriven_wires, module_manager, module_id, blacklist);
for (std::pair<std::string, std::vector<BasicPort>> port_group :
local_undriven_wires) {
for (const BasicPort& local_undriven_wire : port_group.second) {
fp << generate_verilog_port_constant_values(local_undriven_wire, std::vector<size_t>(local_undriven_wire.get_width(), 0), false) << ";"
<< std::endl;
}
}
}
/* Print an empty line as splitter */
fp << std::endl;

1
openfpga/src/fpga_verilog/verilog_module_writer.h
View File

@ -19,6 +19,7 @@ namespace openfpga {
void write_verilog_module_to_file(
std::fstream& fp, const ModuleManager& module_manager,
const ModuleId& module_id, const bool& use_explicit_port_map,
const bool& constant_local_undriven_wires,
const e_verilog_default_net_type& default_net_type);
} /* end namespace openfpga */

2
openfpga/src/fpga_verilog/verilog_mux.cpp
View File

@ -679,6 +679,7 @@ static void generate_verilog_mux_branch_module(
fp, module_manager, mux_module,
use_explicit_port_map ||
circuit_lib.dump_explicit_port_map(mux_model),
false,
default_net_type);
/* Add an empty line as a splitter */
fp << std::endl;
@ -1423,6 +1424,7 @@ static void generate_verilog_mux_module(
circuit_lib.dump_explicit_port_map(mux_model) ||
circuit_lib.dump_explicit_port_map(
circuit_lib.pass_gate_logic_model(mux_model))),
false,
default_net_type);
/* Add an empty line as a splitter */
fp << std::endl;

2
openfpga/src/fpga_verilog/verilog_routing.cpp
View File

@ -117,6 +117,7 @@ static void print_verilog_routing_connection_box_unique_module(
/* Write the verilog module */
write_verilog_module_to_file(fp, module_manager, cb_module,
options.explicit_port_mapping(),
options.constant_undriven_inputs(),
options.default_net_type());
/* Add an empty line as a splitter */
@ -238,6 +239,7 @@ static void print_verilog_routing_switch_box_unique_module(
/* Write the verilog module */
write_verilog_module_to_file(fp, module_manager, sb_module,
options.explicit_port_mapping(),
options.constant_undriven_inputs(),
options.default_net_type());
/* Close file handler */

2
openfpga/src/fpga_verilog/verilog_shift_register_banks.cpp
View File

@ -58,6 +58,7 @@ void print_verilog_submodule_shift_register_banks(
/* Write the module content in Verilog format */
write_verilog_module_to_file(fp, module_manager, sr_module,
options.explicit_port_mapping(),
options.constant_undriven_inputs(),
options.default_net_type());
/* Add an empty line as a splitter */
@ -69,6 +70,7 @@ void print_verilog_submodule_shift_register_banks(
/* Write the module content in Verilog format */
write_verilog_module_to_file(fp, module_manager, sr_module,
options.explicit_port_mapping(),
options.constant_undriven_inputs(),
options.default_net_type());
/* Add an empty line as a splitter */

1
openfpga/src/fpga_verilog/verilog_tile.cpp
View File

@ -60,6 +60,7 @@ static int print_verilog_tile_module_netlist(
/* Write the module content in Verilog format */
write_verilog_module_to_file(fp, module_manager, tile_module,
options.explicit_port_mapping(),
options.constant_undriven_inputs(),
options.default_net_type());
/* Add an empty line as a splitter */

2
openfpga/src/fpga_verilog/verilog_top_module.cpp
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@ -63,6 +63,7 @@ void print_verilog_core_module(NetlistManager& netlist_manager,
/* Write the module content in Verilog format */
write_verilog_module_to_file(fp, module_manager, core_module,
options.explicit_port_mapping(),
options.constant_undriven_inputs(),
options.default_net_type());
/* Add an empty line as a splitter */
@ -129,6 +130,7 @@ void print_verilog_top_module(NetlistManager& netlist_manager,
/* Write the module content in Verilog format */
write_verilog_module_to_file(fp, module_manager, top_module,
options.explicit_port_mapping(),
options.constant_undriven_inputs(),
options.default_net_type());
/* Add an empty line as a splitter */