From 4e21bbb3f1bae2e15c018bf5dce54936b6be6313 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 4 Jul 2024 20:32:56 -0700 Subject: [PATCH] [core] now support constant undriven local wires in verilog writer --- .../fpga_verilog/fabric_verilog_options.cpp | 7 ++++++ .../src/fpga_verilog/fabric_verilog_options.h | 3 +++ openfpga/src/fpga_verilog/verilog_grid.cpp | 3 +++ openfpga/src/fpga_verilog/verilog_lut.cpp | 1 + openfpga/src/fpga_verilog/verilog_memory.cpp | 5 ++++ .../fpga_verilog/verilog_module_writer.cpp | 24 +++++++++++++++++-- .../src/fpga_verilog/verilog_module_writer.h | 1 + openfpga/src/fpga_verilog/verilog_mux.cpp | 2 ++ openfpga/src/fpga_verilog/verilog_routing.cpp | 2 ++ .../verilog_shift_register_banks.cpp | 2 ++ openfpga/src/fpga_verilog/verilog_tile.cpp | 1 + .../src/fpga_verilog/verilog_top_module.cpp | 2 ++ 12 files changed, 51 insertions(+), 2 deletions(-) diff --git a/openfpga/src/fpga_verilog/fabric_verilog_options.cpp b/openfpga/src/fpga_verilog/fabric_verilog_options.cpp index 17fdad397..44da5e47c 100644 --- a/openfpga/src/fpga_verilog/fabric_verilog_options.cpp +++ b/openfpga/src/fpga_verilog/fabric_verilog_options.cpp @@ -21,6 +21,7 @@ FabricVerilogOption::FabricVerilogOption() { default_net_type_ = VERILOG_DEFAULT_NET_TYPE_NONE; time_stamp_ = true; use_relative_path_ = false; + constant_undriven_inputs_ = false; verbose_output_ = false; } @@ -53,6 +54,8 @@ e_verilog_default_net_type FabricVerilogOption::default_net_type() const { return default_net_type_; } +bool FabricVerilogOption::constant_undriven_inputs() const { return constant_undriven_inputs_; } + bool FabricVerilogOption::verbose_output() const { return verbose_output_; } /****************************************************************************** @@ -106,6 +109,10 @@ void FabricVerilogOption::set_default_net_type( } } +void FabricVerilogOption::set_constant_undriven_inputs(const bool& enabled) { + constant_undriven_inputs_ = enabled; +} + void FabricVerilogOption::set_verbose_output(const bool& enabled) { verbose_output_ = enabled; } diff --git a/openfpga/src/fpga_verilog/fabric_verilog_options.h b/openfpga/src/fpga_verilog/fabric_verilog_options.h index dfa7844e9..c8d5cc5eb 100644 --- a/openfpga/src/fpga_verilog/fabric_verilog_options.h +++ b/openfpga/src/fpga_verilog/fabric_verilog_options.h @@ -28,6 +28,7 @@ class FabricVerilogOption { bool compress_routing() const; e_verilog_default_net_type default_net_type() const; bool print_user_defined_template() const; + bool constant_undriven_inputs() const; bool verbose_output() const; public: /* Public mutators */ @@ -39,6 +40,7 @@ class FabricVerilogOption { void set_compress_routing(const bool& enabled); void set_print_user_defined_template(const bool& enabled); void set_default_net_type(const std::string& default_net_type); + void set_constant_undriven_inputs(const bool& enabled); void set_verbose_output(const bool& enabled); private: /* Internal Data */ @@ -50,6 +52,7 @@ class FabricVerilogOption { e_verilog_default_net_type default_net_type_; bool time_stamp_; bool use_relative_path_; + bool constant_undriven_inputs_; bool verbose_output_; }; diff --git a/openfpga/src/fpga_verilog/verilog_grid.cpp b/openfpga/src/fpga_verilog/verilog_grid.cpp index 7d79f3a4d..7ccdd35d4 100644 --- a/openfpga/src/fpga_verilog/verilog_grid.cpp +++ b/openfpga/src/fpga_verilog/verilog_grid.cpp @@ -114,6 +114,7 @@ static void print_verilog_primitive_block( /* Write the verilog module */ write_verilog_module_to_file(fp, module_manager, primitive_module, true, + options.constant_undriven_inputs(), options.default_net_type()); /* Close file handler */ @@ -234,6 +235,7 @@ static void rec_print_verilog_logical_tile( /* Write the verilog module */ write_verilog_module_to_file(fp, module_manager, pb_module, options.explicit_port_mapping(), + options.constant_undriven_inputs(), options.default_net_type()); print_verilog_comment( @@ -348,6 +350,7 @@ static void print_verilog_physical_tile_netlist( module_manager.module_name(grid_module) + " -----")); write_verilog_module_to_file(fp, module_manager, grid_module, options.explicit_port_mapping(), + options.constant_undriven_inputs(), options.default_net_type()); print_verilog_comment( diff --git a/openfpga/src/fpga_verilog/verilog_lut.cpp b/openfpga/src/fpga_verilog/verilog_lut.cpp index fab9205e4..b20b1d07a 100644 --- a/openfpga/src/fpga_verilog/verilog_lut.cpp +++ b/openfpga/src/fpga_verilog/verilog_lut.cpp @@ -63,6 +63,7 @@ void print_verilog_submodule_luts(const ModuleManager& module_manager, fp, module_manager, lut_module, options.explicit_port_mapping() || circuit_lib.dump_explicit_port_map(lut_model), + options.constant_undriven_inputs(), options.default_net_type()); } diff --git a/openfpga/src/fpga_verilog/verilog_memory.cpp b/openfpga/src/fpga_verilog/verilog_memory.cpp index 8c56e5e8e..0e0972269 100644 --- a/openfpga/src/fpga_verilog/verilog_memory.cpp +++ b/openfpga/src/fpga_verilog/verilog_memory.cpp @@ -61,6 +61,7 @@ static void print_verilog_mux_memory_module( fp, module_manager, mem_module, options.explicit_port_mapping() || circuit_lib.dump_explicit_port_map(mux_model), + options.constant_undriven_inputs(), options.default_net_type()); /* Add an empty line as a splitter */ @@ -84,6 +85,7 @@ static void print_verilog_mux_memory_module( fp, module_manager, feedthru_mem_module, options.explicit_port_mapping() || circuit_lib.dump_explicit_port_map(mux_model), + options.constant_undriven_inputs(), options.default_net_type()); /* Add an empty line as a splitter */ @@ -208,6 +210,7 @@ void print_verilog_submodule_memories( write_verilog_module_to_file(fp, module_manager, mem_module, options.explicit_port_mapping() || circuit_lib.dump_explicit_port_map(model), + options.constant_undriven_inputs(), options.default_net_type()); /* Add an empty line as a splitter */ @@ -228,6 +231,7 @@ void print_verilog_submodule_memories( write_verilog_module_to_file(fp, module_manager, feedthru_mem_module, options.explicit_port_mapping() || circuit_lib.dump_explicit_port_map(model), + options.constant_undriven_inputs(), options.default_net_type()); /* Add an empty line as a splitter */ @@ -241,6 +245,7 @@ void print_verilog_submodule_memories( /* Write the module content in Verilog format */ write_verilog_module_to_file(fp, module_manager, mem_group_module, options.explicit_port_mapping(), + options.constant_undriven_inputs(), options.default_net_type()); /* Add an empty line as a splitter */ diff --git a/openfpga/src/fpga_verilog/verilog_module_writer.cpp b/openfpga/src/fpga_verilog/verilog_module_writer.cpp index 7feaa1c28..1c5ce17ad 100644 --- a/openfpga/src/fpga_verilog/verilog_module_writer.cpp +++ b/openfpga/src/fpga_verilog/verilog_module_writer.cpp @@ -147,7 +147,7 @@ static BasicPort generate_verilog_port_for_module_net( *******************************************************************/ static void find_verilog_module_local_undriven_wires( - std::map>& local_wires; + std::map>& local_wires, const ModuleManager& module_manager, const ModuleId& module_id, const std::vector& port_type_blacklist) { @@ -572,6 +572,7 @@ static void write_verilog_instance_to_file(std::fstream& fp, void write_verilog_module_to_file( std::fstream& fp, const ModuleManager& module_manager, const ModuleId& module_id, const bool& use_explicit_port_map, + const bool& constant_local_undriven_wires, const e_verilog_default_net_type& default_net_type) { VTR_ASSERT(true == valid_file_stream(fp)); @@ -603,7 +604,26 @@ void write_verilog_module_to_file( } /* Use constant to drive undriven local wires */ - find_verilog_module_local_undriven_wires(local_wires, module_manager, module_id, std::vector()); + if (constant_local_undriven_wires) { + std::vector blacklist = { + ModuleManager::e_module_port_type::MODULE_GLOBAL_PORT, + ModuleManager::e_module_port_type::MODULE_GPIN_PORT, + ModuleManager::e_module_port_type::MODULE_GPOUT_PORT, + ModuleManager::e_module_port_type::MODULE_GPIO_PORT, + ModuleManager::e_module_port_type::MODULE_INOUT_PORT, + ModuleManager::e_module_port_type::MODULE_OUTPUT_PORT, + ModuleManager::e_module_port_type::MODULE_CLOCK_PORT + }; + std::map> local_undriven_wires; + find_verilog_module_local_undriven_wires(local_undriven_wires, module_manager, module_id, blacklist); + for (std::pair> port_group : + local_undriven_wires) { + for (const BasicPort& local_undriven_wire : port_group.second) { + fp << generate_verilog_port_constant_values(local_undriven_wire, std::vector(local_undriven_wire.get_width(), 0), false) << ";" + << std::endl; + } + } + } /* Print an empty line as splitter */ fp << std::endl; diff --git a/openfpga/src/fpga_verilog/verilog_module_writer.h b/openfpga/src/fpga_verilog/verilog_module_writer.h index 8e11637a7..0657c3985 100644 --- a/openfpga/src/fpga_verilog/verilog_module_writer.h +++ b/openfpga/src/fpga_verilog/verilog_module_writer.h @@ -19,6 +19,7 @@ namespace openfpga { void write_verilog_module_to_file( std::fstream& fp, const ModuleManager& module_manager, const ModuleId& module_id, const bool& use_explicit_port_map, + const bool& constant_local_undriven_wires, const e_verilog_default_net_type& default_net_type); } /* end namespace openfpga */ diff --git a/openfpga/src/fpga_verilog/verilog_mux.cpp b/openfpga/src/fpga_verilog/verilog_mux.cpp index 6fd2b2df4..38fcc0224 100644 --- a/openfpga/src/fpga_verilog/verilog_mux.cpp +++ b/openfpga/src/fpga_verilog/verilog_mux.cpp @@ -679,6 +679,7 @@ static void generate_verilog_mux_branch_module( fp, module_manager, mux_module, use_explicit_port_map || circuit_lib.dump_explicit_port_map(mux_model), + false, default_net_type); /* Add an empty line as a splitter */ fp << std::endl; @@ -1423,6 +1424,7 @@ static void generate_verilog_mux_module( circuit_lib.dump_explicit_port_map(mux_model) || circuit_lib.dump_explicit_port_map( circuit_lib.pass_gate_logic_model(mux_model))), + false, default_net_type); /* Add an empty line as a splitter */ fp << std::endl; diff --git a/openfpga/src/fpga_verilog/verilog_routing.cpp b/openfpga/src/fpga_verilog/verilog_routing.cpp index dbe59e935..3826a2552 100644 --- a/openfpga/src/fpga_verilog/verilog_routing.cpp +++ b/openfpga/src/fpga_verilog/verilog_routing.cpp @@ -117,6 +117,7 @@ static void print_verilog_routing_connection_box_unique_module( /* Write the verilog module */ write_verilog_module_to_file(fp, module_manager, cb_module, options.explicit_port_mapping(), + options.constant_undriven_inputs(), options.default_net_type()); /* Add an empty line as a splitter */ @@ -238,6 +239,7 @@ static void print_verilog_routing_switch_box_unique_module( /* Write the verilog module */ write_verilog_module_to_file(fp, module_manager, sb_module, options.explicit_port_mapping(), + options.constant_undriven_inputs(), options.default_net_type()); /* Close file handler */ diff --git a/openfpga/src/fpga_verilog/verilog_shift_register_banks.cpp b/openfpga/src/fpga_verilog/verilog_shift_register_banks.cpp index f2c0e02e6..6d4707b1e 100644 --- a/openfpga/src/fpga_verilog/verilog_shift_register_banks.cpp +++ b/openfpga/src/fpga_verilog/verilog_shift_register_banks.cpp @@ -58,6 +58,7 @@ void print_verilog_submodule_shift_register_banks( /* Write the module content in Verilog format */ write_verilog_module_to_file(fp, module_manager, sr_module, options.explicit_port_mapping(), + options.constant_undriven_inputs(), options.default_net_type()); /* Add an empty line as a splitter */ @@ -69,6 +70,7 @@ void print_verilog_submodule_shift_register_banks( /* Write the module content in Verilog format */ write_verilog_module_to_file(fp, module_manager, sr_module, options.explicit_port_mapping(), + options.constant_undriven_inputs(), options.default_net_type()); /* Add an empty line as a splitter */ diff --git a/openfpga/src/fpga_verilog/verilog_tile.cpp b/openfpga/src/fpga_verilog/verilog_tile.cpp index da32fc58c..f6b10beaf 100644 --- a/openfpga/src/fpga_verilog/verilog_tile.cpp +++ b/openfpga/src/fpga_verilog/verilog_tile.cpp @@ -60,6 +60,7 @@ static int print_verilog_tile_module_netlist( /* Write the module content in Verilog format */ write_verilog_module_to_file(fp, module_manager, tile_module, options.explicit_port_mapping(), + options.constant_undriven_inputs(), options.default_net_type()); /* Add an empty line as a splitter */ diff --git a/openfpga/src/fpga_verilog/verilog_top_module.cpp b/openfpga/src/fpga_verilog/verilog_top_module.cpp index b8c302f21..60ed91956 100644 --- a/openfpga/src/fpga_verilog/verilog_top_module.cpp +++ b/openfpga/src/fpga_verilog/verilog_top_module.cpp @@ -63,6 +63,7 @@ void print_verilog_core_module(NetlistManager& netlist_manager, /* Write the module content in Verilog format */ write_verilog_module_to_file(fp, module_manager, core_module, options.explicit_port_mapping(), + options.constant_undriven_inputs(), options.default_net_type()); /* Add an empty line as a splitter */ @@ -129,6 +130,7 @@ void print_verilog_top_module(NetlistManager& netlist_manager, /* Write the module content in Verilog format */ write_verilog_module_to_file(fp, module_manager, top_module, options.explicit_port_mapping(), + options.constant_undriven_inputs(), options.default_net_type()); /* Add an empty line as a splitter */