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[core] code format

This commit is contained in:
tangxifan 2024-07-10 15:07:26 -07:00
parent a390aad0b8
commit c96f899c53
5 changed files with 23 additions and 18 deletions
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16
libs/libclkarchopenfpga/src/base/clock_network.cpp
View File

@ -535,13 +535,17 @@ std::vector<std::string> ClockNetwork::flatten_internal_driver_from_pin(
std::vector<std::string> flatten_taps;
BasicPort des_pin = internal_driver_to_pin(int_driver_id);
if (!des_pin.is_valid()) {
VTR_LOG_ERROR("Invalid internal driver destination port name '%s' whose index is not valid\n",
des_pin.to_verilog_string().c_str());
VTR_LOG_ERROR(
"Invalid internal driver destination port name '%s' whose index is not "
"valid\n",
des_pin.to_verilog_string().c_str());
exit(1);
}
if (des_pin.get_width() != 1) {
VTR_LOG_ERROR("Invalid internal driver destination port name '%s' whose width is not 1\n",
des_pin.to_verilog_string().c_str());
VTR_LOG_ERROR(
"Invalid internal driver destination port name '%s' whose width is not "
"1\n",
des_pin.to_verilog_string().c_str());
exit(1);
}
if (des_pin.get_lsb() != size_t(clk_pin_id)) {
@ -795,8 +799,8 @@ ClockInternalDriverId ClockNetwork::add_spine_switch_point_internal_driver(
PortParser to_pin_parser(int_driver_to_port);
/* Find any existing id for the driver port */
for (ClockInternalDriverId int_driver_id : internal_driver_ids_) {
if (internal_driver_from_pins_[int_driver_id] == int_driver_from_port
&& internal_driver_to_pins_[int_driver_id] == to_pin_parser.port()) {
if (internal_driver_from_pins_[int_driver_id] == int_driver_from_port &&
internal_driver_to_pins_[int_driver_id] == to_pin_parser.port()) {
spine_switch_internal_drivers_[spine_id][size_t(switch_point_id)]
.push_back(int_driver_id);
return int_driver_id;

3
libs/libclkarchopenfpga/src/base/clock_network.h
View File

@ -225,7 +225,8 @@ class ClockNetwork {
const vtr::Point<int>& coord);
ClockInternalDriverId add_spine_switch_point_internal_driver(
const ClockSpineId& spine_id, const ClockSwitchPointId& switch_point_id,
const std::string& internal_driver_from_port, const std::string& internal_driver_to_port);
const std::string& internal_driver_from_port,
const std::string& internal_driver_to_port);
ClockTapId add_tree_tap(const ClockTreeId& tree_id,
const BasicPort& from_port,
const std::string& to_port);

6
libs/libclkarchopenfpga/src/io/read_xml_clock_network.cpp
View File

@ -169,9 +169,9 @@ static void read_xml_clock_spine_switch_point_internal_driver(
XML_CLOCK_SPINE_SWITCH_POINT_INTERNAL_DRIVER_ATTRIBUTE_FROM_PIN, loc_data)
.as_string();
std::string int_driver_to_port_name =
get_attribute(
xml_int_driver,
XML_CLOCK_SPINE_SWITCH_POINT_INTERNAL_DRIVER_ATTRIBUTE_TO_PIN, loc_data)
get_attribute(xml_int_driver,
XML_CLOCK_SPINE_SWITCH_POINT_INTERNAL_DRIVER_ATTRIBUTE_TO_PIN,
loc_data)
.as_string();
clk_ntwk.add_spine_switch_point_internal_driver(spine_id, switch_point_id,
int_driver_from_port_name,

4
libs/libclkarchopenfpga/src/io/write_xml_clock_network.cpp
View File

@ -130,7 +130,9 @@ static int write_xml_clock_spine_switch_point(
clk_ntwk.internal_driver_from_pin(int_driver_id).c_str());
write_xml_attribute(
fp, XML_CLOCK_SPINE_SWITCH_POINT_INTERNAL_DRIVER_ATTRIBUTE_TO_PIN,
clk_ntwk.internal_driver_to_pin(int_driver_id).to_verilog_string().c_str());
clk_ntwk.internal_driver_to_pin(int_driver_id)
.to_verilog_string()
.c_str());
fp << "/>"
<< "\n";
}

12
openfpga/src/annotation/append_clock_rr_graph.cpp
View File

@ -590,8 +590,7 @@ static void try_find_and_add_clock_opin2track_node(
std::vector<RRNodeId>& opin_nodes, const DeviceGrid& grids,
const RRGraphView& rr_graph_view, const size_t& layer,
const vtr::Point<int>& grid_coord, const e_side& pin_side,
const ClockNetwork& clk_ntwk,
const ClockTreePinId& clk_pin,
const ClockNetwork& clk_ntwk, const ClockTreePinId& clk_pin,
const ClockInternalDriverId& int_driver_id) {
t_physical_tile_type_ptr grid_type = grids.get_physical_type(
t_physical_tile_loc(grid_coord.x(), grid_coord.y(), layer));
@ -637,8 +636,7 @@ static void try_find_and_add_clock_opin2track_node(
static std::vector<RRNodeId> find_clock_opin2track_node(
const DeviceGrid& grids, const RRGraphView& rr_graph_view,
const size_t& layer, const vtr::Point<int>& sb_coord,
const ClockNetwork& clk_ntwk,
const ClockTreePinId& clk_pin,
const ClockNetwork& clk_ntwk, const ClockTreePinId& clk_pin,
const std::vector<ClockInternalDriverId>& int_driver_ids) {
std::vector<RRNodeId> opin_nodes;
/* Find opins from
@ -661,9 +659,9 @@ static std::vector<RRNodeId> find_clock_opin2track_node(
vtr::Point<int> grid_coord = grid_coords[igrid];
for (e_side grid_side : grid_sides[igrid]) {
for (ClockInternalDriverId int_driver_id : int_driver_ids) {
try_find_and_add_clock_opin2track_node(opin_nodes, grids, rr_graph_view,
layer, grid_coord, grid_side,
clk_ntwk, clk_pin, int_driver_id);
try_find_and_add_clock_opin2track_node(
opin_nodes, grids, rr_graph_view, layer, grid_coord, grid_side,
clk_ntwk, clk_pin, int_driver_id);
}
}
}