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[core] add new command line option 'constant_undriven_inputs'

This commit is contained in:
tangxifan 2024-07-04 20:39:02 -07:00
parent 4e21bbb3f1
commit 72ee39f178
2 changed files with 15 additions and 0 deletions
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4
openfpga/src/base/openfpga_verilog_command_template.h
View File

@ -30,6 +30,10 @@ ShellCommandId add_write_fabric_verilog_command_template(
shell_cmd.set_option_short_name(output_opt, "f");
shell_cmd.set_option_require_value(output_opt, openfpga::OPT_STRING);
/* Add an option '--constant_undriven_inputs' */
shell_cmd.add_option("constant_undriven_inputs", false,
"Use constant gnd for undriven wires in Verilog netlists. Recommand to enable when there are boundary routing tracks in FPGA fabric");
/* Add an option '--explicit_port_mapping' */
shell_cmd.add_option("explicit_port_mapping", false,
"Use explicit port mapping in Verilog netlists");

11
openfpga/src/base/openfpga_verilog_template.h
View File

@ -28,6 +28,8 @@ int write_fabric_verilog_template(T& openfpga_ctx, const Command& cmd,
CommandOptionId opt_output_dir = cmd.option("file");
CommandOptionId opt_explicit_port_mapping =
cmd.option("explicit_port_mapping");
CommandOptionId opt_constant_undriven_inputs =
cmd.option("constant_undriven_inputs");
CommandOptionId opt_include_timing = cmd.option("include_timing");
CommandOptionId opt_print_user_defined_template =
cmd.option("print_user_defined_template");
@ -56,6 +58,15 @@ int write_fabric_verilog_template(T& openfpga_ctx, const Command& cmd,
}
options.set_verbose_output(cmd_context.option_enable(cmd, opt_verbose));
options.set_compress_routing(openfpga_ctx.flow_manager().compress_routing());
/* For perimeter cb, enable the constant undriven inputs, unless it is off by user */
if (g_vpr_ctx.device().arch->perimeter_cb) {
options.set_constant_undriven_inputs(true);
VTR_LOG("Automatically enable the constant_undriven_input option as perimeter connection blocks are seen in FPGA fabric\n");
if (!cmd_context.option_enable(cmd, opt_constant_undriven_inputs)) {
VTR_LOG("User forces to disable the constant_undriven_input option even when perimeter connection blocks are enabled\n");
}
}
options.set_constant_undriven_inputs(cmd_context.option_enable(cmd, opt_constant_undriven_inputs));
return fpga_fabric_verilog(
openfpga_ctx.mutable_module_graph(),