riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

[core] removing the restrictions on only 1 clock tree is supported in programmable clock network

This commit is contained in:
tangxifan 2024-06-21 19:00:01 -07:00
parent 292f4a9273
commit d2053db21c
1 changed files with 0 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
openfpga/src/annotation/route_clock_rr_graph.cpp
View File

@ -210,14 +210,6 @@ int route_clock_rr_graph(VprRoutingAnnotation& vpr_routing_annotation,
return CMD_EXEC_SUCCESS;
}
/* Report any clock structure we do not support yet! */
if (clk_ntwk.num_trees() > 1) {
VTR_LOG(
"Currently only support 1 clock tree in programmable clock "
"architecture\nPlease update your clock architecture definition\n");
return CMD_EXEC_FATAL_ERROR;
}
/* If there are multiple clock signals from the netlist, require pin
* constraints */
std::vector<std::string> clock_net_names =