[test] fixed a bug where ace is no required
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@ -19,7 +19,7 @@ append_clock_rr_graph
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# Annotate the OpenFPGA architecture to VPR data base
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# to debug use --verbose options
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link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
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link_openfpga_arch --sort_gsb_chan_node_in_edges
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# Route clock based on clock network definition
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route_clock_rr_graph --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE}
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