diff --git a/openfpga_flow/openfpga_shell_scripts/example_clkntwk_no_ace_script.openfpga b/openfpga_flow/openfpga_shell_scripts/example_clkntwk_no_ace_script.openfpga
index 83cc44860..1cdaa1932 100644
--- a/openfpga_flow/openfpga_shell_scripts/example_clkntwk_no_ace_script.openfpga
+++ b/openfpga_flow/openfpga_shell_scripts/example_clkntwk_no_ace_script.openfpga
@@ -19,7 +19,7 @@ append_clock_rr_graph
 
 # Annotate the OpenFPGA architecture to VPR data base
 # to debug use --verbose options
-link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
+link_openfpga_arch --sort_gsb_chan_node_in_edges
 
 # Route clock based on clock network definition
 route_clock_rr_graph --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE}