Commit Graph

426 Commits

Author SHA1 Message Date
tangxifan 3a5c26c6a1 [Test] Update IWLS test by using new architecture and customize DFF techmap 2021-04-21 19:51:25 -06:00
tangxifan 8046b16c15 [Test] Remove restrictions in the multi-clock test case and deploy new microbenchmarks for testing 2021-04-21 14:04:34 -06:00
tangxifan 578d81b67a [Test] Patch task configuration file 2021-04-19 16:15:00 -06:00
tangxifan 5976cc0a1c [Test] Add test case for using bitstream setting to overload default paths for pb_type interconnection 2021-04-19 15:54:18 -06:00
tangxifan da95da933b [Test] Add pin constraint file to map reset to correct FPGA pins 2021-04-17 15:04:26 -06:00
tangxifan c020333512
Merge branch 'master' into dff_techmap 2021-04-16 20:54:28 -06:00
tangxifan 7172fc9ea1 [Test] Patch test for architecture using asynchronous DFFs 2021-04-16 20:48:37 -06:00
tangxifan 93be81abe1 [Test] Add test case for architecture using DFF with reset 2021-04-16 20:00:48 -06:00
tangxifan 1566a5558a [Test] Add task configuration file for iwls2005 2021-04-16 16:10:31 -06:00
tangxifan b469705819
Merge branch 'master' into fpga_sdc_test 2021-04-11 21:14:46 -06:00
tangxifan 94c4c817eb [Test] Expand sdc time unit test to sweep all the available units 2021-04-11 20:14:09 -06:00
tangxifan a4893e27cf [Test] Update generate_fabric and generate_testbench test cases; Now generate_testbench tese case use the fabric netlist generated by the generate_fabric test case to run HDL verification 2021-04-11 17:26:27 -06:00
tangxifan 44d97ead86
Merge branch 'master' into hetergeneous_arch 2021-03-23 17:05:03 -06:00
tangxifan 8c970a792a [Test] Add a new test case for heterogeneous FPGA using single-mode 8-bit multiplier 2021-03-23 15:33:00 -06:00
tangxifan 351dec5935 [Test] Add QoR csv file for vtr benchmarks 2021-03-23 11:15:02 -06:00
tangxifan 61eddb08de [Test] Update task configuration by commenting out high-runtime VTR benchmarks 2021-03-22 14:42:42 -06:00
tangxifan 4bfd0c0a02 [Test] Enable more VTR benchmark in testing 2021-03-22 12:53:30 -06:00
tangxifan cc10b10703 [Test] Enable more benchmarks for testing; See problems when mapping BRAMs 2021-03-20 22:53:37 -06:00
tangxifan 9a3aff274f [Test] Use fix routing channel width to save runtime for VTR benchmarks 2021-03-20 21:59:44 -06:00
tangxifan ca9a70fc88 [Test] Comment out benchmarks have problems in synthesis 2021-03-20 21:29:21 -06:00
tangxifan 125e94a6b3 [Test] Add full VTR benchmark (with most commented); ready for massive testing 2021-03-20 21:01:18 -06:00
tangxifan f3792bc6f6 [Test] Update VTR benchmark test case to include DSP example benchmark 2021-03-20 18:09:19 -06:00
tangxifan 1976a8068f [Test] Add test case to run vtr benchmarks (Currently, only ch_instrinsic is included; more to be added) 2021-03-17 15:11:17 -06:00
tangxifan e1f8b252b1 Merge branch 'master' into yosys_heterogeneous_block_support 2021-03-16 20:05:21 -06:00
tangxifan d12a8a03fd [Test] Update test case using yosys bram parameters 2021-03-16 19:52:17 -06:00
tangxifan 73b06256d0 [Test] Deploy the new yosys script supporting BRAM to regression tests 2021-03-16 16:52:59 -06:00
tangxifan e61857aa2b
Merge branch 'master' into ganesh_dev 2021-03-11 19:17:02 -07:00
tangxifan 366bec232c [Test] Now lut_adder_test passed end-of-flow verification; Deploy it to CI 2021-03-11 15:25:48 -07:00
tangxifan a6186db315 [Test] Update bitstream annotation with new syntax 2021-03-10 20:45:17 -07:00
tangxifan 7d07f5d8cb [Test] Update bitstream setting example with mode bit overwriting 2021-03-10 15:34:53 -07:00
tangxifan d21909ad6c [Test] Use custom rewriting script in lut_adder test 2021-03-10 13:48:20 -07:00
Tarachand Pagarani db8ea86b2f update tests to use no_ff_map and remove tests that need async set/reset for now 2021-03-10 10:04:45 -08:00
Tarachand Pagarani 608bd1f658 comment out desings that utilize local async reset/preset 2021-03-09 19:24:01 -08:00
Tarachand Pagarani 7f4c20ff33 comment out desings that utilize local async reset/preset 2021-03-09 10:37:06 -08:00
Tarachand Pagarani c4b83aeaa9 bypas ff map for quicklogic example openfpga flow till xml can support ff pb_type 2021-03-09 00:46:40 -08:00
tangxifan 37aa42d305 [Test] Patch task configuration file for lut_adder_test to use correct rewrite script 2021-03-08 21:38:51 -07:00
Lalit Sharma 7945628307 Adding YOSYS_ARGS instead of YOSYS_MODE. Also commenting vpr_formal_verification for lut_adder_test. Ganesh to do changes to allow yosys generated verilog to be used for verification 2021-03-07 22:25:01 -08:00
Lalit Sharma 6a1ce01084 Replacing YOSYS_FAMILY & YOSYS_MODE with YOSYS_ARGS 2021-03-07 22:02:11 -08:00
Lalit Sharma 0cbad747a1 Incorporating review comments on approach to follow to dynamically select yosys_mode and yosys_family 2021-03-04 01:10:47 -08:00
Lalit Sharma 817729ac86 Added variable YOSYS_MODE, YOSYS_FAMILY in ys script to dynamically pick adder/no_adder mode or family. User can specify their choice in SYNTHESIS_PARAM: bench_yosys_mode, bench_yosys_family variables 2021-03-01 22:31:15 -08:00
tangxifan e34380a654
Merge branch 'master' into default_net_type 2021-03-01 08:38:58 -07:00
Lalit Sharma ea4aee8cb2 For time-being yosys script running in no_adder mode. 2021-02-28 22:07:23 -08:00
tangxifan b90a17543d [Test] Add new test case to test default nettype in different verilog syntax 2021-02-28 16:16:45 -07:00
tangxifan 9f4d05da67 [Test] Bug fix for new test case 2021-02-28 16:11:30 -07:00
tangxifan 18a7041424 [Test] Add default net type test for explicit port mapping 2021-02-28 12:31:32 -07:00
tangxifan ff29cc3dff [Test] Move tests to a test group 2021-02-28 12:23:35 -07:00
tangxifan 9cb1ca42fe [Test] Deploy default net type option to test case 2021-02-28 12:20:43 -07:00
tangxifan 0d82e4939c [Test] Use unified quicklogic synthesis script and enable end-of-flow tests 2021-02-26 09:35:40 -07:00
tangxifan 870d3a0e27 Merge branch 'master' into dev 2021-02-26 09:28:42 -07:00
Lalit Sharma 1082d3c677 Renaming file qlf_k4n8_yosys.ys to qlf_yosys.ys 2021-02-25 23:39:07 -08:00
Lalit Sharma 1e48d4f6dc Modifying custom yosys script file name 2021-02-25 22:21:39 -08:00
tangxifan a62786986b [Test] Turn off verification in adder lut test temporarily 2021-02-23 19:03:25 -07:00
tangxifan 53df7f69e7 [Test] Bug fix in the test case using lut adder 2021-02-23 16:59:46 -07:00
tangxifan db71cc8a16 [Test] Add LUT adder test using quicklogic synthesis script 2021-02-23 16:50:58 -07:00
tangxifan 19f6b221b1 [Test] Rework comments on runtime 2021-02-22 15:25:57 -07:00
tangxifan 4803b0ce42 [Test] Add test case for sdc controller 2021-02-22 15:02:14 -07:00
tangxifan 2e2b1cb6e7 [Test] Use hetergenenous FPGA architecture in quicklogic tests 2021-02-22 13:41:04 -07:00
tangxifan bc30f62c5a [Test] Add test for sdc controller 2021-02-22 12:41:53 -07:00
tangxifan 60dc194d8f [Test] Bug fix in the 5clock test case 2021-02-22 11:46:23 -07:00
tangxifan 71e0026a50 [Test] Add new test for 5-clock counter to quicklogic tests 2021-02-22 11:32:17 -07:00
tangxifan bc8aa0ebc6 [Test] Remove routing test from quicklogic's flow test 2021-02-22 10:22:47 -07:00
tangxifan 9b6b2068ee [Test] Move MCNC test to benchmark sweep test group 2021-02-22 10:18:34 -07:00
tangxifan c1f4a434e4 [Doc] Update README for the regression test tasks 2021-02-22 10:17:02 -07:00
Lalit Narain Sharma be5e0cdea9
Merge pull request #241 from lnis-uofu/add_quicklogic_tests
Adding quicklogic tests and updating the corresponding conf file to r…
2021-02-22 09:50:26 +05:30
Lalit Sharma 576e6753f6 Removing 2 more tests which are variant of and design 2021-02-19 09:11:19 -08:00
Lalit Sharma 6de0954ca5 Uncommenting all benchmarks except 2 that requires multiple clocks 2021-02-19 08:40:26 -08:00
tangxifan e19fc15fec [Test] bug fix in test case 2021-02-18 19:37:45 -07:00
tangxifan 2e88b035ed [Test] Add wire LUT repacker test case 2021-02-18 19:37:44 -07:00
Lalit Sharma 69cdc11ea5 Uncommenting the tests that are running fine 2021-02-18 04:17:12 -08:00
tangxifan d85d6e964e
Merge pull request #227 from watcag/master
Standard-cell flow
2021-02-17 10:11:34 -07:00
Lalit Sharma 44a979288b Adding quicklogic tests and updating the corresponding conf file to run them 2021-02-16 23:08:38 -08:00
Tarachand Pagarani 426b6449d8 change the test to turn off power analysis 2021-02-15 02:45:38 -08:00
tangxifan 3ae501a5ea [Test] Update test case to use dedicated eblif file 2021-02-09 15:51:57 -07:00
tangxifan 2b51b36dd6 [Test] Now use the super LUT arch in the test case 2021-02-09 15:27:44 -07:00
tangxifan 56284059de [Test] Add a test case for a super LUT 2021-02-09 15:25:32 -07:00
Nachiket Kapre 6bb2e29f17 default to ns for time unit -- synopsys dc whines 2021-02-09 17:04:52 -05:00
Nachiket Kapre 87c69460df what is going on 2021-02-09 11:33:08 -05:00
Nachiket Kapre cc74c6268a trying fix chan width 2021-02-09 11:28:19 -05:00
Nachiket Kapre b14b5f975d adding sweep for W 2021-02-09 08:48:25 -05:00
Nachiket Kapre d040ba569c merge for consideration; 2021-02-08 21:29:34 -05:00
Nachiket Kapre 94f858fcde merge for consideration; 2021-02-08 21:27:01 -05:00
tangxifan 8853370c60 [Script, Benchmark, Test] Now use circuit format in openfpga shell script to specify eblif file 2021-02-04 20:20:10 -07:00
tangxifan 31441c0b64 [Test] Deploy adder_8 to soft adder test 2021-02-03 09:26:38 -07:00
tangxifan 8e36ed1ab6 [Test] Update task configuration to use and2 eblif 2021-02-02 15:01:15 -07:00
tangxifan 5e2847bc41 [Test] Update test case to use eblif file 2021-02-02 09:33:41 -07:00
tangxifan 9ff5e7926b [Test] Update test case to use the adder benchmark 2021-02-02 09:24:39 -07:00
tangxifan 04594cb7ab [Test] Adapt bitstream annotatin file to parser's requirement 2021-02-01 17:38:36 -07:00
tangxifan 280c9620aa [Test] Add an example bitstream annotation file 2021-02-01 16:01:21 -07:00
tangxifan 940dce469a [Test] Bug fix for test case configuration 2021-02-01 11:19:47 -07:00
tangxifan a80acfb547 [Test] Add new test case to CI script 2021-02-01 11:16:12 -07:00
tangxifan af630dab1e [Test] Add soft adder test case. This is placeholder. Test arch will be elaborated 2021-02-01 10:53:38 -07:00
tangxifan 9cce411eda [Test] Add adder test cases 2021-02-01 10:42:24 -07:00
AurelienAlacchi 3f5cc59c0a
Microbenchmarks of Single-Port RAM and Associated Example Architecture Files as well as Test Cases (#200)
* Add required files for LUTRAM integration and testing

* Add task for lutram

* Repair format (tab and space mismatched)

* Add disclaimer in architecture file

Co-authored-by: Aur??Lien ALACCHI <u1235811@lnissrv4.eng.utah.edu>
2021-01-29 10:19:05 -07:00
tangxifan af0646260c [Test] Bug fix in pin constraints 2021-01-19 17:44:05 -07:00
tangxifan 186f2f1968 [Test] Use pin constraint in multi-clock test case 2021-01-19 17:42:40 -07:00
tangxifan e17a5cbbf2 [Test] Rename to pin constraint to comply with libpcf requirement 2021-01-19 15:52:51 -07:00
tangxifan ab25e1af5f [Test] Add example XML for net mapping between benchmark to FPGA 2021-01-19 09:29:21 -07:00
tangxifan ea9d6bfe91 [Flow] Update the design constraint file to follow bug fix in parser 2021-01-17 10:41:01 -07:00
tangxifan dd74f05a31 [Test] Add repack constraints to tests 2021-01-17 10:35:36 -07:00
tangxifan d0e05b3575 [Lib] Now use pb_type in design constraints instead of physical tiles 2021-01-16 21:35:43 -07:00
tangxifan 8578c1ecac [Flow] Rename the design contraint file syntax 2021-01-16 15:35:13 -07:00
tangxifan 9154cfdeec [Flow] Add comments for the design constraint file 2021-01-16 15:34:01 -07:00
tangxifan 6ab0f71896 [Test] Add an example of repack pin constraints file 2021-01-16 14:38:39 -07:00
tangxifan 3b5394b45f [Test] Now use dedicated simulation settings for the 4-clock architecture 2021-01-14 15:40:16 -07:00
tangxifan 314e458632 [Test] Update task configuration to use post-yosys .v file in verification 2021-01-13 15:42:45 -07:00
tangxifan 91f12071d5 [Test] Use counter4bit in the multi-clock test 2021-01-13 13:34:59 -07:00
tangxifan 250adb01cf [Test] Update test case to use blif_vpr flow with detailed explaination on the choice 2021-01-13 13:18:31 -07:00
tangxifan 99e2a068fb [Test] Add a test case for multi-clock 2021-01-12 18:06:25 -07:00
tangxifan e58e1e86c2 [Test] Update test case to use new shell script 2021-01-10 11:09:10 -07:00
tangxifan 1c68e43acf [Test] Add new test case for registerable I/O architecture 2021-01-10 11:00:21 -07:00
tangxifan 43418cd76b [Test] Deploy pipeplined and2 to test cases 2021-01-10 10:28:22 -07:00
tangxifan 06af30ef10 [Test] Add test case for the SCFF usage in configuration chain 2021-01-04 17:30:19 -07:00
Lalit Sharma 2484721a45 Updating write_verilog_testbench by removing option explicit_port_mapping 2020-12-22 22:17:50 -08:00
Lalit Sharma 3c9e4919b4 Updating variable name in ys to call BLIF output file. 2020-12-18 03:18:46 -08:00
Lalit Sharma 891e2f8aa3 Adding arch xml from SOFA repo. Also updating the script with its file location 2020-12-16 04:14:18 -08:00
Lalit Sharma 0ee3efb306 Adding a testcase to run yosys quicklogic flow 2020-12-10 02:41:43 -08:00
tangxifan 6b50bbf986
Merge pull request #134 from lnis-uofu/ganesh_dev
Support Delay Customization in OpenFPGA Task Configuration File
2020-12-08 15:32:48 -07:00
tangxifan 0cb8457e21 [Test] Add test case for tileable I/O 2020-12-04 16:02:47 -07:00
tangxifan 179b0ce304 [Test] Use formal verification method to reduce the runtime of iverilog simulation for global tile 2020-11-30 18:11:47 -07:00
tangxifan 27a480b5f8 [Test] arch name fix in the test case 2020-11-30 17:45:54 -07:00
tangxifan a1d3b439d3 [Test] Add a new test case to define a global reset port from a global tile port 2020-11-30 17:19:12 -07:00
ganeshgore 7db030018c [Bug] Fixed variable file location 2020-11-25 22:44:40 -07:00
tangxifan b8559249dc [Test] Bug fix in task configuration file 2020-11-25 22:23:27 -07:00
tangxifan 26e4db56ad [Test] Add new test case for the native fracturable LUT4 2020-11-25 22:21:23 -07:00
ganeshgore fefba0db59 Merge remote-tracking branch 'lnis_origin/master' into ganesh_dev 2020-11-25 17:29:53 -07:00
ganeshgore 1d993296d8 [Flow] Example of using test variable in task conf 2020-11-25 17:25:12 -07:00
tangxifan 617f7e3062 [Flow] disable signal initialization for behavioral verilog generation 2020-11-22 21:13:22 -07:00
tangxifan 655da9f3d0 [Flow] Rename OpenFPGA shell script folder name to consistent with naming convention 2020-11-22 16:37:19 -07:00
tangxifan 845436fa71 [Test] Add sequential benchmark for global tile clock test case 2020-11-17 14:34:54 -07:00
tangxifan 485258a9ea [Test] Add test case for global clock from tiles 2020-11-10 19:24:25 -07:00
tangxifan 6b48ee7f0b [Test] Add new test for caravel io support 2020-11-04 20:58:40 -07:00
tangxifan 61376a2979 [Test] Add test cases for various tile organization 2020-11-04 16:32:52 -07:00
tangxifan 65ca53ac98 [Test] Update test case with the new arch name 2020-11-02 13:16:42 -07:00
tangxifan bc00dee858 [Test] Add test case for embedded I/O 2020-11-02 12:28:25 -07:00
tangxifan 4c14428400 [Test] Add test case for fast configuration support on multi-region frame-based configuration protocol 2020-10-30 10:50:00 -06:00
tangxifan ca7d43275d [Test] Add test case for multi_region configuration frame 2020-10-30 10:48:29 -06:00
tangxifan 241ebf054a [Test] Add a test case for validating fast configuration techniques on multi-region memory banks 2020-10-29 16:29:46 -06:00
tangxifan ff386001c4 [Test] Add openfpga task for multi-region memory banks 2020-10-29 13:56:32 -06:00
tangxifan 179ae355d0 [Test] Do not run icarus verification for non const input test case. Icarus cannot handle the comb. loops 2020-10-13 12:02:26 -06:00
tangxifan 97c3bf7ea0 [Test] Add a test case for non-constant input multiplexers 2020-10-13 11:58:17 -06:00
tangxifan 570b494df7 [Test] Add test case for using GND signal as constant input for routing multiplexers 2020-10-13 11:38:54 -06:00
tangxifan dc68c52d0a [Test] Now use a light architecture to speed up the test case runtime 2020-10-12 12:53:34 -06:00
tangxifan 8941e38613 [Test] Enable verification in the new test case 2020-10-12 12:50:08 -06:00
tangxifan 9e1fd300dc [Test] Add test case for customized location of fabric netlists 2020-10-12 12:47:58 -06:00
tangxifan 82e7b159ce [Regression test] Add test case for fracturable LUT using AND gate to switch modes 2020-10-10 20:26:41 -06:00
tangxifan d4d02ab16a [Regression Test] Move fabric key tests to basic tests 2020-09-29 14:22:23 -06:00
tangxifan ff6570df9d [Regression Test] Bug fix for fabric key test cases using multiple regions and deploy tests to CI 2020-09-29 14:19:40 -06:00
tangxifan 02ea639959 [Regression Test] Add test for fabric key based on multiple region 2020-09-29 14:13:38 -06:00
tangxifan a0d1d68402 [Regression Test] Add regression tests for smart fast configuration chain using multiple regions 2020-09-29 13:53:41 -06:00
tangxifan 5be5835b71 [Regression Test] Add multiple region configuration chain test case 2020-09-29 13:48:39 -06:00