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OpenFPGA
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378 Commits

Author SHA1 Message Date
tangxifan 009e5244d3 minor fix on the port direction of configuration peripherals for memory decoders 2019-06-10 15:39:35 -06:00
tangxifan f43955037c remove input port requirements for SRAM circuit module 2019-06-10 15:29:44 -06:00
tangxifan e4f70771a2 updated SDC generator to embrace the RRGSB data structure 2019-06-10 14:47:27 -06:00
tangxifan 8a8f4153ce use const RRGSB to be more runtime and memory efficient, updating SDC generator to use RRGSB 2019-06-10 12:50:10 -06:00
tangxifan e31407f693 start cleaning up SDC generator with new RRGSB data structure 2019-06-10 10:57:26 -06:00
tangxifan 17bc7fc296 update Verilog generator to use GSB data structure. SDC generator and TCL generator to go 2019-06-08 20:11:22 -06:00
Xifan Tang 61e359efc5 Enable an option to disable/enable graphics in VPR compilation 2019-06-08 15:08:17 -06:00
tangxifan 8c5ec4572d revert string to sprintf 2019-06-07 20:20:41 -06:00
tangxifan 0f1ed19ad0 Revert to the use of sprintf instead std::string. Have no idea why string is not working 2019-06-07 18:54:57 -06:00
tangxifan 44ce0e8834 update gsb unique module detection and fix formal verification port direction 2019-06-07 17:18:38 -06:00
tangxifan 24d53390d8 clean up DeviceRRGSB internal data and member functions 2019-06-07 14:45:56 -06:00
tangxifan c9f810ceb6 update rr_gsb to build connection blocks 2019-06-07 11:01:55 -06:00
tangxifan 472aff5acb add new class port to simplify codes in outputting codes, upgrade RRSwitch to RRGSB 2019-06-06 23:45:21 -06:00
tangxifan ce9fc5696c rename rr_switch_block to rr_gsb, a generic block 2019-06-06 17:41:01 -06:00
tangxifan 8c1e7b799f fixed critical bugs in Connection Block Unique Module detection 2019-06-06 16:31:50 -06:00
tangxifan 873e4d989f fine-tuning Verilog format and node addition to rr_blocks 2019-06-06 12:48:41 -06:00
tangxifan c2de0eefb1 fix redundant comma in SB Verilog module 2019-06-06 09:15:05 -06:00
tangxifan b9e1b1afc4 fix a critical bug in num_reserved_sram_ports 2019-06-05 17:31:01 -06:00
tangxifan aaf8d23971 fix critical bugs in routing submodules 2019-06-05 16:43:18 -06:00
tangxifan 01e075377d fix typo in Verilog generation 2019-06-05 15:30:34 -06:00
tangxifan 21d0cb52bc Merge remote-tracking branch 'origin' into tileable_sb 2019-06-05 13:31:49 -06:00
tangxifan 24ca3104b0 fix minor bugs in Switch Block submodules 2019-06-05 13:30:55 -06:00
tangxifan 0f87ae9886 support switch block submodule Verilog generation by segments 2019-06-05 12:56:05 -06:00
AurelienUoU 84fabbd43b Fix sdc analysis bug related to virtual nodes + add the option in regression test 2019-06-05 12:10:28 -06:00
Baudouin Chauviere d24488092d Fix bug 2019-06-05 11:40:04 -06:00
tangxifan c2d8fa00ba add rr_block unique_side_module verilog generation 2019-06-04 17:47:40 -06:00
tangxifan 98b82c17be bug fixing for clear RRSwitchBlock 2019-06-04 14:02:49 -06:00
tangxifan 2c6780ab92 add side mirror detection for RRSwitchBlock 2019-06-04 13:01:22 -06:00
Baudouin Chauviere 1932d00309 Correction of the SDC to remove global clocks 2019-05-30 15:04:21 -06:00
tangxifan 5b15a746d3 add num_driver_nodes to Switch Block XML writter 2019-05-28 20:52:33 -06:00
tangxifan 5ed076dfb4 fixed a critical bug in rotating 2019-05-28 17:55:09 -06:00
tangxifan 9cc5518d5a keep adding segment information for SB XML outputter 2019-05-28 15:59:55 -06:00
tangxifan e7e18eb4c1 Add more information in SB XML outputter 2019-05-28 15:56:41 -06:00
tangxifan ca363da30c add options to specify output directory of SB XML 2019-05-28 15:19:10 -06:00
tangxifan 6b51b42ee7 Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb 2019-05-28 14:53:44 -06:00
tangxifan af91fca1e0 add rr_blocks XML writer to help debugging Switch Block Rotation 2019-05-28 14:52:44 -06:00
Baudouin Chauviere 3da216f297 correction Null issue for the flat model 2019-05-28 14:15:24 -06:00
tangxifan 6f30d3ad05 support rotation on segment groups inside RRChan and improve rotatable mirror searching 2019-05-28 11:25:16 -06:00
tangxifan 0f5666ea11 fixed the bug in mirror node direction 2019-05-27 21:58:21 -06:00
tangxifan eece161d58 keep debugging on Switch Block rotation 2019-05-27 21:10:30 -06:00
tangxifan 5720217cfd Add copy constructor for RRChan, RRSwitchBlock etc. 2019-05-27 15:44:34 -06:00
tangxifan 1bea9870fc developed new rotating methods for RRSwitchBlocks, debugging ongoing 2019-05-26 23:35:30 -06:00
tangxifan 4b852afeac skip rotating mirror detection which is too time-consuming 2019-05-25 23:41:46 -06:00
tangxifan 22e71f5847 Add rotate one side of switch block functionality 2019-05-25 22:48:07 -06:00
tangxifan 858a323228 Add more support for rotating Switch Blocks 2019-05-25 21:26:35 -06:00
tangxifan 2eab0b1c1c update unique_mirror search algorithm for Switch Blocks 2019-05-25 19:54:15 -06:00
tangxifan d3eae80e64 implemented an native way in finding rotable Switch blocks 2019-05-25 19:37:18 -06:00
tangxifan ae0248fbc6 debugging SwitchBlock rotating 2019-05-24 23:10:30 -06:00
tangxifan 9adc2945c8 add rotate functionality for RRSwitchBlock 2019-05-24 21:40:16 -06:00
tangxifan 02b48d036d clean warnings 2019-05-24 16:48:08 -06:00
tangxifan 2c46da6888 clean-up warnings Verilog routing generator 2019-05-24 16:29:17 -06:00
tangxifan 27b996337a fixed a critical bug in Compact Verilog generation for SB/CBs 2019-05-24 16:14:46 -06:00
tangxifan 1ade1f1d3f update SDC generator disabled_unused_mux by using RRSwitchBlock 2019-05-24 15:42:00 -06:00
tangxifan f27b88db8d Use RRChan in SDC generator to replace old data structures 2019-05-24 15:34:56 -06:00
tangxifan 27c234711e clean up warnings in SDC pb_type generator 2019-05-24 15:23:38 -06:00
tangxifan 924136e7a2 Clean warnings in SDC generator and use RRSwitchBlock to replace old data structure sb_info 2019-05-24 15:10:08 -06:00
tangxifan 994b90ae53 updated report_timing for using RRSwitchBlock 2019-05-24 14:25:51 -06:00
tangxifan eef1312325 updated bitstream to use new RRSwitchBlock as well as the report timing engine 2019-05-24 12:54:10 -06:00
tangxifan 8f4f590ff9 update Verilog compact_netlist outputter with RRSwitchBlock classes 2019-05-23 21:52:12 -06:00
tangxifan ea8c36ce6e upgrade Verilog SB generator using the RRSwitchBlock 2019-05-23 17:37:39 -06:00
tangxifan 4aab93b729 update class rr_switch_block and be ready for updating the downstream verilog generator 2019-05-22 22:04:31 -06:00
tangxifan efbc454cdd Add Class for RRSwtichBlock and plug-in to replace the old t_sb 2019-05-22 12:34:06 -06:00
tangxifan ec3b4c86c4 update file organization and be ready for SB/CB class 2019-05-21 12:15:38 -06:00
tangxifan 8186d6dd11 reorganize files and clean some warnings 2019-05-21 10:17:54 -06:00
tangxifan b185a17359 add routing_channel unique module generation 2019-05-20 22:33:17 -06:00
giacomin ceee28226e Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb 2019-05-20 16:47:07 -06:00
giacomin 8b520349e7 fixed a bug for rram based fpga when using explicit verilog port mapping 2019-05-20 16:44:47 -06:00
AurelienUoU 99beeb48cc Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb 2019-05-13 16:42:27 -06:00
AurelienUoU a3656dde45 Add missing Verilog source, Archictecture folder and Testbenches correction 2019-05-13 16:41:35 -06:00
Baudouin Chauviere b48a27acf0 Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb 2019-05-13 14:45:57 -06:00
Baudouin Chauviere 2019840d7c cleaned unused variables 2019-05-13 14:45:02 -06:00
tangxifan 3313eac23b add rr_chan obj 2019-05-10 22:50:08 -06:00
AurelienUoU 9c05a4fb0a Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb 2019-05-10 14:09:23 -06:00
AurelienUoU ff9b84d800 Bug fix in Icarus requirement 2019-05-10 14:07:32 -06:00
tangxifan be4643b8a6 updated Verilog generator to use compact CBs and SBs. SPICE generator to be updated 2019-05-10 10:21:06 -06:00
tangxifan 5c646f5de7 fix bugs in routing identification 2019-05-09 21:40:06 -06:00
tangxifan a9df922412 finish the identification on mirror switch and connection blocks 
Verilog generator to be updated
 2019-05-09 21:31:39 -06:00
tangxifan a3c3f2b892 developing compact routing hierarchy 2019-05-08 20:49:21 -06:00
tangxifan 4c6639218e Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb 2019-05-08 14:30:33 -06:00
tangxifan e305e60ee4 minor fix on the shell interface of VPR 2019-05-08 14:29:58 -06:00
Baudouin Chauviere 4f386de2ef gen_xxx functions create mem-leaks because the mem is dynamically allocated inside and not freed. TBD later everywhere 2019-05-06 17:25:29 -06:00
Baudouin Chauviere 3b62f8e024 Conversion from s to ns for the loop breaking delays 2019-05-06 16:12:30 -06:00
Baudouin Chauviere a5a1a376ab Modified code for cleaner delay naming convention 2019-05-06 12:52:49 -06:00
tangxifan 4e3487b691 Add latest abc and update ace dependence 2019-05-03 18:56:03 -06:00
Baudouin Chauviere 7860042276 added before after loop breaker constraining 2019-05-03 14:00:06 -06:00
Baudouin Chauviere 4e330ee463 Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb 2019-05-03 10:43:22 -06:00
Baudouin Chauviere 921b694400 Bug fix sdc breaking loop of edges outside current interconnect 2019-05-03 10:42:35 -06:00
AurelienUoU 42f20eda60 Add the user matching for internal register in formal verification script generation 2019-05-03 10:24:02 -06:00
tangxifan 974af5a2ae Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb 2019-04-30 14:30:38 -06:00
tangxifan 42daadee2f critical bug fixing 2019-04-30 14:30:17 -06:00
Baudouin Chauviere 1ab4688339 Create no segment constraint in loop_breaker if none is given by user 2019-04-30 12:30:07 -06:00
tangxifan c46c0fc97d bug fixing for SDC generator 2019-04-26 14:07:44 -06:00
tangxifan 46d44fa42a Update VPR7 X2P with new engine 2019-04-26 12:23:47 -06:00
tangxifan b06df18a89
Update rr_graph_area.c 2019-03-11 21:46:42 +08:00
AurelienUoU 213f94ddee Correct preconfiguration 2019-01-31 16:43:47 -07:00
tangxifan 5e36aa82c5 fixa bug in determining mux structure 2019-01-22 13:54:50 -07:00
tangxifan b8187bbca5 fix a bug for supporting default circuit_model of LUTs and FFs 2019-01-10 15:10:05 -07:00
AurelienUoU b80e435548 Correct manual testbench generation bug 2019-01-07 18:03:56 -07:00
AurelienUoU 21dc8a006f Change simulator script generation (waves) 2018-12-14 14:40:04 -07:00
tangxifan ee6b1d6cd6 adapt arch xml and act for demo 2018-12-13 22:46:40 -07:00
AurelienUoU cc5a01d476 Fix waveform generation + add benchmark and update go.sh 2018-12-11 22:21:39 -07:00
AurelienUoU f5ea3ff233 Add an autochecked configuration free testbench 2018-12-11 14:44:13 -07:00
tangxifan 72fbd8d6a8 update blif reader to identify clock signals 2018-12-10 13:28:44 -07:00
AurelienUoU a69c2e1882 Add security in checking to avoid simulation glitch error 2018-12-10 09:46:16 -07:00
AurelienUoU 7020d9b4b6 Edit waveform generator + fix clock mapping in autochecked testbench 2018-12-09 15:48:59 -07:00
AurelienUoU 5e94b7093d Add scan-chain and timed architecture + update simulation script script (add script for autochecked testbench) 2018-12-08 22:57:54 -07:00
Aur??Lien ALACCHI 10866d1852 Correct verilog syntax error in autocheck testbench 2018-12-08 17:40:23 -07:00
Aur??Lien ALACCHI d716b67e23 Correct syntax error in autocheck testbench 2018-12-08 17:29:56 -07:00
Aur??Lien ALACCHI 0580d8243f Add Autochek testbench option 2018-12-08 17:19:12 -07:00
Aur??Lien ALACCHI 4cc875a5a5 fix a bug in wired LUT 2018-12-06 18:00:17 -07:00
tangxifan b3c1018e28 fixed a bug in wired LUT 2018-12-06 16:50:30 -07:00
Aur??Lien ALACCHI eebdf7cb10 Add possibility to choose default value for initialization 2018-12-06 15:34:14 -07:00
Baudouin Chauviere b6bb419e1d add a ModelSim option 2018-12-06 14:13:37 -07:00
Aur??Lien ALACCHI 8281b7346b Edit auto-generated modelsim script 2018-12-05 16:15:29 -07:00
Aur??Lien ALACCHI 44b7f7f3d4 Correct sub_modules.v generation to include decoders.v when necessary 2018-12-05 13:52:25 -07:00
Aur??Lien ALACCHI dc4accedd9 Add forgottent files + add parameter transmission from verilog_api.c 2018-12-05 11:33:14 -07:00
Aur??Lien ALACCHI 9a8c7b391a Add process for modelsim script autogeneration 2018-12-05 09:20:47 -07:00
Aur??Lien ALACCHI 75d64db0f9 Add verilog header sub_module.v file generation 2018-12-04 18:42:47 -07:00
Aur??Lien ALACCHI 8ac566ecc0 Add timing and initialization for simulation 2018-12-04 17:32:09 -07:00
tangxifan 70751551b5 fix a bug in wired LUT support 2018-11-30 21:33:31 -07:00
tangxifan e223868df8 fix bugs for wired LUTs 2018-11-27 12:46:30 -07:00
Aur??Lien ALACCHI de2bc18bbb bugs fixed for shift register benchmark 2018-11-26 16:58:45 -07:00
tangxifan 861c449606 support wired LUT in FPGA-SPICE and FPGA-Verilog 2018-11-15 15:57:49 -07:00
Baudouin Chauviere f7d7a056da Modification of the fpga_spice_utils 2018-11-15 14:11:55 -07:00
Baudouin Chauviere c81d00bb51 Correction of the double free bug 2018-11-15 13:55:16 -07:00
tangxifan c67ba5f58a clean up codes 2018-09-27 14:26:08 -06:00
tangxifan 681cca99a4 fix a bug in tapbuf 2018-09-21 19:00:22 -06:00
tangxifan d683134b12 rename customized vpr7 to vpr7 XML to Production 2018-09-17 23:10:45 -06:00