tangxifan
|
3fdd5ae8b3
|
[Script] Use pin constraints in template script
|
2021-01-19 17:42:25 -07:00 |
|
tangxifan
|
e17a5cbbf2
|
[Test] Rename to pin constraint to comply with libpcf requirement
|
2021-01-19 15:52:51 -07:00 |
|
tangxifan
|
ab25e1af5f
|
[Test] Add example XML for net mapping between benchmark to FPGA
|
2021-01-19 09:29:21 -07:00 |
|
tangxifan
|
ea9d6bfe91
|
[Flow] Update the design constraint file to follow bug fix in parser
|
2021-01-17 10:41:01 -07:00 |
|
tangxifan
|
dd74f05a31
|
[Test] Add repack constraints to tests
|
2021-01-17 10:35:36 -07:00 |
|
tangxifan
|
12e0efd03e
|
[Script] Add an example openfpga script to use repack design constraints
|
2021-01-17 10:33:56 -07:00 |
|
tangxifan
|
d0e05b3575
|
[Lib] Now use pb_type in design constraints instead of physical tiles
|
2021-01-16 21:35:43 -07:00 |
|
tangxifan
|
8578c1ecac
|
[Flow] Rename the design contraint file syntax
|
2021-01-16 15:35:13 -07:00 |
|
tangxifan
|
9154cfdeec
|
[Flow] Add comments for the design constraint file
|
2021-01-16 15:34:01 -07:00 |
|
tangxifan
|
6ab0f71896
|
[Test] Add an example of repack pin constraints file
|
2021-01-16 14:38:39 -07:00 |
|
tangxifan
|
89f9d24d32
|
[Flow] Update simulation settings for multiple clock to allow unique clock port name
|
2021-01-15 10:35:43 -07:00 |
|
tangxifan
|
dbed04b53b
|
[Flow] Reduce the number of clock cycles to simulation in example sim setting XML for a light test run in CI
|
2021-01-14 15:42:21 -07:00 |
|
tangxifan
|
3b5394b45f
|
[Test] Now use dedicated simulation settings for the 4-clock architecture
|
2021-01-14 15:40:16 -07:00 |
|
tangxifan
|
923f3a3401
|
[Flow] Add an example simulation settings for a 4-clock FPGA fabric
|
2021-01-13 17:29:39 -07:00 |
|
tangxifan
|
9a906e787b
|
[Benchmark] Add post-yosys .v file for counter 4-bit with dual clock
|
2021-01-13 15:43:31 -07:00 |
|
tangxifan
|
314e458632
|
[Test] Update task configuration to use post-yosys .v file in verification
|
2021-01-13 15:42:45 -07:00 |
|
tangxifan
|
c5a2027f36
|
[Flow] Use implicit port mapping to avoid renaming problem between yosys and VPR
|
2021-01-13 15:41:48 -07:00 |
|
tangxifan
|
7af6d7f07d
|
[Benchmark] change the pin sequence of counter4bit_2clock to be easy for testbench generation
|
2021-01-13 15:38:44 -07:00 |
|
tangxifan
|
91f12071d5
|
[Test] Use counter4bit in the multi-clock test
|
2021-01-13 13:34:59 -07:00 |
|
tangxifan
|
ccf3e037ff
|
[Benchmark] Change multi-clock counter from 8-bit to 4-bit
|
2021-01-13 13:31:06 -07:00 |
|
tangxifan
|
250adb01cf
|
[Test] Update test case to use blif_vpr flow with detailed explaination on the choice
|
2021-01-13 13:18:31 -07:00 |
|
tangxifan
|
99e2a068fb
|
[Test] Add a test case for multi-clock
|
2021-01-12 18:06:25 -07:00 |
|
tangxifan
|
2f1aceda67
|
[Doc] Update documentation about architecture naming rules
|
2021-01-12 18:01:24 -07:00 |
|
tangxifan
|
9fa49c401c
|
[Arch] Add openfpga architecture which uses 4 global clocks
|
2021-01-12 18:00:22 -07:00 |
|
tangxifan
|
16b4e89326
|
[Doc] Update documentation for VPR architectures
|
2021-01-12 17:57:40 -07:00 |
|
tangxifan
|
7ccdff4543
|
[Arch] Add an architecture using 4 clocks
|
2021-01-12 17:55:57 -07:00 |
|
tangxifan
|
3790f2c26a
|
[Benchmark] Add 2-clock micro benchmark
|
2021-01-12 17:48:52 -07:00 |
|
tangxifan
|
a0b9f2b40d
|
Merge pull request #170 from lnis-uofu/dev
Extended Support on Defining Global Ports from Physical Tile Ports
|
2021-01-11 10:02:31 -07:00 |
|
tangxifan
|
e58e1e86c2
|
[Test] Update test case to use new shell script
|
2021-01-10 11:09:10 -07:00 |
|
tangxifan
|
18d2a8ce19
|
[Flow] Add new script for fixed device layout using global tile clock
|
2021-01-10 11:08:02 -07:00 |
|
tangxifan
|
aaf582acc5
|
[Arch] Bug fix
|
2021-01-10 11:05:57 -07:00 |
|
tangxifan
|
1c68e43acf
|
[Test] Add new test case for registerable I/O architecture
|
2021-01-10 11:00:21 -07:00 |
|
tangxifan
|
f21d22f691
|
[Doc] Update README for new architectures
|
2021-01-10 10:54:59 -07:00 |
|
tangxifan
|
dfb3e32147
|
[Arch] Add openfpga archiecture for registerable I/O
|
2021-01-10 10:54:41 -07:00 |
|
tangxifan
|
853e7b1a40
|
[Arch] Add vpr architecture where I/O can be either combinational or registered
|
2021-01-10 10:54:09 -07:00 |
|
tangxifan
|
43418cd76b
|
[Test] Deploy pipeplined and2 to test cases
|
2021-01-10 10:28:22 -07:00 |
|
tangxifan
|
6521aa2e7a
|
[Benchmark] Bug fix in pipelined and2 benchmark
|
2021-01-10 10:27:59 -07:00 |
|
tangxifan
|
4412bbd084
|
[Benchmark] Add a micro benchmark to test pipelined architecture
|
2021-01-10 10:21:30 -07:00 |
|
tangxifan
|
0b74575606
|
[Arch] Update arch using global reset tile port
|
2021-01-09 18:04:55 -07:00 |
|
tangxifan
|
7b24da267a
|
[Arch] Remove port size XML syntax
|
2021-01-09 16:30:46 -07:00 |
|
tangxifan
|
9f12b25a24
|
[Arch] Add port size to global port defined thru tile annotation
|
2021-01-09 16:23:28 -07:00 |
|
tangxifan
|
0f5f0a3527
|
[Arch] Add x,y coordinates to global port definition
|
2021-01-09 15:50:09 -07:00 |
|
tangxifan
|
a14a56772a
|
[Arch] Introduce new XML syntax for global port in tile annotation
|
2021-01-09 15:48:42 -07:00 |
Lalit Sharma
|
8a5741b1ae
|
Bumping yosys submodule with the latest changes done in yosys repo related to OpenFPGA flow
|
2021-01-08 07:08:24 -08:00 |
|
tangxifan
|
a813c9016b
|
[Arch] Patch the port name in openfpga arch to avoid conflicts with OpenFPGA's reserved words
|
2021-01-04 17:39:13 -07:00 |
|
tangxifan
|
06af30ef10
|
[Test] Add test case for the SCFF usage in configuration chain
|
2021-01-04 17:30:19 -07:00 |
|
tangxifan
|
709ee1b842
|
[HDL] Update dff netlist for SCFF used in configuration chain
|
2021-01-04 17:17:35 -07:00 |
|
tangxifan
|
c97a92d628
|
[Arch] Patch openfpga architecture for ccff circuit model port requirement
|
2021-01-04 17:15:50 -07:00 |
|
tangxifan
|
294ad97d38
|
[Arch] Add openfpga architecture example using the configure-enable scan-chain flip-flop
|
2021-01-04 14:56:49 -07:00 |
|
tangxifan
|
722a9bcf63
|
[HDL] Add scan-chain DFF cell with configuration enable signal
|
2021-01-04 14:31:26 -07:00 |
|
Lalit Sharma
|
2484721a45
|
Updating write_verilog_testbench by removing option explicit_port_mapping
|
2020-12-22 22:17:50 -08:00 |
|
Lalit Sharma
|
3c9e4919b4
|
Updating variable name in ys to call BLIF output file.
|
2020-12-18 03:18:46 -08:00 |
|
Lalit Sharma
|
1f994319fd
|
Adding this testcase to CI script. Also adding an option in ys script for synthesis to use openfpga compliant FF
|
2020-12-16 04:19:56 -08:00 |
|
Lalit Sharma
|
891e2f8aa3
|
Adding arch xml from SOFA repo. Also updating the script with its file location
|
2020-12-16 04:14:18 -08:00 |
|
Lalit Sharma
|
0ee3efb306
|
Adding a testcase to run yosys quicklogic flow
|
2020-12-10 02:41:43 -08:00 |
|
tangxifan
|
6b50bbf986
|
Merge pull request #134 from lnis-uofu/ganesh_dev
Support Delay Customization in OpenFPGA Task Configuration File
|
2020-12-08 15:32:48 -07:00 |
|
tangxifan
|
6001da3a40
|
[Arch] Bug fix in tileable I/O arch example
|
2020-12-04 17:56:54 -07:00 |
|
tangxifan
|
1d0bdcfeca
|
[Arch] Simplify the grid layout modeling
|
2020-12-04 17:38:44 -07:00 |
|
tangxifan
|
1c3f625e41
|
[Arch] Force empty tiles at corners for tileable I/O arch example
|
2020-12-04 17:11:06 -07:00 |
|
tangxifan
|
0cb8457e21
|
[Test] Add test case for tileable I/O
|
2020-12-04 16:02:47 -07:00 |
|
tangxifan
|
186eb0f0a4
|
[Arch] Add tileable I/O architecture example
|
2020-12-04 15:59:39 -07:00 |
ganeshgore
|
289d9d2169
|
[Bugfix] Honors yosys_tmpl parameter in flow script
|
2020-12-03 12:24:24 -07:00 |
|
tangxifan
|
412fb5bb31
|
[Arch] Bug fix due to valid default value parser
|
2020-12-02 17:51:50 -07:00 |
|
tangxifan
|
179b0ce304
|
[Test] Use formal verification method to reduce the runtime of iverilog simulation for global tile
|
2020-11-30 18:11:47 -07:00 |
|
tangxifan
|
c7604ab94f
|
[Arch] Bug fix due to prog_reset port name conflicting with reserved words of OpenFPGA
|
2020-11-30 18:02:00 -07:00 |
|
tangxifan
|
ff53d2c375
|
[HDL] Add new Scan-chain DFF cell
|
2020-11-30 17:54:10 -07:00 |
|
tangxifan
|
ad703ad85b
|
[HDL] Add new gpio cell with protection circuitry
|
2020-11-30 17:52:39 -07:00 |
|
tangxifan
|
27a480b5f8
|
[Test] arch name fix in the test case
|
2020-11-30 17:45:54 -07:00 |
|
tangxifan
|
7a0a3398d4
|
[Arch] Add new architecture to test global reset ports defined thru tile ports
|
2020-11-30 17:43:41 -07:00 |
|
tangxifan
|
a1d3b439d3
|
[Test] Add a new test case to define a global reset port from a global tile port
|
2020-11-30 17:19:12 -07:00 |
|
tangxifan
|
a60bd4d14a
|
[Arch] Bug fix in nature fracturable architecture
|
2020-11-25 22:48:26 -07:00 |
|
ganeshgore
|
7db030018c
|
[Bug] Fixed variable file location
|
2020-11-25 22:44:40 -07:00 |
|
tangxifan
|
b8559249dc
|
[Test] Bug fix in task configuration file
|
2020-11-25 22:23:27 -07:00 |
|
tangxifan
|
26e4db56ad
|
[Test] Add new test case for the native fracturable LUT4
|
2020-11-25 22:21:23 -07:00 |
|
tangxifan
|
17070c6405
|
[Doc] Update README in openfpga arch directory for native fracturable LUT design
|
2020-11-25 22:19:20 -07:00 |
|
tangxifan
|
f6a667de58
|
[Arch] Add openfpga architecture using native fracturable LUT
|
2020-11-25 22:18:03 -07:00 |
|
tangxifan
|
eda671592e
|
[Doc] Update README about new keyword about fracturable LUT
|
2020-11-25 22:12:56 -07:00 |
|
tangxifan
|
0f841aa6d1
|
[Arch] Add an example architecture using native fracturable LUT
|
2020-11-25 22:11:14 -07:00 |
|
ganeshgore
|
59bd7d0f18
|
[Flow] Changed substitute to safe_sustitute option
|
2020-11-25 22:09:36 -07:00 |
|
ganeshgore
|
fefba0db59
|
Merge remote-tracking branch 'lnis_origin/master' into ganesh_dev
|
2020-11-25 17:29:53 -07:00 |
|
ganeshgore
|
1d993296d8
|
[Flow] Example of using test variable in task conf
|
2020-11-25 17:25:12 -07:00 |
|
ganeshgore
|
1554f583b7
|
[Flow] Now support explicit variable file for task
|
2020-11-25 17:22:41 -07:00 |
|
tangxifan
|
fd80cacaa3
|
[Flow] Add example script for behaviorial verilog generation
|
2020-11-22 21:14:10 -07:00 |
|
tangxifan
|
617f7e3062
|
[Flow] disable signal initialization for behavioral verilog generation
|
2020-11-22 21:13:22 -07:00 |
|
tangxifan
|
5eb04e6fff
|
[HDL] Correct bugs in MUX2 standard cell where iverilog has problems in deposit initial signals
|
2020-11-22 20:53:32 -07:00 |
|
tangxifan
|
655da9f3d0
|
[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention
|
2020-11-22 16:37:19 -07:00 |
|
tangxifan
|
348872f8a4
|
[Flow] Adapt OpenFPGA shell script for the preprocessing flag option changes
|
2020-11-22 16:12:28 -07:00 |
|
tangxifan
|
845436fa71
|
[Test] Add sequential benchmark for global tile clock test case
|
2020-11-17 14:34:54 -07:00 |
|
tangxifan
|
91b0dbbaa2
|
[Script] Add example openfpga shell run script when using global tile clocks
|
2020-11-17 14:33:12 -07:00 |
|
tangxifan
|
485258a9ea
|
[Test] Add test case for global clock from tiles
|
2020-11-10 19:24:25 -07:00 |
|
tangxifan
|
f29916921a
|
[Arch] Add openfpga arch for using global clocks from tiles
|
2020-11-10 19:20:08 -07:00 |
|
tangxifan
|
a6531d9e8d
|
[Arch] Add k4 arch using global clock from tile port (with zero fc)
|
2020-11-10 19:17:34 -07:00 |
|
tangxifan
|
75ce4b5e25
|
[Arch] Fine tune example arch
|
2020-11-10 14:38:47 -07:00 |
|
tangxifan
|
d127304760
|
[Arch] Update sample arch using local clock from physical tile ports
|
2020-11-10 14:31:58 -07:00 |
|
tangxifan
|
4ca2a129c2
|
[Arch] Add an sample architecture where global clock port is defined from tile ports
|
2020-11-10 11:47:03 -07:00 |
|
tangxifan
|
70734abc35
|
[Arch] Remove QN from stdcell arch
|
2020-11-06 11:20:13 -07:00 |
|
tangxifan
|
1a79a55646
|
[HDL] Add DFF cell with reset but only 1 output
|
2020-11-06 11:19:19 -07:00 |
|
tangxifan
|
2aab8bf910
|
[Arch] Use single-output DFF for a standard cell FPGA
|
2020-11-06 10:26:39 -07:00 |
|
tangxifan
|
7d46b35296
|
[HDL] Add single-output DFF HDL
|
2020-11-06 10:18:37 -07:00 |
Laboratory for Nano Integrated Systems (LNIS)
|
55f7a2c187
|
Merge pull request #116 from LNIS-Projects/dev
Extended I/O Support for SoC I/O interface
|
2020-11-04 21:55:37 -07:00 |
|
tangxifan
|
bce8233019
|
[Arch] Bug fix in caravel arch
|
2020-11-04 20:58:58 -07:00 |
|
tangxifan
|
6b48ee7f0b
|
[Test] Add new test for caravel io support
|
2020-11-04 20:58:40 -07:00 |
|
tangxifan
|
c85edb4738
|
[Arch] Bug fix for embedded io arch
|
2020-11-04 20:52:47 -07:00 |
|
tangxifan
|
a6c7bb2c48
|
[Arch] Update OpenFPGA arch for new syntax on I/O
|
2020-11-04 20:24:02 -07:00 |
|
tangxifan
|
dd86f7f464
|
[Arch] Path architecture for caravel i/o interface
|
2020-11-04 17:16:21 -07:00 |
|
tangxifan
|
c074e88dcd
|
[HDL] Add embedded I/O HDL for Caravel SoC interface
|
2020-11-04 17:09:59 -07:00 |
|
tangxifan
|
aebf7453d0
|
[Arch] Add architecture files with compatible I/O capacity with caravel SoC
|
2020-11-04 16:57:00 -07:00 |
|
tangxifan
|
61376a2979
|
[Test] Add test cases for various tile organization
|
2020-11-04 16:32:52 -07:00 |
|
tangxifan
|
cf455df555
|
[Arch] Add architecture for bottom-right and top-left tile organization
|
2020-11-04 16:24:36 -07:00 |
|
tangxifan
|
46ca406f10
|
[Arch] Add a new vpr architecture with new tile organization
|
2020-11-04 16:20:01 -07:00 |
|
tangxifan
|
049ca14461
|
[Doc] Add new naming rules for vpr architecture files
|
2020-11-04 16:17:56 -07:00 |
|
Laboratory for Nano Integrated Systems (LNIS)
|
5d41cc6d23
|
Merge pull request #114 from LNIS-Projects/dev
Support I/O interfaces for Embedded FPGAs
|
2020-11-02 21:10:52 -07:00 |
|
tangxifan
|
c036c87d6d
|
[HDL] Bug fix in the GP output pad
|
2020-11-02 18:37:53 -07:00 |
|
tangxifan
|
3b49e6d090
|
[Arch] Patch embedded IO architecture by forcing only 1 pad per block
|
2020-11-02 15:39:31 -07:00 |
|
tangxifan
|
c512644a09
|
[Arch] Patch embedded I/O example architecture
|
2020-11-02 15:16:19 -07:00 |
|
tangxifan
|
7e9e0ec9d4
|
[HDL] Bug fix in I/O HDL code
|
2020-11-02 15:15:45 -07:00 |
|
tangxifan
|
2f237a6240
|
[HDL] Add HDL codes for embedded I/Os
|
2020-11-02 14:01:27 -07:00 |
|
tangxifan
|
55b77ac6cb
|
[Arch] Bug fixed in embedded FPGA architecture
|
2020-11-02 13:57:15 -07:00 |
|
tangxifan
|
a7e7fa2005
|
[Arch] Update arch with true embedded I/O definition
|
2020-11-02 13:29:40 -07:00 |
|
tangxifan
|
65ca53ac98
|
[Test] Update test case with the new arch name
|
2020-11-02 13:16:42 -07:00 |
|
tangxifan
|
8c8190047f
|
[Arch] Rename architecture files for embedded I/Os
|
2020-11-02 13:15:19 -07:00 |
|
tangxifan
|
bc00dee858
|
[Test] Add test case for embedded I/O
|
2020-11-02 12:28:25 -07:00 |
|
tangxifan
|
f86f43d287
|
[Arch] Add openfpga architecture file for constrained pin equivalence
|
2020-11-02 12:27:40 -07:00 |
|
tangxifan
|
795b30f76b
|
[Arch] Add VPR architecture with partial pin equivalence
|
2020-11-02 11:54:25 -07:00 |
|
tangxifan
|
032cbfb8b2
|
Merge pull request #113 from LNIS-Projects/dev
Multi-region support on Frame-based Configuration Protocol
|
2020-10-31 10:37:38 -06:00 |
|
tangxifan
|
4c14428400
|
[Test] Add test case for fast configuration support on multi-region frame-based configuration protocol
|
2020-10-30 10:50:00 -06:00 |
|
tangxifan
|
ca7d43275d
|
[Test] Add test case for multi_region configuration frame
|
2020-10-30 10:48:29 -06:00 |
|
tangxifan
|
29da368742
|
[Arch] Add architecture example for multi-region frame-based architecture using both set/reset for configurable memories
|
2020-10-30 10:46:47 -06:00 |
|
tangxifan
|
b701bd2640
|
[Arch] Add multi-region architecture example for frame-based protocol
|
2020-10-30 10:45:14 -06:00 |
|
Laboratory for Nano Integrated Systems (LNIS)
|
cd0d3dd798
|
Merge pull request #112 from LNIS-Projects/dev
Multi-region Memory Bank Configuration Protocol Support
|
2020-10-29 18:39:44 -06:00 |
|
tangxifan
|
1d930d1b5d
|
[Architecture] Add missing arch files and bug fix
|
2020-10-29 18:08:26 -06:00 |
|
tangxifan
|
153b265a6d
|
[Architecture] Add openfpga architecture using multiple memory banks whose memory cell has both reset and set
|
2020-10-29 16:32:05 -06:00 |
|
tangxifan
|
241ebf054a
|
[Test] Add a test case for validating fast configuration techniques on multi-region memory banks
|
2020-10-29 16:29:46 -06:00 |
|
tangxifan
|
ff386001c4
|
[Test] Add openfpga task for multi-region memory banks
|
2020-10-29 13:56:32 -06:00 |
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tangxifan
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7534474423
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[Arch] Add architecture for multiple-region memory banks
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2020-10-29 13:54:51 -06:00 |
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Laboratory for Nano Integrated Systems (LNIS)
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d984547258
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Merge pull request #108 from LNIS-Projects/dev
Add test cases for constant inputs of routing multiplexers
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2020-10-14 22:33:14 -06:00 |
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tangxifan
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179ae355d0
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[Test] Do not run icarus verification for non const input test case. Icarus cannot handle the comb. loops
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2020-10-13 12:02:26 -06:00 |
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tangxifan
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97c3bf7ea0
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[Test] Add a test case for non-constant input multiplexers
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2020-10-13 11:58:17 -06:00 |
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tangxifan
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c5bcd93408
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[Architecture] Add the example architecture where std cell-based multiplexers do not have a constant input
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2020-10-13 11:57:21 -06:00 |
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tangxifan
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99b1e68d92
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[Architecture] Add architecture using GND as constant inputs for multiplexers
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2020-10-13 11:39:27 -06:00 |
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tangxifan
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570b494df7
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[Test] Add test case for using GND signal as constant input for routing multiplexers
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2020-10-13 11:38:54 -06:00 |
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Laboratory for Nano Integrated Systems (LNIS)
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16128f0905
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Merge pull request #107 from LNIS-Projects/dev
Enable Customized Fabric Netlist Location in Verilog Testbench Generation
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2020-10-12 13:47:40 -06:00 |
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tangxifan
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dc68c52d0a
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[Test] Now use a light architecture to speed up the test case runtime
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2020-10-12 12:53:34 -06:00 |
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tangxifan
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e59377a3ec
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[Flow] bug fix in the sample script for fabric netlist customization
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2020-10-12 12:52:01 -06:00 |
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tangxifan
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8941e38613
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[Test] Enable verification in the new test case
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2020-10-12 12:50:08 -06:00 |
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tangxifan
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9e1fd300dc
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[Test] Add test case for customized location of fabric netlists
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2020-10-12 12:47:58 -06:00 |
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tangxifan
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e510e79c12
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[Flow] Add openfpga shell example script to use fabric netlist option
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2020-10-12 12:42:43 -06:00 |
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Laboratory for Nano Integrated Systems (LNIS)
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8493345b52
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Merge pull request #105 from LNIS-Projects/dev
Misc Update: Analysis SDC renaming and Addition of test case for fracturable LUT switch by AND gates
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2020-10-10 21:43:02 -06:00 |
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tangxifan
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82e7b159ce
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[Regression test] Add test case for fracturable LUT using AND gate to switch modes
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2020-10-10 20:26:41 -06:00 |
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tangxifan
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d0014878d5
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[Architecture] Add an openfpga architecture using and gate to control fracturable LUT modes
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2020-10-10 20:24:57 -06:00 |
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tangxifan
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521accdc88
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Merge pull request #104 from lukefahr/disp_fix
FLOW: fixed display flag
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2020-10-07 09:54:06 -06:00 |
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tangxifan
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7b12c28e4f
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Merge pull request #102 from lukefahr/blif_bug
Fixed blif formatting bug
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2020-10-06 20:05:02 -06:00 |
Andrew Lukefahr
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33bbe0ec48
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FLOW: fixed display flag
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2020-10-06 20:52:28 -04:00 |
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Andrew Lukefahr
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d68427e47b
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Fixed blif formatting bug
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2020-10-06 20:46:50 -04:00 |
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Andrew Lukefahr
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2d92a1f1af
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Edits to enable basic run_fpga_flow.py
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2020-10-02 10:18:10 -04:00 |
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tangxifan
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d4d02ab16a
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[Regression Test] Move fabric key tests to basic tests
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2020-09-29 14:22:23 -06:00 |
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tangxifan
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ff6570df9d
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[Regression Test] Bug fix for fabric key test cases using multiple regions and deploy tests to CI
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2020-09-29 14:19:40 -06:00 |
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tangxifan
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4f00d310d3
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[Architecture] Add example fabric key using multiple regions
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2020-09-29 14:14:50 -06:00 |
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tangxifan
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02ea639959
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[Regression Test] Add test for fabric key based on multiple region
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2020-09-29 14:13:38 -06:00 |
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tangxifan
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a0d1d68402
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[Regression Test] Add regression tests for smart fast configuration chain using multiple regions
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2020-09-29 13:53:41 -06:00 |
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tangxifan
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d5c7411399
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[Architecture] Add more architecture to test fast configuration support on the multi-region configuration chain
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2020-09-29 13:50:31 -06:00 |
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tangxifan
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5be5835b71
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[Regression Test] Add multiple region configuration chain test case
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2020-09-29 13:48:39 -06:00 |
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tangxifan
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23449dc5c3
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[Architecture] Add multiple region configuration chain architecture
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2020-09-29 13:46:40 -06:00 |
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tangxifan
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e09e5fa6c6
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[Architecture] Update fabric key for region syntax
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2020-09-27 20:40:37 -06:00 |
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tangxifan
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ffd926d686
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[Architecture] Update external bitstream
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2020-09-25 21:30:59 -06:00 |
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tangxifan
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dcbd6a0614
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[Architecture] Add lib name to TGATE to test compatibility
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2020-09-25 21:08:12 -06:00 |
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tangxifan
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019208ec0f
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[Architecture] Reorganize the cell netlists and update architecture files accordingly
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2020-09-25 11:55:28 -06:00 |
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tangxifan
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20d6b2bf84
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[Architecture] Remove out-of-date Verilog testbench
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2020-09-24 21:14:13 -06:00 |
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tangxifan
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00bf775971
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[Architecture] Bug fix for adder renaming
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2020-09-24 20:54:18 -06:00 |
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tangxifan
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0a53a719bd
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[Architecture] Bug fix due to adder renaming
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2020-09-24 20:42:24 -06:00 |
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tangxifan
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e4bfa2ef51
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[Architecture] Update external bitstream file
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2020-09-24 20:16:50 -06:00 |
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tangxifan
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bd0f0144a0
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[Architecture] Rename AIB architecture for the new cell naming
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2020-09-24 20:14:16 -06:00 |
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tangxifan
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8edfc79f53
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[Architecture] Rename AIB cell
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2020-09-24 20:11:21 -06:00 |
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tangxifan
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4ada793c84
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[Architecture] Adapt openfpga architecture to follow the renamed adder cell
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2020-09-24 20:09:29 -06:00 |
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tangxifan
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53187044e6
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[Architecture] Rename adder cell
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2020-09-24 20:07:57 -06:00 |
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tangxifan
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4a0a448171
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[Architecture] Rename openfpga architecture for the I/O cell
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2020-09-24 19:56:01 -06:00 |
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tangxifan
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e0f9547f5b
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[Architecture] Rework the i/o cell Verilog HDL
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2020-09-24 19:53:54 -06:00 |
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tangxifan
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eb5fd1f44e
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[Architecture] Bug fix for architectures using scan-chain DFF cell
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2020-09-24 18:37:25 -06:00 |
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tangxifan
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60a14ccbd2
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[Architecture] Bug fix in architectures that use BRAM
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2020-09-24 18:20:55 -06:00 |
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tangxifan
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d51efd397f
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[Architecture] Bug fix for architectures using DFF cells
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2020-09-24 18:02:42 -06:00 |
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tangxifan
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3ade6d6ff5
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[Architecture] Bug fix for dff that are used in data path
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2020-09-24 17:53:30 -06:00 |
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tangxifan
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3e7c88eac8
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[Architecture] Bug fix in Verilog netlist for scan-chain DFF
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2020-09-24 17:41:03 -06:00 |
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tangxifan
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7494556316
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[Architecture] Bug fix for scan-chain FF cell
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2020-09-24 17:38:16 -06:00 |
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tangxifan
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54b3f244d3
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[Architecture] Remove obsolete Verilog netlists
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2020-09-24 17:35:02 -06:00 |
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tangxifan
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49d6863641
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[Architecture] Bug fix for scan-chain FF cell renaming
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2020-09-24 17:33:14 -06:00 |
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tangxifan
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0a5369f919
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[Architecture] Adapt all the architecture files to use standard DFF cell
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2020-09-24 17:26:48 -06:00 |
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tangxifan
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19dd3778d9
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[Architecture] Add test case for memory bank to use both reset and set
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2020-09-24 17:04:24 -06:00 |
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tangxifan
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335f5b78c1
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[Regression Test] Add test case to use both set and reset for configuration frame
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2020-09-24 17:02:28 -06:00 |
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tangxifan
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2d81ff9012
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[Regression test] Add configuration chain test case where both set and reset are used
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2020-09-24 16:59:52 -06:00 |
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tangxifan
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fc154b8560
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[Architecture] Bug fix due to switching CCFF cell
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2020-09-24 16:45:56 -06:00 |
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tangxifan
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79875d5a91
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[Architecture] Bug fix in the configuration chain arch using both reset and set
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2020-09-24 15:27:26 -06:00 |
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tangxifan
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9cb67e6097
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[Architecture] Now all the configuration chain architecture use the DFFR cell by default
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2020-09-24 15:19:37 -06:00 |
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tangxifan
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81965e75f6
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[Architecture] Bug fix in DFF Verilog HDL
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2020-09-24 14:53:21 -06:00 |
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tangxifan
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3b42fe94d6
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[Architecture] Update external bitstream file
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2020-09-24 14:41:44 -06:00 |
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tangxifan
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7fbccdd102
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[Regression Tests] Add test cases for configuration chain using different DFF cells
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2020-09-24 14:34:12 -06:00 |
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tangxifan
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178afb3c7f
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[Architecture] Add configuration chain architectures using different DFF cells
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2020-09-24 14:23:27 -06:00 |
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tangxifan
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98d88dc686
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[Architecture] Bug fix for vanilla memory organization
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2020-09-24 14:13:48 -06:00 |
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tangxifan
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efad0402c2
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[Regression Test] Bug fix for CI errors
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2020-09-24 13:55:41 -06:00 |
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tangxifan
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e7906899dd
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[Regression test] Bug fix for fast configuration frame. Now should use a latch with reset
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2020-09-24 13:53:12 -06:00 |
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tangxifan
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e832d806c7
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[Architecture] Add DFF Verilog netlist using standard naming convention
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2020-09-24 13:50:59 -06:00 |