Eddie Hung
|
593e4a30bb
|
MUXF78 -> $__MUXF78 to indicate internal
|
2019-06-26 20:09:28 -07:00 |
Eddie Hung
|
dbb8c8caaa
|
Merge remote-tracking branch 'origin/xaig' into xc7mux
|
2019-06-26 20:07:31 -07:00 |
Eddie Hung
|
4de25a1949
|
Add WE to ECP5 dist RAM's abc_scc_break too
|
2019-06-26 20:02:19 -07:00 |
Eddie Hung
|
a7a88109f5
|
Update comment on boxes
|
2019-06-26 20:00:15 -07:00 |
Eddie Hung
|
b7bef15b16
|
Add "WE" to dist RAM's abc_scc_break
|
2019-06-26 19:58:09 -07:00 |
Eddie Hung
|
b9ff0503f3
|
synth_xilinx's muxcover call to be very conservative -- -nodecode
|
2019-06-26 17:57:10 -07:00 |
Eddie Hung
|
f0a1726a1a
|
Accidentally removed "simplemap $mux"
|
2019-06-26 17:48:49 -07:00 |
Eddie Hung
|
2b104ed6c8
|
Replace with <internal options>
|
2019-06-26 17:42:50 -07:00 |
Eddie Hung
|
cae69a3edd
|
Rework help_mode for synth_xilinx -widemux
|
2019-06-26 17:41:21 -07:00 |
Eddie Hung
|
5f807a7a5b
|
Return to upstream synth_xilinx with opt -full and wreduce
|
2019-06-26 16:25:48 -07:00 |
Eddie Hung
|
812469aaa3
|
Merge remote-tracking branch 'origin/eddie/fix1132' into xc7mux
|
2019-06-26 14:48:35 -07:00 |
Eddie Hung
|
c762be5930
|
Instead of blocking wreduce on $mux, use -keepdc instead #1132
|
2019-06-26 11:48:35 -07:00 |
Eddie Hung
|
8d8261c71f
|
Do not call opt with -full before muxcover
|
2019-06-26 11:38:28 -07:00 |
Eddie Hung
|
80de03a7a6
|
Merge remote-tracking branch 'origin/xaig' into xc7mux
|
2019-06-26 11:24:39 -07:00 |
Eddie Hung
|
4d0014d1b1
|
Cleanup abc_box_id
|
2019-06-26 11:23:57 -07:00 |
Eddie Hung
|
612083a807
|
Merge remote-tracking branch 'origin/xaig' into xc7mux
|
2019-06-26 10:33:54 -07:00 |
Eddie Hung
|
5e1b8d458b
|
Remove unused var
|
2019-06-26 10:33:07 -07:00 |
Eddie Hung
|
988e6163ab
|
Add _nowide variants of LUT libraries in -nowidelut flows
|
2019-06-26 10:23:29 -07:00 |
Eddie Hung
|
741ebba70a
|
Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig
|
2019-06-26 10:10:16 -07:00 |
Eddie Hung
|
799b18263f
|
Merge branch 'koriakin/xc7nocarrymux' into xaig
|
2019-06-26 10:04:01 -07:00 |
Miodrag Milanovic
|
ea0b6258ab
|
Simulation model verilog fix
|
2019-06-26 18:34:34 +02:00 |
Eddie Hung
|
4ce329aefd
|
synth_ecp5 rename -nomux to -nowidelut, but preserve former
|
2019-06-26 09:33:48 -07:00 |
Eddie Hung
|
7389b043c0
|
Merge branch 'xc7nocarrymux' of https://github.com/koriakin/yosys into koriakin/xc7nocarrymux
|
2019-06-26 09:33:38 -07:00 |
Eddie Hung
|
177c26ca35
|
Rename -minmuxf to -widemux
|
2019-06-26 09:16:45 -07:00 |
Eddie Hung
|
184cfacfb5
|
Merge remote-tracking branch 'origin/xaig' into xc7mux
|
2019-06-26 09:15:28 -07:00 |
David Shah
|
0dd850e655
|
abc9: Add wire delays to synth_ice40
Signed-off-by: David Shah <dave@ds0.me>
|
2019-06-26 11:39:44 +01:00 |
whitequark
|
3d4102cfa4
|
Add more ECP5 Diamond flip-flops.
This includes all I/O registers, and a few more regular FFs where it
was convenient.
|
2019-06-26 01:57:29 +00:00 |
Eddie Hung
|
480a04cb3c
|
Realistic delays for RAM32X1D too
|
2019-06-25 09:34:28 -07:00 |
Eddie Hung
|
6095357390
|
Add RAM32X1D box info
|
2019-06-25 09:34:19 -07:00 |
Eddie Hung
|
6f36ec8ecf
|
Merge remote-tracking branch 'origin/master' into xaig
|
2019-06-25 09:33:11 -07:00 |
Eddie Hung
|
4238feed81
|
This optimisation doesn't seem to work...
|
2019-06-25 09:21:46 -07:00 |
Eddie Hung
|
158325956e
|
Realistic delays for RAM32X1D too
|
2019-06-24 23:05:28 -07:00 |
Eddie Hung
|
3825068a75
|
Merge remote-tracking branch 'origin/xaig' into xc7mux
|
2019-06-24 23:04:25 -07:00 |
Eddie Hung
|
2f770b7400
|
Use LUT delays for dist RAM delays
|
2019-06-24 23:02:53 -07:00 |
Eddie Hung
|
e1ba25d79f
|
Add RAM32X1D box info
|
2019-06-24 22:54:35 -07:00 |
Eddie Hung
|
1564eb8b54
|
Merge remote-tracking branch 'origin/xaig' into xc7mux
|
2019-06-24 22:48:49 -07:00 |
Eddie Hung
|
4fadb471a3
|
Re-enable dist RAM boxes for ECP5
|
2019-06-24 22:12:50 -07:00 |
Eddie Hung
|
a4a7e63d84
|
Revert "Re-enable dist RAM boxes for ECP5"
This reverts commit ca0225fcfa .
|
2019-06-24 22:10:28 -07:00 |
Eddie Hung
|
ca0225fcfa
|
Re-enable dist RAM boxes for ECP5
|
2019-06-24 21:55:54 -07:00 |
Eddie Hung
|
152e682bd5
|
Add Xilinx dist RAM as comb boxes
|
2019-06-24 21:54:01 -07:00 |
Eddie Hung
|
f1675b88f6
|
Merge remote-tracking branch 'origin/eddie/ram32x1d' into xc7mux
|
2019-06-24 16:39:18 -07:00 |
Eddie Hung
|
efd04880db
|
Add RAM32X1D support
|
2019-06-24 16:16:50 -07:00 |
Eddie Hung
|
c3df895bf4
|
Reduce MuxFx resources in mux techmapping
|
2019-06-24 15:16:44 -07:00 |
Eddie Hung
|
db6a0b72b2
|
Reduce number of decomposed muxes during techmap
|
2019-06-24 14:28:56 -07:00 |
Eddie Hung
|
2e7992efff
|
Revert "Fix techmapping muxes some more"
This reverts commit 0aae3b4f43 .
|
2019-06-24 14:15:31 -07:00 |
Eddie Hung
|
7fbfcf20d1
|
Move comment
|
2019-06-24 14:15:00 -07:00 |
Eddie Hung
|
0aae3b4f43
|
Fix techmapping muxes some more
|
2019-06-24 12:50:48 -07:00 |
Eddie Hung
|
2b4501503d
|
Fix mux techmapping
|
2019-06-24 12:18:17 -07:00 |
Eddie Hung
|
aa1eeda567
|
Modify costs for muxcover
|
2019-06-24 11:51:55 -07:00 |
Eddie Hung
|
36e6da5396
|
Change synth_xilinx's -nomux to -minmuxf <int>
|
2019-06-24 10:04:01 -07:00 |
Eddie Hung
|
d54dceb547
|
Merge remote-tracking branch 'origin/xaig' into xc7mux
|
2019-06-22 19:44:17 -07:00 |
Eddie Hung
|
6027549464
|
Add comments to ecp5 box
|
2019-06-22 14:33:47 -07:00 |
Eddie Hung
|
792d0670c3
|
Add comment to xc7 box
|
2019-06-22 14:28:24 -07:00 |
Eddie Hung
|
63182ed57d
|
Fix and cleanup ice40 boxes for carry in/out
|
2019-06-22 14:27:41 -07:00 |
Eddie Hung
|
7903ebe3e0
|
Carry in/out box ordering now move to end, not swap with end
|
2019-06-22 14:18:42 -07:00 |
Eddie Hung
|
65c022c257
|
Remove DFF and RAMD box info for now
|
2019-06-21 20:41:14 -07:00 |
Eddie Hung
|
bbf3ad90f5
|
Remove $_MUX4_ techmap rule
|
2019-06-21 18:12:33 -07:00 |
Eddie Hung
|
39e0e006d5
|
Fix wreduce call (!!!), tweak muxcover costs
|
2019-06-21 18:12:07 -07:00 |
Eddie Hung
|
6c2cb51996
|
Merge remote-tracking branch 'origin/xaig' into xc7mux
|
2019-06-21 17:44:21 -07:00 |
Eddie Hung
|
1abe93e48d
|
Merge remote-tracking branch 'origin/master' into xaig
|
2019-06-21 17:43:29 -07:00 |
Eddie Hung
|
faa2d6fc1c
|
Constrain wreduce only if wide mux
|
2019-06-21 17:12:34 -07:00 |
Eddie Hung
|
aeee9dcad7
|
Simplify and comment out mux_map.v
|
2019-06-21 17:06:30 -07:00 |
Eddie Hung
|
ed00823b41
|
synth_xilinx to now wreduce except $mux, remove extra peepopt
|
2019-06-21 16:56:56 -07:00 |
Eddie Hung
|
29aee0989f
|
mux_map to no longer copy last value into 1'bx
|
2019-06-21 16:55:59 -07:00 |
Eddie Hung
|
8bce3fb329
|
Fix spacing
|
2019-06-21 16:55:34 -07:00 |
Eddie Hung
|
694d40719f
|
Fix spacing again, A_forward -> A_backward
|
2019-06-21 16:47:07 -07:00 |
Eddie Hung
|
11886c874c
|
Restore wreduce to synth_xilinx, after muxcover
|
2019-06-21 16:18:29 -07:00 |
Eddie Hung
|
44fc616fc7
|
Revert B_SIGNED optimisation, since only works for Y_WIDTH==1
|
2019-06-21 16:18:14 -07:00 |
Eddie Hung
|
4d6fac019a
|
Fix spacing
|
2019-06-21 16:06:13 -07:00 |
Eddie Hung
|
aa0b107afb
|
synth_xilinx to use _ABC macro, and perform muxpack again
|
2019-06-21 15:48:20 -07:00 |
Eddie Hung
|
9abde12110
|
Add $__XILINX_MUXF78 to preserve entire box
|
2019-06-21 15:47:42 -07:00 |
Eddie Hung
|
7acbea6b28
|
Fix alignment
|
2019-06-21 14:38:30 -07:00 |
Eddie Hung
|
f433a52374
|
Add FIXME about need for -mux4
|
2019-06-21 11:15:23 -07:00 |
Eddie Hung
|
c6b4653ebe
|
Since muxcover uses MUX4s, blast them back to gates here
|
2019-06-21 11:13:01 -07:00 |
Eddie Hung
|
dd22edcd28
|
Expand synth -coarse without wreduce, move muxcover
|
2019-06-21 11:12:32 -07:00 |
David Shah
|
a0d3d2bb41
|
ecp5: Improve mapping of $alu when BI is used
Signed-off-by: David Shah <dave@ds0.me>
|
2019-06-21 09:45:11 +01:00 |
Eddie Hung
|
e612dade12
|
Merge remote-tracking branch 'origin/master' into xaig
|
2019-06-20 19:00:36 -07:00 |
Eddie Hung
|
f11c9a419b
|
Call opt_expr -mux_undef to get rid of 1'bx in muxes prior to abc
|
2019-06-20 17:38:16 -07:00 |
Eddie Hung
|
d1dadfcec8
|
Call opt_expr -mux_undef to get rid of 1'bx in muxes prior to abc
|
2019-06-20 16:45:09 -07:00 |
Eddie Hung
|
9faab38e8d
|
mux_map to drop sign bit, and eliminate 'bx-es
|
2019-06-20 16:45:04 -07:00 |
Eddie Hung
|
f374e0ab7e
|
Merge remote-tracking branch 'origin/master' into xc7mux
|
2019-06-20 10:18:01 -07:00 |
acw1251
|
ce29ede801
|
Fixed small typo in ice40_unlut help summary
|
2019-06-19 16:39:46 -04:00 |
acw1251
|
0d888ee7ed
|
Fixed the help summary line for a few commands
|
2019-06-19 15:27:04 -04:00 |
Eddie Hung
|
4ca847a217
|
Merge remote-tracking branch 'origin/xaig' into xc7mux
|
2019-06-18 11:49:54 -07:00 |
Eddie Hung
|
8e0a47fb92
|
Really permute Xilinx LUT mappings as default LUT6.I5:A6
|
2019-06-18 11:48:48 -07:00 |
Eddie Hung
|
8f5e6d73ff
|
Revert "Fix (do not) permute LUT inputs, but permute mux selects"
This reverts commit da3d2eedd2 .
|
2019-06-18 11:35:21 -07:00 |
Eddie Hung
|
3d283e69f8
|
Merge remote-tracking branch 'origin/xaig' into xc7mux
|
2019-06-18 09:51:28 -07:00 |
Eddie Hung
|
b304744d15
|
Clean up
|
2019-06-18 09:50:37 -07:00 |
Eddie Hung
|
da3d2eedd2
|
Fix (do not) permute LUT inputs, but permute mux selects
|
2019-06-18 09:49:57 -07:00 |
Eddie Hung
|
2b0e28b261
|
Merge remote-tracking branch 'origin/xaig' into xc7mux
|
2019-06-17 22:29:34 -07:00 |
Eddie Hung
|
608a95eb01
|
Fix copy-pasta issue
|
2019-06-17 22:29:22 -07:00 |
Eddie Hung
|
59b4e69d16
|
Merge remote-tracking branch 'origin/xaig' into xc7mux
|
2019-06-17 22:25:14 -07:00 |
Eddie Hung
|
2a35c4ef94
|
Permute INIT for +/xilinx/lut_map.v
|
2019-06-17 22:24:35 -07:00 |
Eddie Hung
|
75f8b4cf10
|
Simplify comment
|
2019-06-17 19:14:41 -07:00 |
Eddie Hung
|
9d56c0d525
|
Merge remote-tracking branch 'origin/xaig' into xc7mux
|
2019-06-17 18:25:35 -07:00 |
Eddie Hung
|
840562943f
|
Update LUT7/8 delays to take account for [ABC]OUTMUX delay
|
2019-06-17 17:06:01 -07:00 |
Eddie Hung
|
c15ee827f4
|
Try -W 300
|
2019-06-17 10:29:06 -07:00 |
Eddie Hung
|
1ec450d6bf
|
Try -W 300
|
2019-06-16 12:08:03 -07:00 |
Eddie Hung
|
842c110357
|
Merge remote-tracking branch 'origin/xaig' into xc7mux
|
2019-06-15 05:48:47 -07:00 |
Eddie Hung
|
bf312043d4
|
Fix upper XC7 LUT[78] delays to use I[01] -> O delay not S -> O
|
2019-06-15 05:45:16 -07:00 |
Eddie Hung
|
b63b2a0bd4
|
Revert "Remove wide mux inference"
This reverts commit 738fdfe8f5 .
|
2019-06-14 12:50:24 -07:00 |
Eddie Hung
|
8fa74287a7
|
As per @daveshah1 remove async DFF timing from xilinx
|
2019-06-14 12:43:20 -07:00 |
Eddie Hung
|
97d2656375
|
Resolve comments from @daveshah1
|
2019-06-14 12:00:02 -07:00 |
Eddie Hung
|
2e34859a6b
|
Add XC7_WIRE_DELAY macro to synth_xilinx.cc
|
2019-06-14 11:38:22 -07:00 |
Eddie Hung
|
ba4b4a0088
|
Update delays based on SymbiFlow/prjxray-db
|
2019-06-14 11:33:10 -07:00 |
Eddie Hung
|
d47ff7ba87
|
Rename +/xilinx/abc.{box,lut} -> abc_xc7.{box,lut}
|
2019-06-14 10:51:11 -07:00 |
Eddie Hung
|
94314ae2d5
|
Comment out dist RAM boxing on ECP5 for now
|
2019-06-14 10:42:30 -07:00 |
Eddie Hung
|
ee428f73ab
|
Remove WIP ABC9 flop support
|
2019-06-14 10:37:52 -07:00 |
Eddie Hung
|
627a62a797
|
Make doc consistent
|
2019-06-14 10:32:46 -07:00 |
David Shah
|
9566573054
|
ecp5: Add abc9 option
Signed-off-by: David Shah <dave@ds0.me>
|
2019-06-14 17:15:02 +01:00 |
Eddie Hung
|
75d89e56cf
|
Fix name clash
|
2019-06-13 14:27:07 -07:00 |
Eddie Hung
|
2052806d33
|
Fix LP SB_LUT4 timing
|
2019-06-13 08:24:33 -07:00 |
Eddie Hung
|
009255d11d
|
Move neg-pol to pos-pol mapping from ff_map to cells_map.v
|
2019-06-12 16:07:24 -07:00 |
Eddie Hung
|
c7f5091c2f
|
Reduce diff with master
|
2019-06-12 09:34:41 -07:00 |
Eddie Hung
|
f9433cc34b
|
Remove abc_flop{,_d} attributes from ice40/cells_sim.v
|
2019-06-12 09:29:30 -07:00 |
Eddie Hung
|
99267f660f
|
Fix spacing
|
2019-06-12 09:21:52 -07:00 |
Eddie Hung
|
738fdfe8f5
|
Remove wide mux inference
|
2019-06-12 09:20:46 -07:00 |
Eddie Hung
|
1e838a8913
|
Retry "Add "-W' wire delay arg to abc9, use from synth_xilinx"
|
2019-06-12 08:49:15 -07:00 |
Eddie Hung
|
4c9fde87d1
|
Revert "Add "-W' wire delay arg to abc9, use from synth_xilinx"
This reverts commit 2dffa4685b .
|
2019-06-12 08:48:45 -07:00 |
Eddie Hung
|
2dffa4685b
|
Add "-W' wire delay arg to abc9, use from synth_xilinx
|
2019-06-11 17:10:47 -07:00 |
Eddie Hung
|
54379f9872
|
Disable dist RAM boxes due to comb loop
|
2019-06-11 12:02:51 -07:00 |
Eddie Hung
|
8a708d1fdb
|
Remove #ifndef ABC
|
2019-06-11 12:02:31 -07:00 |
Eddie Hung
|
b77c5da769
|
Revert "Revert "Move ff_map back after ABC for shregmap""
This reverts commit e473e74565 .
|
2019-06-10 14:37:09 -07:00 |
Eddie Hung
|
a1d4ae78a0
|
Revert "Rename shregmap -tech xilinx -> xilinx_dynamic"
This reverts commit 94a5f4e609 .
|
2019-06-10 14:34:43 -07:00 |
Eddie Hung
|
352c532bb2
|
Merge remote-tracking branch 'origin/master' into xc7mux
|
2019-06-10 11:02:54 -07:00 |
Simon Schubert
|
abf90b0403
|
ice40/cells_sim.v: Add support for RGB_DRV/LED_DRV_CUR for u4k
|
2019-06-10 11:49:08 +02:00 |
Eddie Hung
|
816b5f5891
|
Comment out muxpack (currently broken)
|
2019-06-07 16:58:57 -07:00 |
Eddie Hung
|
88ae13e6a5
|
$__XILINX_MUX_ -> $__XILINX_SHIFTX
|
2019-06-06 15:32:36 -07:00 |
Eddie Hung
|
d3b7ae218b
|
Fix muxcover and its techmapping
|
2019-06-06 15:31:18 -07:00 |
Eddie Hung
|
a8c49168fb
|
Run muxpack and muxcover in synth_xilinx
|
2019-06-06 14:43:08 -07:00 |
Eddie Hung
|
7166dbe418
|
Remove abc_flop attributes for now
|
2019-06-06 14:35:38 -07:00 |
Eddie Hung
|
eaee250a6e
|
Merge remote-tracking branch 'origin/eddie/muxpack' into xc7mux
|
2019-06-06 14:06:59 -07:00 |
David Shah
|
30cedaca10
|
Merge pull request #1073 from whitequark/ecp5-diamond-iob
ECP5: implement most Diamond I/O buffer primitives
|
2019-06-06 11:22:49 +01:00 |
whitequark
|
f3a26730b6
|
ECP5: implement all Diamond I/O buffer primitives.
|
2019-06-06 10:18:33 +00:00 |
Eddie Hung
|
6ed15b7890
|
Update abc attributes on FD*E_1
|
2019-06-05 12:33:40 -07:00 |
Eddie Hung
|
67f744d428
|
Cleanup
|
2019-06-05 12:28:46 -07:00 |
Eddie Hung
|
2c18d530ea
|
Call shregmap -tech xilinx_static
|
2019-06-05 12:28:26 -07:00 |
Eddie Hung
|
e473e74565
|
Revert "Move ff_map back after ABC for shregmap"
This reverts commit 9b9bd4e19f .
|
2019-06-05 11:53:06 -07:00 |
Eddie Hung
|
94a5f4e609
|
Rename shregmap -tech xilinx -> xilinx_dynamic
|
2019-06-04 14:34:36 -07:00 |
Eddie Hung
|
82d41bc2f2
|
Add space between -D and _ABC
|
2019-06-04 11:54:08 -07:00 |
Eddie Hung
|
f0e93f33cf
|
Add (* abc_flop_q *) to brams_bb.v
|
2019-06-04 11:53:51 -07:00 |
Eddie Hung
|
6cf092641f
|
Fix name clash
|
2019-06-04 09:56:36 -07:00 |
Eddie Hung
|
e260150321
|
Add mux_map.v for wide mux
|
2019-06-04 09:51:47 -07:00 |
Eddie Hung
|
9b9bd4e19f
|
Move ff_map back after ABC for shregmap
|
2019-06-03 23:43:23 -07:00 |
Eddie Hung
|
09b778744d
|
Respect -nocarry
|
2019-06-03 23:42:30 -07:00 |
Eddie Hung
|
5afa42432f
|
Fix pmux2shiftx logic
|
2019-06-03 23:29:45 -07:00 |
Eddie Hung
|
23a73ca624
|
Merge mistake
|
2019-06-03 23:19:22 -07:00 |
Eddie Hung
|
f81a0ed92e
|
Merge remote-tracking branch 'origin/master' into xc7mux
|
2019-06-03 23:07:08 -07:00 |
Eddie Hung
|
b6e59741ae
|
Typo
|
2019-06-03 20:21:41 -07:00 |
Eddie Hung
|
02973474df
|
Remove extra newline
|
2019-06-03 20:04:47 -07:00 |
Eddie Hung
|
c9a0bac541
|
IS_C_INVERTED
|
2019-06-03 19:45:56 -07:00 |
Eddie Hung
|
0ad50332d9
|
Execute techmap and arith_map simultaneously
|
2019-06-03 19:36:09 -07:00 |
Eddie Hung
|
ebcc85b9b8
|
Fix `ifndef
|
2019-06-03 12:37:02 -07:00 |
Eddie Hung
|
0092770317
|
Make SB_LUT4 a whitebox, SB_DFF a blackbox (for now)
|
2019-06-03 12:34:55 -07:00 |
Eddie Hung
|
4da25c76b3
|
Ooopsie
|
2019-06-03 09:33:42 -07:00 |
Eddie Hung
|
9f44a71715
|
Consistent with xilinx
|
2019-06-03 09:23:43 -07:00 |
Eddie Hung
|
2228cef62f
|
Add flops as blackboxes
|
2019-05-31 18:11:46 -07:00 |
Eddie Hung
|
01f71085f2
|
Add FD*E_1 -> FD*E techmap rules
|
2019-05-31 18:11:24 -07:00 |
Eddie Hung
|
dea36d4366
|
Techmap flops before ABC again
|
2019-05-31 18:10:25 -07:00 |
Eddie Hung
|
eb08e71bd1
|
Merge branch 'xaig' into xc7mux
|
2019-05-31 13:03:03 -07:00 |
Eddie Hung
|
1ad33c3b5a
|
Remove whitebox attribute from DRAMs for now
|
2019-05-30 13:07:29 -07:00 |
Eddie Hung
|
fdfc18be91
|
Carry in/out to be the last input/output for chains to be preserved
|
2019-05-30 01:23:36 -07:00 |
Eddie Hung
|
276f5f8b81
|
Some more realistic delays...
|
2019-05-29 22:55:34 -07:00 |
Eddie Hung
|
f228621b80
|
Typo
|
2019-05-28 09:36:01 -07:00 |
Eddie Hung
|
e032e5bcde
|
Make MUXF{7,8} and CARRY4 whitebox
|
2019-05-27 23:09:06 -07:00 |
Eddie Hung
|
54e28eb3ea
|
Re-enable lib_whitebox
|
2019-05-27 23:08:55 -07:00 |
Eddie Hung
|
4311b9b583
|
Blackboxes
|
2019-05-26 11:32:02 -07:00 |
Eddie Hung
|
66701c5fcc
|
Muck about with LUT delays some more
|
2019-05-26 02:52:48 -07:00 |
Eddie Hung
|
ca5774ed40
|
Try new LUT delays
|
2019-05-24 20:39:55 -07:00 |
Eddie Hung
|
60af2ca94d
|
Transpose CARRY4 delays
|
2019-05-24 14:09:15 -07:00 |
Eddie Hung
|
52e9036d39
|
Merge remote-tracking branch 'origin/master' into xc7mux
|
2019-05-23 13:38:04 -07:00 |
Eddie Hung
|
68359bcd6f
|
Merge remote-tracking branch 'origin/eddie/opt_rmdff' into xc7mux
|
2019-05-23 13:37:53 -07:00 |
Eddie Hung
|
99a3fee8f4
|
Add "min bits" and "min wports" to xilinx dram rules
|
2019-05-23 11:32:28 -07:00 |
Eddie Hung
|
ae89e6ab26
|
Add whitebox support to DRAM
|
2019-05-23 08:58:57 -07:00 |
Eddie Hung
|
4f44e3399b
|
shift register inference before mux
|
2019-05-22 02:36:28 -07:00 |
Eddie Hung
|
9b1078b9bd
|
Fix/workaround symptom unveiled by #1023
|
2019-05-21 18:50:02 -07:00 |
Eddie Hung
|
ee8435b820
|
Instead of MUXCY/XORCY use CARRY4 (with timing)
|
2019-05-21 16:19:45 -07:00 |
Eddie Hung
|
36a219063a
|
Modify LUT area cost to be same as old abc
|
2019-05-21 14:31:19 -07:00 |
Eddie Hung
|
fb09c6219b
|
Merge remote-tracking branch 'origin/master' into xc7mux
|
2019-05-21 14:21:00 -07:00 |
Clifford Wolf
|
c4b8575f43
|
Add "wreduce -keepdc", fixes #1016
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2019-05-20 15:36:13 +02:00 |
Sylvain Munaut
|
4f9183d107
|
ice40/cells_sim.v: Add support for TRIM input to SB_HFOSC
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
|
2019-05-13 12:51:06 +02:00 |
Clifford Wolf
|
04ef222cfb
|
Add "stat -tech xilinx"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2019-05-11 09:24:52 +02:00 |
Ben Widawsky
|
05d8cc4567
|
Fix formatting for synth_intel.cc
This is realized through the recently added .clang-format file.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
|
2019-05-09 08:40:05 -07:00 |
Clifford Wolf
|
09467bb9a3
|
Add "synth_xilinx -arch"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2019-05-07 15:04:36 +02:00 |
Eddie Hung
|
d9c4644e88
|
Merge remote-tracking branch 'origin/master' into clifford/specify
|
2019-05-03 15:05:57 -07:00 |
Eddie Hung
|
c2e29ab809
|
Rename cells_map.v to prevent clash with ff_map.v
|
2019-05-03 14:40:32 -07:00 |
Clifford Wolf
|
373b236108
|
Merge pull request #969 from YosysHQ/clifford/pmgenstuff
Improve pmgen, Add "peepopt" pass with shift-mul pattern
|
2019-05-03 20:39:50 +02:00 |
Eddie Hung
|
283e33ba5a
|
Trim off leading 1'bx in A
|
2019-05-02 16:02:37 -07:00 |
Eddie Hung
|
fc72f07efd
|
Add don't care optimisation
|
2019-05-02 15:01:37 -07:00 |
Eddie Hung
|
d80445e049
|
Use new peepopt from #969
|
2019-05-02 11:35:57 -07:00 |
Eddie Hung
|
8829cba901
|
Merge remote-tracking branch 'origin/clifford/pmgenstuff' into xc7mux
|
2019-05-02 11:25:34 -07:00 |
Eddie Hung
|
95867109ea
|
Revert to pre-muxcover approach
|
2019-05-02 11:25:10 -07:00 |
Eddie Hung
|
d05ac7257e
|
Missing help_mode
|
2019-05-02 11:14:28 -07:00 |
Eddie Hung
|
3b5e8c86a4
|
Fix -nocarry
|
2019-05-02 11:00:49 -07:00 |
Eddie Hung
|
5cd19b52da
|
Merge remote-tracking branch 'origin/master' into xc7mux
|
2019-05-02 10:44:59 -07:00 |
Eddie Hung
|
d394b9301b
|
Back to passing all xc7srl tests!
|
2019-05-01 18:23:21 -07:00 |
Eddie Hung
|
31ff0d8ef5
|
Merge remote-tracking branch 'origin/master' into eddie/synth_xilinx_fine
|
2019-05-01 18:09:38 -07:00 |
Clifford Wolf
|
a27eeff573
|
Merge pull request #966 from YosysHQ/clifford/fix956
Drive dangling wires with init attr with their init value
|
2019-04-30 18:08:41 +02:00 |
Clifford Wolf
|
9d117eba9d
|
Add handling of init attributes in "opt_expr -undriven"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2019-04-30 14:46:12 +02:00 |
Marcin Kościelnicki
|
98e5a625c4
|
synth_xilinx: Add -nocarry and -nomux options.
|
2019-04-30 12:54:21 +02:00 |
Clifford Wolf
|
d2d402e625
|
Run "peepopt" in generic "synth" pass and "synth_ice40"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2019-04-30 08:10:37 +02:00 |
Eddie Hung
|
e97178a888
|
WIP
|
2019-04-28 12:51:00 -07:00 |
Eddie Hung
|
af840bbc63
|
Move neg-pol to pos-pol mapping from ff_map to cells_map.v
|
2019-04-28 12:36:04 -07:00 |
Eddie Hung
|
4aca928033
|
Fix spacing
|
2019-04-26 19:46:34 -07:00 |
Eddie Hung
|
d855683917
|
Revert synth_xilinx 'fine' label more to how it used to be...
|
2019-04-26 16:53:16 -07:00 |
Eddie Hung
|
ccc283737d
|
Apparently, this reduces number of MUXCY/XORCY
|
2019-04-26 16:28:48 -07:00 |
Eddie Hung
|
e31e21766d
|
Try a different approach with 'muxcover'
|
2019-04-26 16:09:54 -07:00 |
Eddie Hung
|
76b7c5d4cc
|
Merge remote-tracking branch 'origin/master' into xc7mux
|
2019-04-26 15:35:55 -07:00 |
Eddie Hung
|
ea0e0722bb
|
Where did this check come from!?!
|
2019-04-26 15:35:34 -07:00 |
Eddie Hung
|
6b9ca7cd6d
|
Remove split_shiftx call
|
2019-04-26 15:32:58 -07:00 |
Eddie Hung
|
8469d9fe9f
|
Missing newline
|
2019-04-26 14:51:37 -07:00 |
Eddie Hung
|
727eec04c5
|
Refactor synth_xilinx to auto-generate doc
|
2019-04-26 14:32:18 -07:00 |
Eddie Hung
|
1ea6d7920f
|
Cleanup ice40
|
2019-04-26 14:31:59 -07:00 |
Eddie Hung
|
f14d7f0df6
|
Cleanup superseded
|
2019-04-25 19:43:41 -07:00 |
Eddie Hung
|
019c48b508
|
bitblast_shiftx -> split_shiftx
|
2019-04-25 19:38:35 -07:00 |
Eddie Hung
|
feff976454
|
synth_xilinx to call bitblast_shiftx
|
2019-04-25 17:11:18 -07:00 |
Eddie Hung
|
f96d82a5f1
|
Add -nocarry option to synth_xilinx
|
2019-04-24 16:46:41 -07:00 |
Clifford Wolf
|
64925b4e8f
|
Improve $specrule interface
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2019-04-23 22:57:10 +02:00 |
Eddie Hung
|
91c3afcab7
|
Use nonblocking
|
2019-04-23 13:42:06 -07:00 |
Clifford Wolf
|
4575e4ad86
|
Improve $specrule interface
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2019-04-23 22:18:04 +02:00 |
Clifford Wolf
|
71c38d9de5
|
Add $specrule cells for $setup/$hold/$skew specify rules
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2019-04-23 21:36:59 +02:00 |
Clifford Wolf
|
e807e88b60
|
Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std nomenclature
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2019-04-23 21:36:59 +02:00 |
Clifford Wolf
|
a7e11261bd
|
Add $specify2 and $specify3 cells to simlib
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2019-04-23 21:36:59 +02:00 |
Eddie Hung
|
0bd2bfa737
|
Merge remote-tracking branch 'origin/master' into xaig
|
2019-04-22 18:15:28 -07:00 |
Eddie Hung
|
60026842b2
|
Tweak
|
2019-04-22 17:59:56 -07:00 |
Eddie Hung
|
26e461f47d
|
Fix for A_WIDTH == 2 but B_WIDTH==3
|
2019-04-22 17:58:28 -07:00 |
Eddie Hung
|
1fa2c36fbd
|
Trim A_WIDTH by Y_WIDTH-1
|
2019-04-22 17:14:11 -07:00 |
Eddie Hung
|
69863f7698
|
Add comment
|
2019-04-22 16:58:44 -07:00 |
Eddie Hung
|
61161faefc
|
Fix for mux_case_* mappings
|
2019-04-22 16:56:18 -07:00 |
Eddie Hung
|
ac1e13819e
|
Fix for non-pow2 width muxes
|
2019-04-22 14:26:13 -07:00 |
Eddie Hung
|
75b96b1aff
|
Add synth_xilinx -nomux option
|
2019-04-22 12:36:15 -07:00 |
Eddie Hung
|
79fb291dbe
|
Cleanup, call pmux2shiftx even without -nosrl
|
2019-04-22 12:14:37 -07:00 |
Eddie Hung
|
4cfef7897f
|
Merge branch 'xaig' into xc7mux
|
2019-04-22 11:58:59 -07:00 |
Eddie Hung
|
4486a98fd5
|
Merge remote-tracking branch 'origin/xc7srl' into xc7mux
|
2019-04-22 11:45:49 -07:00 |
Eddie Hung
|
ec88129a5c
|
Update help message
|
2019-04-22 11:38:23 -07:00 |
Eddie Hung
|
4883391b63
|
Merge remote-tracking branch 'origin/master' into xaig
|
2019-04-22 11:19:52 -07:00 |
Eddie Hung
|
0e76718720
|
Move 'shregmap -tech xilinx' into map_cells
|
2019-04-22 10:45:39 -07:00 |
Eddie Hung
|
e300b1922c
|
Merge remote-tracking branch 'origin/master' into xc7srl
|
2019-04-22 10:36:27 -07:00 |
Clifford Wolf
|
0e7901e45c
|
Merge pull request #941 from Wren6991/sim_lib_io_clke
ice40 cells_sim.v: update clock enable behaviour based on hardware experiments
|
2019-04-22 09:11:13 +02:00 |
Clifford Wolf
|
913659d644
|
Merge branch 'master' of https://github.com/dh73/yosys_gowin into dh73-master
|
2019-04-22 09:09:27 +02:00 |
Clifford Wolf
|
cf1ba46fa0
|
Re-added clean after techmap in synth_xilinx
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2019-04-22 09:03:11 +02:00 |
Clifford Wolf
|
cbd9b8a3f3
|
Merge pull request #916 from YosysHQ/map_cells_before_map_luts
synth_xilinx to map_cells before map_luts
|
2019-04-22 09:01:00 +02:00 |
Clifford Wolf
|
19fd411e77
|
Merge pull request #911 from mmicko/gowin-nobram
Make nobram false by default for gowin
|
2019-04-22 08:58:09 +02:00 |
Eddie Hung
|
d342b5b135
|
Tidy up, fix for -nosrl
|
2019-04-21 15:33:03 -07:00 |
Eddie Hung
|
d7f0700bae
|
Convert to use #945
|
2019-04-21 15:19:02 -07:00 |
Eddie Hung
|
726e2da8f2
|
Merge branch 'map_cells_before_map_luts' into xc7srl
|
2019-04-21 14:28:55 -07:00 |
Eddie Hung
|
a3371e118b
|
Merge branch 'master' into map_cells_before_map_luts
|
2019-04-21 14:24:50 -07:00 |
Eddie Hung
|
ae95aba60a
|
Add comments
|
2019-04-21 14:16:59 -07:00 |
Eddie Hung
|
d99422411f
|
Use new pmux2shiftx from #944, remove my old attempt
|
2019-04-21 14:16:34 -07:00 |
Luke Wren
|
71da836300
|
ice40 cells_sim.v: SB_IO: update clock enable behaviour based on hardware experiments
|
2019-04-21 21:40:11 +01:00 |