Eddie Hung
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6e475484b2
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Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl
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2019-08-30 09:37:32 -07:00 |
David Shah
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91b46ed816
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ecp5: Add simulation equivalence check for Diamond FF implementations
Signed-off-by: David Shah <dave@ds0.me>
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2019-08-30 13:27:36 +01:00 |
whitequark
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d9c621f9d1
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ecp5: deduplicate Diamond FD/IFS/OFS/IO primitives.
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2019-08-30 10:05:09 +00:00 |
whitequark
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1e6b60d563
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ecp5: allow (and enable by default) GSR on FD/IFS/OFS primitives.
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2019-08-30 09:56:19 +00:00 |
whitequark
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6fa8ce93e6
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ecp5: add missing FD primitives.
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2019-08-30 09:54:48 +00:00 |
whitequark
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7e2825a2a4
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ecp5: fix CEMUX on IFS/OFS primitives.
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2019-08-30 09:42:33 +00:00 |
Eddie Hung
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25b1670a84
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Rename boxes too
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2019-08-29 07:03:32 -07:00 |
Eddie Hung
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a4f641f230
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Do not overwrite LUT param
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2019-08-28 18:46:53 -07:00 |
Eddie Hung
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d46d38e4d5
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Trailing comma
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2019-08-28 17:25:54 -07:00 |
Eddie Hung
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f5b4bc847c
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Adapt to $__ICE40_CARRY_WRAPPER
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2019-08-28 17:25:05 -07:00 |
Eddie Hung
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e569f13870
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Revert "Remove $__ICE40_FULL_ADDER handling from ice40_opt; cannot reason with"
This reverts commit 2aedee1f0e .
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2019-08-28 17:22:44 -07:00 |
Eddie Hung
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2aedee1f0e
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Remove $__ICE40_FULL_ADDER handling from ice40_opt; cannot reason with
CARRY_WRAPPER in the same way since I0 and I3 could be used
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2019-08-28 17:07:36 -07:00 |
Eddie Hung
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077e9d4ada
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Update box size and timings
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2019-08-28 17:07:24 -07:00 |
Eddie Hung
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129df7184a
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Update to new $__ICE40_CARRY_WRAPPER
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2019-08-28 17:07:07 -07:00 |
Eddie Hung
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9314a0a42e
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Add (* clkbuf_sink *) to SRLC16E, reorder ports to match vendor
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2019-08-28 10:51:39 -07:00 |
Eddie Hung
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ba5d81c7f1
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Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl
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2019-08-28 09:21:03 -07:00 |
David Shah
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13424352cc
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Merge pull request #1332 from YosysHQ/dave/ecp5gsr
ecp5: Add GSR and SGSR support
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2019-08-28 12:44:02 +01:00 |
Marcin Kościelnicki
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d361f5ab79
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xilinx: Add SRLC16E primitive.
Fixes #1331.
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2019-08-27 20:27:12 +02:00 |
David Shah
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fc001b4731
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ecp5: Add GSR support
Signed-off-by: David Shah <dave@ds0.me>
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2019-08-27 13:07:06 +01:00 |
Eddie Hung
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1ba09c4ab7
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Merge branch 'master' into eddie/xilinx_srl
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2019-08-26 13:56:31 -07:00 |
Eddie Hung
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a098205479
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Merge branch 'master' into mwk/xilinx_bufgmap
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2019-08-26 13:25:17 -07:00 |
Eddie Hung
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d7051b90de
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Add undocumented feature
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2019-08-23 16:41:32 -07:00 |
Eddie Hung
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08139aa53a
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xilinx_srl now copes with word-level flops $dff{,e}
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2019-08-23 12:22:46 -07:00 |
Eddie Hung
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78b7d8f531
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Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl
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2019-08-23 11:32:44 -07:00 |
Eddie Hung
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20f4d191b5
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Merge branch 'master' into mwk/xilinx_bufgmap
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2019-08-23 11:24:19 -07:00 |
Eddie Hung
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509c353fe9
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Forgot one
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2019-08-23 11:23:50 -07:00 |
Eddie Hung
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0d0ad15898
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Merge branch 'master' into mwk/xilinx_bufgmap
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2019-08-23 11:23:31 -07:00 |
Eddie Hung
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a270af00cc
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Put abc_* attributes above port
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2019-08-23 11:21:44 -07:00 |
Eddie Hung
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6872805a3e
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Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmap
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2019-08-23 10:00:50 -07:00 |
Eddie Hung
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7188972645
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Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl
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2019-08-22 10:32:54 -07:00 |
Clifford Wolf
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151db528e4
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Fix missing newline at end of file
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-08-22 18:09:37 +02:00 |
Clifford Wolf
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2c8c8b3c74
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Merge pull request #1289 from mmicko/anlogic_fixes
Anlogic fixes and optimization
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2019-08-22 18:09:10 +02:00 |
Clifford Wolf
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4c449caf9b
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Fix missing newline at end of file
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-08-22 18:06:36 +02:00 |
Clifford Wolf
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4d37710e82
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Merge pull request #1281 from mmicko/efinix
Initial support for Efinix Trion series FPGAs
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2019-08-22 18:06:02 +02:00 |
Eddie Hung
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15188033da
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Add variable length support to xilinx_srl
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2019-08-21 17:34:40 -07:00 |
Eddie Hung
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edec73fec1
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abc9 to perform new 'map_ffs' before 'map_luts'
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2019-08-21 15:37:55 -07:00 |
Eddie Hung
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5ce0c31d0e
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Add init support
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2019-08-21 13:05:10 -07:00 |
Eddie Hung
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076af2e617
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Missing newline
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2019-08-20 20:37:52 -07:00 |
Eddie Hung
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33960dd3d8
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Merge pull request #1209 from YosysHQ/eddie/synth_xilinx
[WIP] synth xilinx renaming, as per #1184
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2019-08-20 12:55:26 -07:00 |
Eddie Hung
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14c03861b6
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Merge pull request #1304 from YosysHQ/eddie/abc9_refactor
Refactor abc9 to use port attributes, not module attributes
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2019-08-20 11:59:31 -07:00 |
Eddie Hung
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d9fe4cccbf
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Merge remote-tracking branch 'origin/master' into eddie/synth_xilinx
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2019-08-20 11:57:52 -07:00 |
Eddie Hung
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d81a090d89
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Unify abc_carry_{in,out} into abc_carry and use port dir, as @mithro
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2019-08-19 09:56:17 -07:00 |
Miodrag Milanovic
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4a32e29445
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Merge remote-tracking branch 'upstream/master' into anlogic_fixes
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2019-08-18 11:47:46 +02:00 |
whitequark
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101235400c
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Merge branch 'master' into eddie/pr1266_again
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2019-08-18 08:04:10 +00:00 |
Eddie Hung
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1c57b1e7ea
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Update abc_* attr in ecp5 and ice40
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2019-08-16 15:56:57 -07:00 |
Eddie Hung
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562c9e3624
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Attach abc_scc_break, abc_carry_{in,out} attr to ports not modules
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2019-08-16 15:40:53 -07:00 |
Eddie Hung
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41191f1ea4
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Merge pull request #1250 from bwidawsk/master
techlibs/intel: Clean up Makefile
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2019-08-16 14:07:09 -07:00 |
Marcin Kościelnicki
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3c75a72feb
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move attributes to wires
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2019-08-13 19:36:59 +00:00 |
Marcin Kościelnicki
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49765ec19e
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minor review fixes
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2019-08-13 18:05:49 +00:00 |
Marcin Kościelnicki
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c6d5b97b98
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review fixes
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2019-08-13 00:35:54 +00:00 |