Marcin Kościelnicki
f4c62f33ac
Add clock buffer insertion pass, improve iopadmap.
...
A few new attributes are defined for use in cell libraries:
- iopad_external_pin: marks PAD cell's external-facing pin. Pad
insertion will be skipped for ports that are already connected
to such a pin.
- clkbuf_sink: marks an input pin as a clock pin, requesting clock
buffer insertion.
- clkbuf_driver: marks an output pin as a clock buffer output pin.
Clock buffer insertion will be skipped for nets that are already
driven by such a pin.
All three are module attributes that should be set to a comma-separeted
list of pin names.
Clock buffer insertion itself works as follows:
1. All cell ports, starting from bottom up, can be marked as clock sinks
(requesting clock buffer insertion) or as clock buffer outputs.
2. If a wire in a given module is driven by a cell port that is a clock
buffer output, it is in turn also considered a clock buffer output.
3. If an input port in a non-top module is connected to a clock sink in a
contained cell, it is also in turn considered a clock sink.
4. If a wire in a module is driven by a non-clock-buffer cell, and is
also connected to a clock sink port in a contained cell, a clock
buffer is inserted in this module.
5. For the top module, a clock buffer is also inserted on input ports
connected to clock sinks, optionally with a special kind of input
PAD (such as IBUFG for Xilinx).
6. Clock buffer insertion on a given wire is skipped if the clkbuf_inhibit
attribute is set on it.
2019-08-13 00:16:38 +02:00
Eddie Hung
8a2480526f
Fix $lut pin ordering inside $__ICE40_CARRY_WRAPPER
2019-08-12 12:19:25 -07:00
Eddie Hung
12c692f6ed
Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_adder"
...
This reverts commit c851dc1310
, reversing
changes made to f54bf1631f
.
2019-08-12 12:06:45 -07:00
Miodrag Milanovic
5f561bdcb1
Proper arith for Anlogic and use standard pass
2019-08-12 20:21:36 +02:00
Miodrag Milanovic
2897fe4d09
Fix formating
2019-08-11 17:05:24 +02:00
Miodrag Milanovic
ead2b52b5a
one bit enable signal
2019-08-11 13:59:39 +02:00
Miodrag Milanovic
aa0c37722a
fix mixing signals on FF mapping
2019-08-11 11:40:15 +02:00
Miodrag Milanovic
853c755a0c
Replaced custom step with setundef
2019-08-11 11:01:46 +02:00
Miodrag Milanovic
e609537e38
Fixed data width
2019-08-11 10:46:48 +02:00
Miodrag Milanovic
8c8100e0df
Adding new pass to fix carry chain
2019-08-11 10:17:49 +02:00
Miodrag Milanovic
b3a91d6508
cleanup
2019-08-11 08:37:56 +02:00
David Shah
f9020ce2b3
Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER"
2019-08-10 17:14:48 +01:00
Clifford Wolf
f54bf1631f
Merge pull request #1258 from YosysHQ/eddie/cleanup
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Cleanup a few barnacles across codebase
2019-08-10 09:52:14 +02:00
Clifford Wolf
a469d1a64a
Merge pull request #1270 from YosysHQ/eddie/alu_lcu_doc
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Add a few comments to document $alu and $lcu
2019-08-10 09:46:46 +02:00
Eddie Hung
041defc5a6
Reformat so it shows up/looks nice when "help $alu" and "help $alu+"
2019-08-09 12:33:39 -07:00
Eddie Hung
acfb672d34
A bit more on where $lcu comes from
2019-08-09 09:50:47 -07:00
Eddie Hung
5aef998957
Add more comments
2019-08-09 09:48:17 -07:00
Miodrag Milanovic
d51b135e33
Fix CO
2019-08-09 12:37:10 +02:00
Miodrag Milanovic
7a860c5623
Merge remote-tracking branch 'upstream/master' into efinix
2019-08-09 09:46:37 +02:00
Eddie Hung
dae7c59358
Add a few comments to document $alu and $lcu
2019-08-08 10:05:28 -07:00
Eddie Hung
9776084eda
Allow whitebox modules to be overwritten
2019-08-07 16:40:24 -07:00
Eddie Hung
675c1d4218
Add ice40_wrapcarry pass, rename $__ICE40_FULL_ADDER -> CARRY_WRAPPER
2019-08-07 16:29:38 -07:00
Eddie Hung
cc331cf70d
Add test
2019-08-07 16:29:38 -07:00
Eddie Hung
ea8ac8fd74
Remove ice40_unlut
2019-08-07 16:29:38 -07:00
Eddie Hung
6b314c8371
Wrap SB_CARRY+SB_LUT into $__ICE40_FULL_ADDER
2019-08-07 16:29:38 -07:00
Eddie Hung
6d77236f38
substr() -> compare()
2019-08-07 12:20:08 -07:00
Eddie Hung
7164996921
RTLIL::S{0,1} -> State::S{0,1}
2019-08-07 11:12:38 -07:00
Eddie Hung
e6d5147214
Merge remote-tracking branch 'origin/master' into eddie/cleanup
2019-08-07 11:11:50 -07:00
Eddie Hung
48d0f99406
stoi -> atoi
2019-08-07 11:09:17 -07:00
David Shah
5545cd3c10
Merge pull request #1260 from YosysHQ/dave/ecp5_cell_fixes
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ecp5: Make cells_sim.v consistent with nextpnr
2019-08-07 15:35:29 +01:00
David Shah
a36fd8582e
ecp5: Make cells_sim.v consistent with nextpnr
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Signed-off-by: David Shah <dave@ds0.me>
2019-08-07 14:19:31 +01:00
Clifford Wolf
4c49ddf36a
Merge pull request #1249 from mmicko/anlogic_fix
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anlogic : Fix alu mapping
2019-08-07 12:30:52 +02:00
Eddie Hung
e5be9ff871
Fix spacing
2019-08-06 16:47:55 -07:00
Eddie Hung
c11ad24fd7
Use std::stoi instead of atoi(<str>.c_str())
2019-08-06 16:45:48 -07:00
Eddie Hung
3486235338
Make liberal use of IdString.in()
2019-08-06 16:18:18 -07:00
Clifford Wolf
023086bd46
Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-06 04:47:55 +02:00
Ben Widawsky
7de098ad45
techlibs/intel: Clean up Makefile
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Use GNU make's foreach iterator and remove nonexistent files. Gmake is
already a requirement of the build system.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2019-08-05 11:22:11 -07:00
Miodrag Milanovic
8a3329871b
clock for ram trough gbuf
2019-08-04 12:17:55 +02:00
Miodrag Milanovic
cf96f41c6d
Added bram support
2019-08-04 11:46:36 +02:00
Miodrag Milanovic
837cb0a1b9
anlogic : Fix alu mapping
2019-08-03 14:47:33 +02:00
Miodrag Milanovic
6e210f26fa
Custom step to add global clock buffers
2019-08-03 14:40:23 +02:00
Miodrag Milanovic
ab98f604fd
Initial EFINIX support
2019-08-03 13:10:44 +02:00
Clifford Wolf
f4ae6afc22
Merge pull request #1239 from mmicko/mingw_fix
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Fix formatting for msys2 mingw build
2019-08-02 16:37:57 +02:00
Miodrag Milanovic
28b7053a01
Fix formatting for msys2 mingw build using GetSize
2019-08-01 17:27:34 +02:00
Eddie Hung
66806085db
RST -> RSTBRST for RAMB8BWER
2019-07-29 16:05:44 -07:00
Clifford Wolf
eb663c7579
Merge branch 'ZirconiumX-synth_intel_m9k'
2019-07-25 17:23:48 +02:00
Clifford Wolf
5c933e5110
Merge pull request #1218 from ZirconiumX/synth_intel_iopads
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intel: Make -noiopads the default
2019-07-25 17:19:54 +02:00
Eddie Hung
5248a902ef
Merge pull request #1224 from YosysHQ/xilinx_fix_ff
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xilinx: Fix missing cell name underscore in cells_map.v
2019-07-25 06:44:17 -07:00
David Shah
ab607e896e
xilinx: Fix missing cell name underscore in cells_map.v
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Signed-off-by: David Shah <dave@ds0.me>
2019-07-25 08:19:07 +01:00
Dan Ravensloft
49528ed3bd
intel: Make -noiopads the default
2019-07-24 10:38:15 +01:00
Dan Ravensloft
67b4ce06e0
intel: Map M9K BRAM only on families that have it
...
This regresses Cyclone V and Cyclone 10 substantially, but these
numbers were artificial, targeting a BRAM that they did not contain.
Amusingly, synth_intel still does better when synthesizing PicoSoC
than Quartus when neither are inferring block RAM.
2019-07-23 18:11:11 +01:00
David Shah
80884d6f7b
ice40: Fix test_dsp_model.sh
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Signed-off-by: David Shah <dave@ds0.me>
2019-07-19 17:33:57 +01:00
David Shah
79f14c7514
ice40/cells_sim.v: Fix sign of J and K partial products
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Signed-off-by: David Shah <dave@ds0.me>
2019-07-19 17:33:41 +01:00
David Shah
3c84271543
ice40/cells_sim.v: LSB of A/B only signed in 8x8 mode
...
Signed-off-by: David Shah <dave@ds0.me>
2019-07-19 17:13:34 +01:00
Eddie Hung
171cd2ff73
Add tests for all combinations of A and B signedness for comb mul
2019-07-19 08:52:49 -07:00
Eddie Hung
f7753720fe
Don't copy ref if exists already
2019-07-19 08:45:35 -07:00
Eddie Hung
43616e1414
Update Makefile too
2019-07-18 14:51:55 -07:00
Eddie Hung
b97fe6e866
Work in progress for renaming labels/options in synth_xilinx
2019-07-18 14:20:43 -07:00
David Shah
9cb0456b6f
Merge pull request #1208 from ZirconiumX/intel_cleanups
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Assorted synth_intel cleanups from @bwidawsk
2019-07-18 19:04:28 +01:00
Dan Ravensloft
0c999ac2c4
synth_intel: Use stringf
2019-07-18 19:02:23 +01:00
Dan Ravensloft
50f5e29724
synth_intel: s/not family/no family/
2019-07-18 17:28:21 +01:00
Ben Widawsky
999811572a
intel_synth: Fix help message
...
cyclonev has been a "supported" family since the initial commit. The old
commit message suggested to use a10gx which is incorrect.
Aside from the obvious lack of functional change due to this just being
a help message, users who were previously using "a10gx" for "cyclonev" will
also have no functional change by using "cyclonev" instead.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2019-07-18 17:06:25 +01:00
Ben Widawsky
f950a7a75d
intel_synth: Small code cleanup to remove if ladder
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Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2019-07-18 17:06:12 +01:00
Ben Widawsky
809b94a67b
intel_synth: Make family explicit and match
...
The help and code default to MAX10 for the family, however the couple of
if ladders defaulted to cycloneive. Fix this inconsistency and the next
patch will clean it up.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2019-07-18 17:06:03 +01:00
Ben Widawsky
060e77c09b
intel_synth: Minor code cleanups
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Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2019-07-18 17:05:54 +01:00
Dan Ravensloft
c78ab8ebc5
synth_intel: rename for consistency with #1184
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Also fix a typo in the help message.
2019-07-18 16:46:21 +01:00
Clifford Wolf
e66e8fb59d
Merge pull request #1184 from whitequark/synth-better-labels
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synth_{ice40,ecp5}: more sensible pass label naming
2019-07-18 15:34:28 +02:00
David Shah
82153059a1
Merge pull request #1204 from smunaut/fix_1187
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ice40: Adapt the relut process passes to the new $lut/SB_LUT4 port map
2019-07-17 07:55:26 +01:00
Sylvain Munaut
f28e38de99
ice40: Adapt the relut process passes to the new $lut <=> SB_LUT4 port map
...
The new mapping introduced in 437fec0d88
needed matching adaptation when converting and optimizing LUTs during
the relut process
Fixes #1187
(Diagnosis of the issue by @daveshah1 on IRC)
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2019-07-16 23:57:15 +02:00
whitequark
698ab9beee
synth_ecp5: rename dram to lutram everywhere.
2019-07-16 20:45:12 +00:00
whitequark
ba099bfe9b
synth_{ice40,ecp5}: more sensible pass label naming.
2019-07-16 20:41:51 +00:00
Eddie Hung
7a58ee78dc
gen_lut to return correctly sized LUT mask
2019-07-16 12:45:29 -07:00
Eddie Hung
ba8ccbdea8
Merge pull request #1186 from YosysHQ/eddie/abc9_ice40_fix
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abc9/ice40: encapsulate SB_CARRY+SB_LUT4 into one box
2019-07-16 08:52:14 -07:00
Eddie Hung
5fb27c071b
$__ICE40_CARRY_LUT4 -> $__ICE40_FULL_ADDER as per @whitequark
2019-07-15 12:03:51 -07:00
Eddie Hung
d032198fac
ice40_opt to $__ICE40_CARRY_LUT4 into $lut not SB_LUT
2019-07-13 01:11:00 -07:00
Clifford Wolf
463f710066
Merge pull request #1183 from whitequark/ice40-always-relut
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synth_ice40: switch -relut to be always on
2019-07-12 10:48:00 +02:00
Eddie Hung
7a912f22b2
Use Const::from_string() not its constructor...
2019-07-12 01:32:10 -07:00
Eddie Hung
28274dfb09
Off by one
2019-07-12 01:17:53 -07:00
Eddie Hung
e0e5d7d68e
Fix spacing
2019-07-12 01:15:22 -07:00
Eddie Hung
4de03bd5e6
Remove double push
2019-07-12 01:08:48 -07:00
Eddie Hung
62ac5ebd02
Map to and from this box if -abc9
2019-07-12 00:53:01 -07:00
Eddie Hung
0f5bddcd79
ice40_opt to handle this box and opt back to SB_LUT4
2019-07-12 00:52:31 -07:00
Eddie Hung
a79ff2501e
Add new box to cells_sim.v
2019-07-12 00:52:19 -07:00
Eddie Hung
c6e16e1334
_ABC macro will map and unmap to this new box
2019-07-12 00:51:37 -07:00
Eddie Hung
fc3d74616f
Combine SB_CARRY+SB_LUT into one $__ICE40_CARRY_LUT4 box
2019-07-12 00:50:42 -07:00
whitequark
b700a4b1c5
synth_ice40: switch -relut to be always on.
2019-07-11 20:18:41 +00:00
whitequark
a8c5f7f41e
synth_ice40: fix help text typo. NFC.
2019-07-11 20:18:41 +00:00
Eddie Hung
19c1c3cfa3
Merge pull request #1182 from koriakin/xc6s-bram
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synth_xilinx: Initial Spartan 6 block RAM inference support.
2019-07-11 12:55:35 -07:00
Marcin Kościelnicki
a9efacd01d
xilinx: Fix the default values for FDPE/FDSE INIT attributes to match ISE/Vivado.
2019-07-11 21:13:12 +02:00
Marcin Kościelnicki
ce250b341c
synth_xilinx: Initial Spartan 6 block RAM inference support.
2019-07-11 14:45:48 +02:00
Eddie Hung
bb2144ae73
Merge pull request #1180 from YosysHQ/eddie/no_abc9_retime
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Error out if -abc9 and -retime specified
2019-07-10 14:38:13 -07:00
Eddie Hung
2f990a7319
Merge pull request #1148 from YosysHQ/xc7mux
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synth_xilinx to infer wide multiplexers using new '-widemux <min>' option
2019-07-10 14:38:00 -07:00
Eddie Hung
6bbd286e03
Error out if -abc9 and -retime specified
2019-07-10 12:47:48 -07:00
Eddie Hung
58bb84e5b2
Add some spacing
2019-07-10 12:32:33 -07:00
Eddie Hung
521971e32e
Add some ASCII art explaining mux decomposition
2019-07-10 12:20:04 -07:00
Eddie Hung
e573d024a2
Call muxpack and pmux2shiftx before cmp2lut
2019-07-09 21:26:38 -07:00
Eddie Hung
c55530b901
Restore opt_clean back to original place
2019-07-09 14:29:58 -07:00
Eddie Hung
5b48b18d29
Restore missing techmap -map +/cmp2lut.v with LUT_WIDTH=6
2019-07-09 14:28:54 -07:00
David Shah
27b27b8781
synth_ecp5: Fix typo in copyright header
...
Signed-off-by: David Shah <dave@ds0.me>
2019-07-09 22:26:10 +01:00
Eddie Hung
b1a048a703
Extend using A[1] to preserve don't care
2019-07-09 12:35:41 -07:00