Dan Ravensloft
67b4ce06e0
intel: Map M9K BRAM only on families that have it
...
This regresses Cyclone V and Cyclone 10 substantially, but these
numbers were artificial, targeting a BRAM that they did not contain.
Amusingly, synth_intel still does better when synthesizing PicoSoC
than Quartus when neither are inferring block RAM.
2019-07-23 18:11:11 +01:00
David Shah
80884d6f7b
ice40: Fix test_dsp_model.sh
...
Signed-off-by: David Shah <dave@ds0.me>
2019-07-19 17:33:57 +01:00
David Shah
79f14c7514
ice40/cells_sim.v: Fix sign of J and K partial products
...
Signed-off-by: David Shah <dave@ds0.me>
2019-07-19 17:33:41 +01:00
David Shah
3c84271543
ice40/cells_sim.v: LSB of A/B only signed in 8x8 mode
...
Signed-off-by: David Shah <dave@ds0.me>
2019-07-19 17:13:34 +01:00
Eddie Hung
171cd2ff73
Add tests for all combinations of A and B signedness for comb mul
2019-07-19 08:52:49 -07:00
Eddie Hung
f7753720fe
Don't copy ref if exists already
2019-07-19 08:45:35 -07:00
Eddie Hung
43616e1414
Update Makefile too
2019-07-18 14:51:55 -07:00
Eddie Hung
b97fe6e866
Work in progress for renaming labels/options in synth_xilinx
2019-07-18 14:20:43 -07:00
David Shah
9cb0456b6f
Merge pull request #1208 from ZirconiumX/intel_cleanups
...
Assorted synth_intel cleanups from @bwidawsk
2019-07-18 19:04:28 +01:00
Dan Ravensloft
0c999ac2c4
synth_intel: Use stringf
2019-07-18 19:02:23 +01:00
Dan Ravensloft
50f5e29724
synth_intel: s/not family/no family/
2019-07-18 17:28:21 +01:00
Ben Widawsky
999811572a
intel_synth: Fix help message
...
cyclonev has been a "supported" family since the initial commit. The old
commit message suggested to use a10gx which is incorrect.
Aside from the obvious lack of functional change due to this just being
a help message, users who were previously using "a10gx" for "cyclonev" will
also have no functional change by using "cyclonev" instead.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2019-07-18 17:06:25 +01:00
Ben Widawsky
f950a7a75d
intel_synth: Small code cleanup to remove if ladder
...
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2019-07-18 17:06:12 +01:00
Ben Widawsky
809b94a67b
intel_synth: Make family explicit and match
...
The help and code default to MAX10 for the family, however the couple of
if ladders defaulted to cycloneive. Fix this inconsistency and the next
patch will clean it up.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2019-07-18 17:06:03 +01:00
Ben Widawsky
060e77c09b
intel_synth: Minor code cleanups
...
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2019-07-18 17:05:54 +01:00
Dan Ravensloft
c78ab8ebc5
synth_intel: rename for consistency with #1184
...
Also fix a typo in the help message.
2019-07-18 16:46:21 +01:00
Clifford Wolf
e66e8fb59d
Merge pull request #1184 from whitequark/synth-better-labels
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synth_{ice40,ecp5}: more sensible pass label naming
2019-07-18 15:34:28 +02:00
David Shah
82153059a1
Merge pull request #1204 from smunaut/fix_1187
...
ice40: Adapt the relut process passes to the new $lut/SB_LUT4 port map
2019-07-17 07:55:26 +01:00
Sylvain Munaut
f28e38de99
ice40: Adapt the relut process passes to the new $lut <=> SB_LUT4 port map
...
The new mapping introduced in 437fec0d88
needed matching adaptation when converting and optimizing LUTs during
the relut process
Fixes #1187
(Diagnosis of the issue by @daveshah1 on IRC)
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2019-07-16 23:57:15 +02:00
whitequark
698ab9beee
synth_ecp5: rename dram to lutram everywhere.
2019-07-16 20:45:12 +00:00
whitequark
ba099bfe9b
synth_{ice40,ecp5}: more sensible pass label naming.
2019-07-16 20:41:51 +00:00
Eddie Hung
7a58ee78dc
gen_lut to return correctly sized LUT mask
2019-07-16 12:45:29 -07:00
Eddie Hung
ba8ccbdea8
Merge pull request #1186 from YosysHQ/eddie/abc9_ice40_fix
...
abc9/ice40: encapsulate SB_CARRY+SB_LUT4 into one box
2019-07-16 08:52:14 -07:00
Eddie Hung
5fb27c071b
$__ICE40_CARRY_LUT4 -> $__ICE40_FULL_ADDER as per @whitequark
2019-07-15 12:03:51 -07:00
Eddie Hung
d032198fac
ice40_opt to $__ICE40_CARRY_LUT4 into $lut not SB_LUT
2019-07-13 01:11:00 -07:00
Clifford Wolf
463f710066
Merge pull request #1183 from whitequark/ice40-always-relut
...
synth_ice40: switch -relut to be always on
2019-07-12 10:48:00 +02:00
Eddie Hung
7a912f22b2
Use Const::from_string() not its constructor...
2019-07-12 01:32:10 -07:00
Eddie Hung
28274dfb09
Off by one
2019-07-12 01:17:53 -07:00
Eddie Hung
e0e5d7d68e
Fix spacing
2019-07-12 01:15:22 -07:00
Eddie Hung
4de03bd5e6
Remove double push
2019-07-12 01:08:48 -07:00
Eddie Hung
62ac5ebd02
Map to and from this box if -abc9
2019-07-12 00:53:01 -07:00
Eddie Hung
0f5bddcd79
ice40_opt to handle this box and opt back to SB_LUT4
2019-07-12 00:52:31 -07:00
Eddie Hung
a79ff2501e
Add new box to cells_sim.v
2019-07-12 00:52:19 -07:00
Eddie Hung
c6e16e1334
_ABC macro will map and unmap to this new box
2019-07-12 00:51:37 -07:00
Eddie Hung
fc3d74616f
Combine SB_CARRY+SB_LUT into one $__ICE40_CARRY_LUT4 box
2019-07-12 00:50:42 -07:00
whitequark
b700a4b1c5
synth_ice40: switch -relut to be always on.
2019-07-11 20:18:41 +00:00
whitequark
a8c5f7f41e
synth_ice40: fix help text typo. NFC.
2019-07-11 20:18:41 +00:00
Eddie Hung
19c1c3cfa3
Merge pull request #1182 from koriakin/xc6s-bram
...
synth_xilinx: Initial Spartan 6 block RAM inference support.
2019-07-11 12:55:35 -07:00
Marcin Kościelnicki
a9efacd01d
xilinx: Fix the default values for FDPE/FDSE INIT attributes to match ISE/Vivado.
2019-07-11 21:13:12 +02:00
Marcin Kościelnicki
ce250b341c
synth_xilinx: Initial Spartan 6 block RAM inference support.
2019-07-11 14:45:48 +02:00
Eddie Hung
bb2144ae73
Merge pull request #1180 from YosysHQ/eddie/no_abc9_retime
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Error out if -abc9 and -retime specified
2019-07-10 14:38:13 -07:00
Eddie Hung
2f990a7319
Merge pull request #1148 from YosysHQ/xc7mux
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synth_xilinx to infer wide multiplexers using new '-widemux <min>' option
2019-07-10 14:38:00 -07:00
Eddie Hung
6bbd286e03
Error out if -abc9 and -retime specified
2019-07-10 12:47:48 -07:00
Eddie Hung
58bb84e5b2
Add some spacing
2019-07-10 12:32:33 -07:00
Eddie Hung
521971e32e
Add some ASCII art explaining mux decomposition
2019-07-10 12:20:04 -07:00
Eddie Hung
e573d024a2
Call muxpack and pmux2shiftx before cmp2lut
2019-07-09 21:26:38 -07:00
Eddie Hung
c55530b901
Restore opt_clean back to original place
2019-07-09 14:29:58 -07:00
Eddie Hung
5b48b18d29
Restore missing techmap -map +/cmp2lut.v with LUT_WIDTH=6
2019-07-09 14:28:54 -07:00
David Shah
27b27b8781
synth_ecp5: Fix typo in copyright header
...
Signed-off-by: David Shah <dave@ds0.me>
2019-07-09 22:26:10 +01:00
Eddie Hung
b1a048a703
Extend using A[1] to preserve don't care
2019-07-09 12:35:41 -07:00
Eddie Hung
93522b0ae1
Extend during mux decomposition with 1'bx
2019-07-09 10:59:37 -07:00
Eddie Hung
c864995343
Fix typo and comments
2019-07-09 10:38:07 -07:00
Eddie Hung
c91cb73562
Merge remote-tracking branch 'origin/master' into xc7mux
2019-07-09 10:22:49 -07:00
Eddie Hung
c68b909210
synth_xilinx to call commands of synth -coarse directly
2019-07-09 10:21:54 -07:00
Eddie Hung
737340327f
Revert "synth_xilinx to call "synth -run coarse" with "-keepdc""
...
This reverts commit 7f964859ec
.
2019-07-09 10:15:02 -07:00
Eddie Hung
713337255e
Revert "Add "synth -keepdc" option"
2019-07-09 10:14:23 -07:00
Eddie Hung
bc84f7dd10
Fix spacing
2019-07-09 09:22:12 -07:00
Eddie Hung
667199d460
Fix spacing
2019-07-09 09:16:00 -07:00
Clifford Wolf
a429aedc0f
Merge pull request #1167 from YosysHQ/eddie/xc7srl_cleanup
...
Cleanup synth_xilinx SRL inference, make more consistent
2019-07-09 16:49:08 +02:00
Eddie Hung
6951e32070
Decompose mux inputs in delay-orientated (rather than area) fashion
2019-07-08 23:51:13 -07:00
Eddie Hung
45da3ada7b
Do not call opt -mux_undef (part of -full) before muxcover
2019-07-08 23:49:16 -07:00
Eddie Hung
d4ab43d940
Add one more comment
2019-07-08 23:05:48 -07:00
Eddie Hung
939a225f92
Less thinking
2019-07-08 23:02:57 -07:00
Eddie Hung
de40453553
Reword
2019-07-08 22:56:19 -07:00
Eddie Hung
7f8c420cf7
Merge pull request #1166 from YosysHQ/eddie/synth_keepdc
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Add "synth -keepdc" option
2019-07-08 21:43:16 -07:00
Eddie Hung
7f964859ec
synth_xilinx to call "synth -run coarse" with "-keepdc"
2019-07-08 19:23:24 -07:00
Eddie Hung
9ac078be6f
Merge remote-tracking branch 'origin/eddie/synth_keepdc' into xc7mux
2019-07-08 19:21:53 -07:00
Eddie Hung
dd9771cbcd
Add synth -keepdc option
2019-07-08 19:14:54 -07:00
Eddie Hung
3f86407cc3
Map $__XILINX_SHIFTX in a more balanced manner
2019-07-08 17:06:35 -07:00
Eddie Hung
78914e2e0e
Capitalisation
2019-07-08 17:06:22 -07:00
Eddie Hung
baf47e496f
Add synth_xilinx -widemux recommended value
2019-07-08 17:04:39 -07:00
Eddie Hung
895ca50173
Fixes for 2:1 muxes
2019-07-08 12:03:38 -07:00
Eddie Hung
0944acf3af
synth_xilinx -widemux=2 is minimum now
2019-07-08 11:29:21 -07:00
Eddie Hung
dbe1326573
Parametric muxcover costs as per @daveshah1
2019-07-08 11:08:20 -07:00
Eddie Hung
c58998a7d2
atoi -> stoi as per @daveshah1
2019-07-08 10:48:10 -07:00
Dan Ravensloft
4f798cda9d
synth_intel: Warn about untested Quartus backend
2019-07-07 19:26:31 +01:00
Eddie Hung
810f8c5dbd
Merge branch 'eddie/script_from_wire' into eddie/xc7srl_cleanup
2019-07-02 09:21:02 -07:00
Eddie Hung
2ea6083b7e
Fix $__XILINX_MUXF78 box timing
2019-07-01 14:04:06 -07:00
Eddie Hung
09ac274716
Revert "Fix broken MUXFx box, use MUXF7x2 box instead"
...
This reverts commit a9a140aa6c
.
2019-07-01 14:01:09 -07:00
Eddie Hung
a9a140aa6c
Fix broken MUXFx box, use MUXF7x2 box instead
2019-07-01 13:36:27 -07:00
Eddie Hung
85f1c2dcbe
Cleanup SRL inference/make more consistent
2019-06-29 21:42:20 -07:00
Eddie Hung
62ba724ccb
Merge remote-tracking branch 'origin/master' into xc7mux
2019-06-29 19:39:27 -07:00
Eddie Hung
dd8d264bf5
install *_nowide.lut files
2019-06-29 19:37:04 -07:00
Eddie Hung
728839d6ca
Remove peepopt call in synth_xilinx since already in synth -run coarse
2019-06-28 12:53:38 -07:00
Eddie Hung
ea0f7c9be9
Restore $__XILINX_MUXF78 const optimisation
2019-06-28 12:12:41 -07:00
Eddie Hung
a193bf27c9
Clean up trimming leading 1'bx in A during techmappnig
2019-06-28 12:03:43 -07:00
Eddie Hung
cf020befeb
Fix CARRY4 abc_box_id
2019-06-28 11:28:50 -07:00
Eddie Hung
4ef26d4755
Merge remote-tracking branch 'origin/master' into xc7mux
2019-06-28 11:09:42 -07:00
Eddie Hung
03705f69f4
Update synth_ice40 -device doc to be relevant for -abc9 only
2019-06-28 09:49:01 -07:00
Eddie Hung
3f87575cb6
Disable boxing of ECP5 dist RAM due to regression
2019-06-28 09:46:36 -07:00
Eddie Hung
0318860b93
Add write address to abc_scc_break of ECP5 dist RAM
2019-06-28 09:45:48 -07:00
Eddie Hung
b9ddee0c87
Fix DO4 typo
2019-06-28 09:45:40 -07:00
Eddie Hung
00f63d82ce
Reduce diff with upstream
2019-06-27 16:13:22 -07:00
Eddie Hung
af8a5ae5fe
Extraneous newline
2019-06-27 16:12:20 -07:00
Eddie Hung
4daa746797
Remove noise from ice40/cells_sim.v
2019-06-27 16:11:39 -07:00
Eddie Hung
9398921af1
Refactor for one "abc_carry" attribute on module
2019-06-27 16:07:14 -07:00
Eddie Hung
312c03e4ca
Remove redundant doc
2019-06-27 15:28:55 -07:00
Eddie Hung
4d00e27ed7
Merge remote-tracking branch 'origin/xaig' into xc7mux
2019-06-27 11:23:30 -07:00
Eddie Hung
1237a4c116
Add warning if synth_xilinx -abc9 with family != xc7
2019-06-27 11:22:49 -07:00
Eddie Hung
6c256b8cda
Merge origin/master
2019-06-27 11:20:15 -07:00
Eddie Hung
593e4a30bb
MUXF78 -> $__MUXF78 to indicate internal
2019-06-26 20:09:28 -07:00
Eddie Hung
dbb8c8caaa
Merge remote-tracking branch 'origin/xaig' into xc7mux
2019-06-26 20:07:31 -07:00
Eddie Hung
4de25a1949
Add WE to ECP5 dist RAM's abc_scc_break too
2019-06-26 20:02:19 -07:00
Eddie Hung
a7a88109f5
Update comment on boxes
2019-06-26 20:00:15 -07:00
Eddie Hung
b7bef15b16
Add "WE" to dist RAM's abc_scc_break
2019-06-26 19:58:09 -07:00
Eddie Hung
b9ff0503f3
synth_xilinx's muxcover call to be very conservative -- -nodecode
2019-06-26 17:57:10 -07:00
Eddie Hung
f0a1726a1a
Accidentally removed "simplemap $mux"
2019-06-26 17:48:49 -07:00
Eddie Hung
2b104ed6c8
Replace with <internal options>
2019-06-26 17:42:50 -07:00
Eddie Hung
cae69a3edd
Rework help_mode for synth_xilinx -widemux
2019-06-26 17:41:21 -07:00
Eddie Hung
5f807a7a5b
Return to upstream synth_xilinx with opt -full and wreduce
2019-06-26 16:25:48 -07:00
Eddie Hung
812469aaa3
Merge remote-tracking branch 'origin/eddie/fix1132' into xc7mux
2019-06-26 14:48:35 -07:00
Eddie Hung
c762be5930
Instead of blocking wreduce on $mux, use -keepdc instead #1132
2019-06-26 11:48:35 -07:00
Eddie Hung
8d8261c71f
Do not call opt with -full before muxcover
2019-06-26 11:38:28 -07:00
Eddie Hung
80de03a7a6
Merge remote-tracking branch 'origin/xaig' into xc7mux
2019-06-26 11:24:39 -07:00
Eddie Hung
4d0014d1b1
Cleanup abc_box_id
2019-06-26 11:23:57 -07:00
Eddie Hung
612083a807
Merge remote-tracking branch 'origin/xaig' into xc7mux
2019-06-26 10:33:54 -07:00
Eddie Hung
5e1b8d458b
Remove unused var
2019-06-26 10:33:07 -07:00
Eddie Hung
988e6163ab
Add _nowide variants of LUT libraries in -nowidelut flows
2019-06-26 10:23:29 -07:00
Eddie Hung
741ebba70a
Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig
2019-06-26 10:10:16 -07:00
Eddie Hung
799b18263f
Merge branch 'koriakin/xc7nocarrymux' into xaig
2019-06-26 10:04:01 -07:00
Miodrag Milanovic
ea0b6258ab
Simulation model verilog fix
2019-06-26 18:34:34 +02:00
Eddie Hung
4ce329aefd
synth_ecp5 rename -nomux to -nowidelut, but preserve former
2019-06-26 09:33:48 -07:00
Eddie Hung
7389b043c0
Merge branch 'xc7nocarrymux' of https://github.com/koriakin/yosys into koriakin/xc7nocarrymux
2019-06-26 09:33:38 -07:00
Eddie Hung
177c26ca35
Rename -minmuxf to -widemux
2019-06-26 09:16:45 -07:00
Eddie Hung
184cfacfb5
Merge remote-tracking branch 'origin/xaig' into xc7mux
2019-06-26 09:15:28 -07:00
David Shah
0dd850e655
abc9: Add wire delays to synth_ice40
...
Signed-off-by: David Shah <dave@ds0.me>
2019-06-26 11:39:44 +01:00
whitequark
3d4102cfa4
Add more ECP5 Diamond flip-flops.
...
This includes all I/O registers, and a few more regular FFs where it
was convenient.
2019-06-26 01:57:29 +00:00
Eddie Hung
480a04cb3c
Realistic delays for RAM32X1D too
2019-06-25 09:34:28 -07:00
Eddie Hung
6095357390
Add RAM32X1D box info
2019-06-25 09:34:19 -07:00
Eddie Hung
6f36ec8ecf
Merge remote-tracking branch 'origin/master' into xaig
2019-06-25 09:33:11 -07:00
Eddie Hung
4238feed81
This optimisation doesn't seem to work...
2019-06-25 09:21:46 -07:00
Eddie Hung
158325956e
Realistic delays for RAM32X1D too
2019-06-24 23:05:28 -07:00
Eddie Hung
3825068a75
Merge remote-tracking branch 'origin/xaig' into xc7mux
2019-06-24 23:04:25 -07:00
Eddie Hung
2f770b7400
Use LUT delays for dist RAM delays
2019-06-24 23:02:53 -07:00
Eddie Hung
e1ba25d79f
Add RAM32X1D box info
2019-06-24 22:54:35 -07:00
Eddie Hung
1564eb8b54
Merge remote-tracking branch 'origin/xaig' into xc7mux
2019-06-24 22:48:49 -07:00
Eddie Hung
4fadb471a3
Re-enable dist RAM boxes for ECP5
2019-06-24 22:12:50 -07:00
Eddie Hung
a4a7e63d84
Revert "Re-enable dist RAM boxes for ECP5"
...
This reverts commit ca0225fcfa
.
2019-06-24 22:10:28 -07:00
Eddie Hung
ca0225fcfa
Re-enable dist RAM boxes for ECP5
2019-06-24 21:55:54 -07:00
Eddie Hung
152e682bd5
Add Xilinx dist RAM as comb boxes
2019-06-24 21:54:01 -07:00
Eddie Hung
f1675b88f6
Merge remote-tracking branch 'origin/eddie/ram32x1d' into xc7mux
2019-06-24 16:39:18 -07:00
Eddie Hung
efd04880db
Add RAM32X1D support
2019-06-24 16:16:50 -07:00
Eddie Hung
c3df895bf4
Reduce MuxFx resources in mux techmapping
2019-06-24 15:16:44 -07:00
Eddie Hung
db6a0b72b2
Reduce number of decomposed muxes during techmap
2019-06-24 14:28:56 -07:00
Eddie Hung
2e7992efff
Revert "Fix techmapping muxes some more"
...
This reverts commit 0aae3b4f43
.
2019-06-24 14:15:31 -07:00
Eddie Hung
7fbfcf20d1
Move comment
2019-06-24 14:15:00 -07:00
Eddie Hung
0aae3b4f43
Fix techmapping muxes some more
2019-06-24 12:50:48 -07:00
Eddie Hung
2b4501503d
Fix mux techmapping
2019-06-24 12:18:17 -07:00
Eddie Hung
aa1eeda567
Modify costs for muxcover
2019-06-24 11:51:55 -07:00
Eddie Hung
36e6da5396
Change synth_xilinx's -nomux to -minmuxf <int>
2019-06-24 10:04:01 -07:00