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Author SHA1 Message Date
Miodrag Milanovic dc75ed7dac Add one mode dependency 2020-03-19 16:53:40 +01:00
N. Engelhardt b473264a06
Merge pull request #1775 from huaixv/asserts_locations 
Add precise locations for asserts
 2020-03-19 13:12:18 +01:00
huaixv cd82ccd258 Add precise locations for asserts 2020-03-19 10:22:07 +08:00
Alberto Gonzalez 6dd2024965
Add AST node source location information in a couple more parser rules. 2020-03-17 06:22:12 +00:00
Miodrag Milanović 569e834df2
Merge pull request #1759 from zeldin/constant_with_comment_redux 
refixed parsing of constant with comment between size and value
 2020-03-14 13:34:59 +02:00
Marcus Comstedt 5e94bf0291 refixed parsing of constant with comment between size and value 
The three parts of a based constant (size, base, digits) are now three
separate tokens, allowing the linear whitespace (including comments)
between them to be treated as normal inter-token whitespace.
 2020-03-11 18:21:44 +01:00
Eddie Hung 2d63bf5877 verilog: also set location for simple_behavioral_stmt 2020-03-10 10:29:24 -07:00
Alberto Gonzalez da8270aa01
Set AST source locations in more parser rules. 2020-03-10 01:50:39 +00:00
Claire Wolf a7cc4673c3 Fix partsel expr bit width handling and add test case 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-03-08 16:12:12 +01:00
Claire Wolf d59da5a4e4 Fix bison warning for "pure-parser" option 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-03-03 08:41:55 -08:00
Alberto Gonzalez f0afd65035
Closes #1717. Add more precise Verilog source location information to AST and RTLIL nodes. 2020-02-23 07:22:26 +00:00
Eddie Hung 760096e8d2
Merge pull request #1703 from YosysHQ/eddie/specify_improve 
Improve specify parser
 2020-02-21 09:15:17 -08:00
Claire Wolf cd044a2bb6
Merge pull request #1642 from jjj11x/jjj11x/sv-enum 
Enum support
 2020-02-20 18:17:25 +01:00
Eddie Hung ea4bd161b6 verilog: add support for more delays than just rise/fall 2020-02-19 11:09:37 -08:00
Jeff Wang d12ba42a74 add attributes for enumerated values in ilang 
- information also useful for strongly-typed enums (not implemented)
- resolves enum values in ilang part of #1594
- still need to output enums to VCD (or better yet FST) files
 2020-02-17 04:42:42 -05:00
Eddie Hung d20c1dac73 verilog: ignore ranges too without -specify 2020-02-13 17:58:43 -08:00
Eddie Hung 6b58c1820c verilog: improve specify support when not in -specify mode 2020-02-13 13:27:15 -08:00
Eddie Hung 2e51dc1856 verilog: ignore '&&&' when not in -specify mode 2020-02-13 13:06:13 -08:00
Eddie Hung b523ecf2f4 specify: system timing checks to accept min:typ:max triple 2020-02-13 12:42:15 -08:00
N. Engelhardt e069259a53
Merge pull request #1679 from thasti/delay-parsing 
Fix crash on wire declaration with delay
 2020-02-13 12:01:27 +01:00
Stefan Biereigel b844b078db correct wire declaration grammar for #1614 2020-02-03 21:29:40 +01:00
David Shah 4bfd2ef4f3 sv: Improve handling of wildcard port connections 
Signed-off-by: David Shah <dave@ds0.me>
 2020-02-02 16:12:33 +00:00
David Shah 5df591c023 hierarchy: Resolve SV wildcard port connections 
Signed-off-by: David Shah <dave@ds0.me>
 2020-02-02 16:12:33 +00:00
David Shah 50f86c11b2 sv: Add lexing and parsing of .* (wildcard port conns) 
Signed-off-by: David Shah <dave@ds0.me>
 2020-02-02 16:12:33 +00:00
Jeff Wang cc2236d0c0 lexer doesn't seem to return TOK_REG for logic anymore 2020-01-16 18:08:58 -05:00
Jeff Wang 5ddf84d430 allow enum typedefs 2020-01-16 17:17:42 -05:00
Jeff Wang 16ea4ea61a partial rebase of PeterCrozier's enum work onto current master 
I tried to keep only the enum-related changes, and minimize the diff. (The
original commit also had a lot of work done to get typedefs working, but yosys
has diverged quite a bit since the 2018-03-09 commit, with a new typedef
implementation.) I did not include the import related changes either.

Original commit:
"Initial implementation of enum, typedef, import.  Still a WIP."
881833aa73
 2020-01-16 13:51:47 -05:00
Rodrigo Alejandro Melo e9dc2759c4 Fixed some missing "verilog_" in documentation 2019-12-13 10:17:05 -03:00
whitequark e97e33d00d kernel: require \B_SIGNED=0 on $shl, $sshl, $shr, $sshr. 
Before this commit, these cells would accept any \B_SIGNED and in
case of \B_SIGNED=1, would still treat the \B input as unsigned.

Also fix the Verilog frontend to never emit such constructs.
 2019-12-04 11:59:36 +00:00
David Shah 9e4801cca7 sv: Correct parsing of always_comb, always_ff and always_latch 
Signed-off-by: David Shah <dave@ds0.me>
 2019-11-21 20:27:19 +00:00
Clifford Wolf 65f197e28f Add check for valid macro names in macro definitions 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-11-07 13:30:03 +01:00
Clifford Wolf 5025aab8c9 Add "verilog_defines -list" and "verilog_defines -reset" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-10-21 13:35:56 +02:00
Clifford Wolf e84cedfae4 Use "(id)" instead of "id" for types as temporary hack 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-10-14 05:24:31 +02:00
David Shah 8cc1bee33c sv: Disambiguate interface ports 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-03 09:54:45 +01:00
David Shah c0bb47beca sv: Fix memories of typedefs 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-03 09:54:14 +01:00
David Shah 497faf4ec0 sv: Add %expect 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-03 09:54:14 +01:00
David Shah 30d2326030 sv: Add support for memory typedefs 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-03 09:54:14 +01:00
David Shah c962951612 sv: Fix typedef parameters 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-03 09:54:14 +01:00
David Shah f6b5e47e40 sv: Switch parser to glr, prep for typedef 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-03 09:54:14 +01:00
Clifford Wolf a67d63714b Fix handling of z_digit "?" and fix optimization of cmp with "z" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-09-13 13:39:39 +02:00
Clifford Wolf 855e6a9b91 Fix lexing of integer literals without radix 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-09-13 10:19:58 +02:00
Clifford Wolf 7eb593829f Fix lexing of integer literals, fixes #1364 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-09-12 09:43:32 +02:00
Eddie Hung 6d77236f38 substr() -> compare() 2019-08-07 12:20:08 -07:00
Eddie Hung 7164996921 RTLIL::S{0,1} -> State::S{0,1} 2019-08-07 11:12:38 -07:00
David Shah 92694ea3a9 verilog_lexer: Increase YY_BUF_SIZE to 65536 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-26 13:35:39 +01:00
Clifford Wolf e38b2ac648
Merge pull request #1147 from YosysHQ/clifford/fix1144 
Improve specify dummy parser
 2019-07-03 12:30:37 +02:00
Clifford Wolf ba36567908 Some cleanups in "ignore specify parser" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-07-03 11:22:10 +02:00
Clifford Wolf d206eca03b Fix read_verilog assert/assume/etc on default case label, fixes YosysHQ/SymbiYosys#53 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-07-02 11:36:26 +02:00
Clifford Wolf af74409749 Improve specify dummy parser, fixes #1144 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-28 10:21:16 +02:00
Clifford Wolf f6053b8810 Fix segfault on failed VERILOG_FRONTEND::const2ast, closes #1131 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-26 11:09:43 +02:00
Clifford Wolf 78e7a6f6f2
Merge pull request #1119 from YosysHQ/eddie/fix1118 
Make genvar a signed type
 2019-06-21 10:13:13 +02:00
Eddie Hung c27ab609fa Make genvar a signed type 2019-06-20 16:04:12 -07:00
Eddie Hung 20119ee50e Maintain "is_unsized" state of constants 2019-06-20 12:43:39 -07:00
Clifford Wolf 2428fb7dc2 Merge branch 'unpacked_arrays' of https://github.com/towoe/yosys-sv into towoe-unpacked_arrays 2019-06-20 12:03:00 +02:00
Clifford Wolf ec4565009a Add "read_verilog -pwires" feature, closes #1106 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-19 14:38:50 +02:00
Tobias Wölfel 8b8af10f5e Unpacked array declaration using size 
Allows fixed-sized array dimension specified by a single number.

This commit is based on the work from PeterCrozier
https://github.com/YosysHQ/yosys/pull/560.
But is split out of the original work.
 2019-06-19 12:47:48 +02:00
Clifford Wolf 8d0cd529c9 Add defaultvalue attribute 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-19 11:37:11 +02:00
Clifford Wolf 6d64e242ba Fix handling of "logic" variables with initial value 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-19 11:25:11 +02:00
Udi Finkelstein 4b56f6646d Fixed brojen $error()/$info/$warning() on non-generate blocks 
(within always/initial blocks)
 2019-06-11 02:52:06 +03:00
Clifford Wolf a3bbc5365b Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into clifford/pr983 2019-06-07 12:08:42 +02:00
Clifford Wolf a0b57f2a6f Cleanup tux3-implicit_named_connection 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-07 11:46:16 +02:00
Clifford Wolf b637b3109d Merge branch 'implicit_named_connection' of https://github.com/tux3/yosys into tux3-implicit_named_connection 2019-06-07 11:41:54 +02:00
tux3 88f5977093 SystemVerilog support for implicit named port connections 
This is the `foo foo(.port1, .port2);` SystemVerilog syntax
introduced in IEEE1800-2005.
 2019-06-06 18:07:49 +02:00
Maciej Kurc 03e0d3a17c Fixed memory leak. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-06-05 10:42:43 +02:00
Maciej Kurc a6cadf6318 Added support for parsing attributes on port connections. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-05-31 14:58:43 +02:00
Stefan Biereigel 816082d5a1
Merge branch 'master' into wandwor 2019-05-27 19:07:46 +02:00
Miodrag Milanovic 34417ce55f Added support for unsized constants, fixes #1022 
Includes work from @sumit0190 and @AaronKel
 2019-05-27 11:42:10 +02:00
Stefan Biereigel fd003e0e97 fix indentation across files 2019-05-23 13:57:27 +02:00
Stefan Biereigel 9df04d7e75 make lexer/parser aware of wand/wor net types 2019-05-23 13:57:27 +02:00
Kaj Tuomi 48ddbe52fb Read bigger Verilog files. 
Hit parser limit with 3M gate design. This commit fix it.
 2019-05-18 14:20:30 +03:00
Clifford Wolf b6345b111d
Merge pull request #1013 from antmicro/parameter_attributes 
Support for attributes on parameters and localparams for Verilog frontend
 2019-05-16 14:21:18 +02:00
Maciej Kurc ce4a0954bc Added support for parsing attributes on parameters in Verilog frontent. Content of those attributes is ignored. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-05-16 12:44:16 +02:00
Henner Zeller 8eb2798776 Make the generated *.tab.hh include all the headers needed to define the union. 2019-05-14 21:07:26 -07:00
Clifford Wolf 752553d8e9
Merge pull request #946 from YosysHQ/clifford/specify 
Add specify parser
 2019-05-06 20:57:15 +02:00
Clifford Wolf c7f2e93024 Merge branch 'master' of github.com:YosysHQ/yosys into clifford/specify 2019-05-06 11:46:10 +02:00
Ben Widawsky a98069d762 verilog_parser: Fix Bison warning 
As of Bison 2.6, name-prefix is deprecated. This fixes
frontends/verilog/verilog_parser.y:99.1-34: warning: deprecated directive, use ‘%define api.prefix {frontend_verilog_yy}’ [-Wdeprecated]
 %name-prefix "frontend_verilog_yy"

For details: https://www.gnu.org/software/bison/manual/html_node/Multiple-Parsers.html

Compile tested only.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
 2019-05-05 19:36:27 -07:00
Clifford Wolf 70d0f389ad
Merge pull request #988 from YosysHQ/clifford/fix987 
Add approximate support for SV "var" keyword
 2019-05-04 21:58:25 +02:00
Clifford Wolf 66d6ca2de2 Add support for SVA "final" keyword 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-04 09:25:32 +02:00
Clifford Wolf 9804c86e87 Add approximate support for SV "var" keyword, fixes #987 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-04 07:52:51 +02:00
Eddie Hung d9c4644e88 Merge remote-tracking branch 'origin/master' into clifford/specify 2019-05-03 15:05:57 -07:00
Udi Finkelstein ac10e7d96d Initial implementation of elaboration system tasks 
(IEEE1800-2017 section 20.11)
This PR allows us to use $info/$warning/$error/$fatal **at elaboration time** within a generate block.
This is very useful to stop a synthesis of a parametrized block when an
illegal combination of parameters is chosen.
 2019-05-03 03:10:43 +03:00
Clifford Wolf 84f3a796e1 Include filename in "Executing Verilog-2005 frontend" message, fixes #959 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-30 15:37:46 +02:00
Clifford Wolf 64925b4e8f Improve $specrule interface 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-23 22:57:10 +02:00
Clifford Wolf 4575e4ad86 Improve $specrule interface 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-23 22:18:04 +02:00
Clifford Wolf 71c38d9de5 Add $specrule cells for $setup/$hold/$skew specify rules 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-23 21:36:59 +02:00
Clifford Wolf e807e88b60 Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std nomenclature 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-23 21:36:59 +02:00
Clifford Wolf 41b843c27b Un-break default specify parser 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-23 21:36:59 +02:00
Clifford Wolf 3cc95fb4be Add specify parser 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-23 21:36:59 +02:00
Clifford Wolf fb7f02be55 New behavior for front-end handling of whiteboxes 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-20 22:24:50 +02:00
Clifford Wolf f4abc21d8a Add "whitebox" attribute, add "read_verilog -wb" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-18 17:45:47 +02:00
Clifford Wolf 584d2030bf Build Verilog parser with -DYYMAXDEPTH=100000, fixes #906 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-29 16:32:44 +01:00
Clifford Wolf 9b0e7af6d7 Improve read_verilog debug output capabilities 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-21 20:52:29 +01:00
Clifford Wolf b02d9c2634 Fix handling of cases that look like sva labels, fixes #862 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-10 16:27:18 -07:00
Clifford Wolf e7a34d342e Also add support for labels on sva module items, fixes #699 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-08 22:55:09 -08:00
Clifford Wolf 22ff60850e Add support for SVA labels in read_verilog 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-07 11:17:32 -08:00
Clifford Wolf 17ceab92a9 Bugfix in Verilog string handling 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-01-05 12:10:24 +01:00
whitequark efa278e232 Fix typographical and grammatical errors and inconsistencies. 
The initial list of hits was generated with the codespell command
below, and each hit was evaluated and fixed manually while taking
context into consideration.

    DIRS="kernel/ frontends/ backends/ passes/ techlibs/"
    DIRS="${DIRS} libs/ezsat/ libs/subcircuit"
    codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint

More hits were found by looking through comments and strings manually.
 2019-01-02 13:12:17 +00:00
Sylvain Munaut 58fb2ac818 verilog_parser: Properly handle recursion when processing attributes 
Fixes #737

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-12-14 12:48:00 +01:00
Clifford Wolf 36ea98385f Add warning for SV "restrict" without "property" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-04 15:57:17 +01:00
Clifford Wolf 5ab58d4930 Fix minor typo in error message 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-10-25 13:20:00 +02:00
Udi Finkelstein 536ae16c3a Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique, 
meaningful info on the error.
Also add 13 compilation examples that triggers each of these messages.
 2018-10-25 02:37:56 +03:00
Clifford Wolf f24bc1ed0a
Merge pull request #659 from rubund/sv_interfaces 
Support for SystemVerilog interfaces and modports
 2018-10-18 10:58:47 +02:00
argama 097da32e1a ignore protect endprotect 2018-10-16 21:33:37 +08:00
Ruben Undheim 736105b046 Handle FIXME for modport members without type directly in front 2018-10-13 20:50:33 +02:00
Ruben Undheim 458a94059e Support for 'modports' for System Verilog interfaces 2018-10-12 21:11:48 +02:00
Ruben Undheim 75009ada3c Synthesis support for SystemVerilog interfaces 
This time doing the changes mostly in AST before RTLIL generation
 2018-10-12 21:11:36 +02:00
Clifford Wolf 8fde05dfa5 Add "read_verilog -noassert -noassume -assert-assumes" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-09-24 20:51:16 +02:00
Clifford Wolf eb452ffb28 Added support for ommited "parameter" in Verilog-2001 style parameter decl in SV mode 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-09-23 10:32:54 +02:00
Clifford Wolf ddc1761f1a Add "make coverage" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-27 14:22:21 +02:00
Clifford Wolf 4d269f9b25
Merge pull request #610 from udif/udif_specify_round2 
More specify/endspecify fixes
 2018-08-23 14:43:25 +02:00
Udi Finkelstein 042b3074f8 Added -no_dump_ptr flag for AST dump options in 'read_verilog' 
This option disables the memory pointer display.
This is useful when diff'ing different dumps because otherwise the node pointers
makes every diff line different when the AST content is the same.
 2018-08-23 15:26:02 +03:00
Udi Finkelstein fbfc677df3 Fixed all known specify/endspecify issues, without breaking 'make test'. 
Some the of parser fixes may look strange but they were needed to avoid shift/reduce conflicts,
due to the explicit parentheses in path_delay_value, and the mintypmax values without parentheses
 2018-08-20 17:27:45 +03:00
Udi Finkelstein 95241c8f4d Yosys can now parse https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/master/vtr_flow/primitives.v , 
(specify block ignored).
Must use 'read_verilog -defer' due to a parameter not assigned a default value.
 2018-08-20 00:08:08 +03:00
Udi Finkelstein 28cfc75a90 A few minor enhancements to specify block parsing. 
Just remember specify blocks are parsed but ignored.
 2018-08-15 20:14:52 +03:00
Clifford Wolf 67b1026297
Merge pull request #591 from hzeller/virtual-override 
Consistent use of 'override' for virtual methods in derived classes.
 2018-08-15 14:05:38 +02:00
Clifford Wolf 3d27c1cc80
Merge pull request #513 from udif/pr_reg_wire_error 
Add error checking for reg/wire/logic misuse - PR now passes 'make test' (plus a new test)
 2018-08-15 13:35:41 +02:00
Clifford Wolf d71529baa1
Merge pull request #562 from udif/pr_fix_illegal_port_decl 
Detect illegal port declaration, e.g input/output/inout keyword must …
 2018-08-15 13:14:23 +02:00
Henner Zeller 3aa4484a3c Consistent use of 'override' for virtual methods in derived classes. 
o Not all derived methods were marked 'override', but it is a great
  feature of C++11 that we should make use of.
o While at it: touched header files got a -*- c++ -*- for emacs to
  provide support for that language.
o use YS_OVERRIDE for all override keywords (though we should probably
  use the plain keyword going forward now that C++11 is established)
 2018-07-20 23:51:06 -07:00
Henner Zeller 68b5d0c3b1 Convert more log_error() to log_file_error() where possible. 
Mostly statements that span over multiple lines and haven't been
caught with the previous conversion.
 2018-07-20 09:37:44 -07:00
Henner Zeller b5ea598ef6 Use log_file_warning(), log_file_error() functions. 
Wherever we can report a source-level location.
 2018-07-20 08:19:06 -07:00
Udi Finkelstein 8b7580b0a1 Detect illegal port declaration, e.g input/output/inout keyword must be the first. 2018-06-06 22:27:25 +03:00
Udi Finkelstein 73d426bc87 Modified errors into warnings 
No longer false warnings for memories and assertions
 2018-06-05 18:03:22 +03:00
Jim Paris 4a229e5b95 Support SystemVerilog `` extension for macros 2018-05-17 00:09:56 -04:00
Jim Paris 872d8d49e9 Skip spaces around macro arguments 2018-05-17 00:06:49 -04:00
Clifford Wolf a572b49538 Replace -ignore_redef with -[no]overwrite 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-03 15:25:59 +02:00
Dan Gisselquist e060375f23 Support more character literals 2018-05-03 12:35:01 +02:00
Clifford Wolf 2d7f3123f0 Add statement labels for immediate assertions 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-04-13 11:52:28 +02:00
Clifford Wolf 66ffc99695 Allow "property" in immediate assertions 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-04-12 14:28:28 +02:00
Clifford Wolf 5ea2c53604 Add read_verilog anyseq/anyconst/allseq/allconst attribute support 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-04-06 14:35:11 +02:00
Udi Finkelstein 6378e2cd46 First draft of Verilog parser support for specify blocks and parameters. 
The only functionality of this code at the moment is to accept correct specify syntax and ignore it.
No part of the specify block is added to the AST
 2018-03-27 14:34:00 +02:00
Udi Finkelstein 2b9c75f8e3 This PR should be the base for discussion, do not merge it yet! 
It correctly detects reg/wire mix and incorrect use on blocking,nonblocking assignments within blocks and assign statements.

What it DOES'T do:
Detect registers connected to output ports of instances.

Where it FAILS:
memorty nonblocking assignments causes spurious (I assume??) errors on yosys-generated "_ADDR", "_DATA", "EN" signals.

You can test it with tests/simple/reg_wire_error.v (look inside for the comments to enable/disable specific lines)
 2018-03-11 23:09:34 +02:00
Clifford Wolf eb67a7532b Add $allconst and $allseq cell types 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-02-23 13:14:47 +01:00
Clifford Wolf a96c775a73 Add support for "yosys -E" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-01-07 16:36:13 +01:00
Clifford Wolf 34005348b6 Bugfix in verilog_defaults argument parser 2017-12-24 17:21:37 +01:00
Clifford Wolf 777f2881d8 Add Verilog "automatic" keyword (ignored in synthesis) 2017-11-23 08:51:38 +01:00
Clifford Wolf 5b6e52118c Accept real-valued delay values 2017-11-18 10:01:30 +01:00
William D. Jones abc5b4b8ce Accommodate Windows-style paths during include-file processing. 2017-11-14 16:16:24 -05:00
Udi Finkelstein 72a08eca3d Resolved classical Bison IF/THEN/ELSE shift/reduce conflict using the textbook solution 
(Oreilly 'Flex & Bison' page 189)
 2017-09-30 06:39:07 +03:00
Clifford Wolf 2c04d883b1 Minor coding style fix 2017-09-26 13:50:14 +02:00
Clifford Wolf cb1d439d10 Merge branch 'master' of https://github.com/combinatorylogic/yosys into combinatorylogic-master 2017-09-26 13:48:13 +02:00
Clifford Wolf 2cc09161ff Fix ignoring of simulation timings so that invalid module parameters cause syntax errors 2017-09-26 01:52:59 +02:00
combinatorylogic 64ca0be971 Adding support for string macros and macros with arguments after include 2017-09-21 18:25:02 +01:00
Clifford Wolf 26766da343 Add a paragraph about pre-defined macros to read_verilog help message 2017-07-21 14:34:53 +02:00
Clifford Wolf 8f8baccfde Fix generation of vlogtb output in yosys-smtbmc for "rand reg" and "rand const reg" 2017-06-07 12:30:24 +02:00
Clifford Wolf 129984e115 Fix handling of Verilog ~& and ~| operators 2017-06-01 12:43:21 +02:00
Clifford Wolf e91548b33e Add support for localparam in module header 2017-04-30 17:20:30 +02:00
Clifford Wolf f0db8ffdbc Add support for `resetall compiler directive 2017-04-26 16:09:41 +02:00
Clifford Wolf 088f9c9cab Fix verilog pre-processor for multi-level relative includes 2017-03-14 17:30:20 +01:00
Clifford Wolf 5b3b5ffc8c Allow $anyconst, etc. in non-formal SV mode 2017-03-01 10:47:05 +01:00
Clifford Wolf 5f1d0b1024 Add $live and $fair cell types, add support for s_eventually keyword 2017-02-25 10:36:39 +01:00
Clifford Wolf 00dba4c197 Add support for SystemVerilog unique, unique0, and priority case 2017-02-23 16:33:19 +01:00
Clifford Wolf 34d4e72132 Added SystemVerilog support for ++ and -- 2017-02-23 11:21:33 +01:00
Clifford Wolf 848062088c Add checker support to verilog front-end 2017-02-09 13:51:44 +01:00
Clifford Wolf ef4a28e112 Add SV "rand" and "const rand" support 2017-02-08 14:38:15 +01:00
Clifford Wolf 6abf79eb28 Further improve cover() support 2017-02-04 17:02:13 +01:00
Clifford Wolf 3928482a3c Add $cover cell type and SVA cover() support 2017-02-04 14:14:26 +01:00
Clifford Wolf fea528280b Add "enum" and "typedef" lexer support 2017-01-17 17:33:52 +01:00
Clifford Wolf 3886669ab6 Added "verilog_defines" command 2016-12-15 17:49:28 +01:00
Clifford Wolf ecdc22b06c Added support for macros as include file names 2016-11-28 14:50:17 +01:00
Clifford Wolf c7f6fb6e17 Bugfix in "read_verilog -D NAME=VAL" handling 2016-11-28 14:45:05 +01:00
Clifford Wolf 70d7a02cae Added support for hierarchical defparams 2016-11-15 13:35:19 +01:00
Clifford Wolf a926a6afc2 Remember global declarations and defines accross read_verilog calls 2016-11-15 12:42:43 +01:00
Clifford Wolf bdc316db50 Added $anyseq cell type 2016-10-14 15:24:03 +02:00
Clifford Wolf 6f41e5277d Removed $aconst cell type 2016-08-30 19:09:56 +02:00
Clifford Wolf eae390ae17 Removed $predict again 2016-08-28 21:35:33 +02:00
Clifford Wolf 1276c87a56 Added read_verilog -norestrict -assume-asserts 2016-08-26 23:35:27 +02:00
Clifford Wolf 4be4969bae Improved verilog parser errors 2016-08-25 11:44:37 +02:00
Clifford Wolf cd18235f30 Added SV "restrict" keyword 2016-08-24 15:30:08 +02:00
Clifford Wolf 7f755dec75 Fixed bug in parsing real constants 2016-08-06 13:16:23 +02:00
Clifford Wolf 4056312987 Added $anyconst and $aconst 2016-07-27 15:41:22 +02:00
Clifford Wolf a7b0769623 Added "read_verilog -dump_rtlil" 2016-07-27 15:40:17 +02:00
Clifford Wolf 5b944ef11b Fixed a verilog parser memory leak 2016-07-25 16:37:58 +02:00
Clifford Wolf 7a67add95d Fixed parsing of empty positional cell ports 2016-07-25 12:48:03 +02:00
Clifford Wolf 9aae1d1e8f No tristate warning message for "read_verilog -lib" 2016-07-23 11:56:53 +02:00
Clifford Wolf 5c166e76e5 Added $initstate cell type and vlog function 2016-07-21 14:23:22 +02:00
Clifford Wolf d7763634b6 After reading the SV spec, using non-standard predict() instead of expect() 2016-07-21 13:34:33 +02:00
Clifford Wolf 721f1f5ecf Added basic support for $expect cells 2016-07-13 16:56:17 +02:00
Ruben Undheim 545bcb37e8 Allow defining input ports as "input logic" in SystemVerilog 2016-06-20 20:16:37 +02:00
Ruben Undheim 178ff3e7f6 Added support for SystemVerilog packages with localparam definitions 2016-06-18 10:53:55 +02:00
Clifford Wolf 060bf4819a Small improvements in Verilog front-end docs 2016-05-20 16:21:35 +02:00
Clifford Wolf 0bc95f1e04 Added "yosys -D" feature 2016-04-21 23:28:37 +02:00
Clifford Wolf 5a09fa4553 Fixed handling of parameters and const functions in casex/casez pattern 2016-04-21 15:31:54 +02:00
Clifford Wolf 33c10350b2 Fixed Verilog parser fix and more similar improvements 2016-03-15 12:22:31 +01:00
Andrew Becker 81d4e9e7c1 Use left-recursive rule for cell_port_list in Verilog parser. 2016-03-15 12:03:40 +01:00
Clifford Wolf 35a6ad4cc1 Fixed typos in verilog_defaults help message 2016-03-10 11:14:51 +01:00
Clifford Wolf 34f2b84fb6 Fixed handling of parameters and localparams in functions 2015-11-11 10:54:35 +01:00
Clifford Wolf 5308c1e02a Fixed bug in verilog parser 2015-10-15 15:19:23 +02:00
Clifford Wolf f13e387321 SystemVerilog also has assume(), added implicit -D FORMAL 2015-10-13 14:21:20 +02:00
Clifford Wolf ba4cce9f19 Added support for "parameter" and "localparam" in global context 2015-10-07 14:59:08 +02:00
Clifford Wolf e2e092b144 Added read_verilog -nodpi 2015-09-23 08:23:38 +02:00
Clifford Wolf b845b77f86 Fixed support for $write system task 2015-09-23 07:10:56 +02:00
Clifford Wolf a3a13cce32 Fixed detection of "task foo(bar);" syntax error 2015-09-22 21:34:21 +02:00
Clifford Wolf 4b8200eb49 Fixed segfault on invalid verilog constant 1'b_ 2015-09-22 08:13:09 +02:00
Clifford Wolf a7ab9172f9 Small corrections to const2ast warning messages 2015-08-17 16:22:53 +02:00
Florian Zeitz 0491042849 Check base-n literals only contain valid digits 2015-08-17 15:37:33 +02:00
Florian Zeitz 64ccbf8510 Warn on literals exceeding the specified bit width 2015-08-17 15:27:35 +02:00
Larry Doolittle 6c00704a5e Another block of spelling fixes 
Smaller this time
 2015-08-14 23:27:05 +02:00
Clifford Wolf 0350074819 Re-created command-reference-manual.tex, copied some doc fixes to online help 2015-08-14 11:27:19 +02:00
Clifford Wolf 84bf862f7c Spell check (by Larry Doolittle) 2015-08-14 10:56:05 +02:00
Clifford Wolf e4ef000b70 Adjust makefiles to work with out-of-tree builds 
This is based on work done by Larry Doolittle
 2015-08-12 15:04:44 +02:00