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Merge pull request #1013 from antmicro/parameter_attributes 

Support for attributes on parameters and localparams for Verilog frontend
This commit is contained in:
Clifford Wolf 2019-05-16 14:21:18 +02:00 committed by GitHub
parent c9def5407c 1f52332b8d
commit b6345b111d
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GPG Key ID: 4AEE18F83AFDEB23
3 changed files with 24 additions and 2 deletions
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4
frontends/verilog/verilog_parser.y
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@ -1202,7 +1202,7 @@ param_range:
};
param_decl:
TOK_PARAMETER {
attr TOK_PARAMETER {
astbuf1 = new AstNode(AST_PARAMETER);
astbuf1->children.push_back(AstNode::mkconst_int(0, true));
} param_signed param_integer param_real param_range param_decl_list ';' {
@ -1210,7 +1210,7 @@ param_decl:
};
localparam_decl:
TOK_LOCALPARAM {
attr TOK_LOCALPARAM {
astbuf1 = new AstNode(AST_LOCALPARAM);
astbuf1->children.push_back(AstNode::mkconst_int(0, true));
} param_signed param_integer param_real param_range param_decl_list ';' {

11
tests/simple/localparam_attr.v Normal file
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@ -0,0 +1,11 @@
module uut_localparam_attr (I, O);
(* LOCALPARAM_ATTRIBUTE = "attribute_content" *)
localparam WIDTH = 1;
input wire [WIDTH-1:0] I;
output wire [WIDTH-1:0] O;
assign O = I;
endmodule

11
tests/simple/param_attr.v Normal file
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@ -0,0 +1,11 @@
module uut_param_attr (I, O);
(* PARAMETER_ATTRIBUTE = "attribute_content" *)
parameter WIDTH = 1;
input wire [WIDTH-1:0] I;
output wire [WIDTH-1:0] O;
assign O = I;
endmodule