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Added support for parsing attributes on parameters in Verilog frontent. Content of those attributes is ignored. 

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
This commit is contained in:
Maciej Kurc 2019-05-16 12:44:16 +02:00
parent 3ef88ffbb2
commit ce4a0954bc
1 changed files with 2 additions and 2 deletions
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4
frontends/verilog/verilog_parser.y
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@ -1193,7 +1193,7 @@ param_range:
};
param_decl:
TOK_PARAMETER {
attr TOK_PARAMETER {
astbuf1 = new AstNode(AST_PARAMETER);
astbuf1->children.push_back(AstNode::mkconst_int(0, true));
} param_signed param_integer param_real param_range param_decl_list ';' {
@ -1201,7 +1201,7 @@ param_decl:
};
localparam_decl:
TOK_LOCALPARAM {
attr TOK_LOCALPARAM {
astbuf1 = new AstNode(AST_LOCALPARAM);
astbuf1->children.push_back(AstNode::mkconst_int(0, true));
} param_signed param_integer param_real param_range param_decl_list ';' {