clairexen
a9681f4e06
Merge pull request #2317 from zachjs/expand-genblock
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Fix generate scoping issues
2020-08-18 17:37:11 +02:00
Claire Wolf
7f767bf2b7
Merge branch 'const-func-block-var' of https://github.com/zachjs/yosys into zachjs-const-func-block-var
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-08-18 17:29:49 +02:00
clairexen
5ee9349647
Merge pull request #2281 from zachjs/const-real
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Allow reals as constant function parameters
2020-08-18 17:22:20 +02:00
Marcelina Kościelnicka
2b777bbda8
opt_share: Refactor, fix some bugs.
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Fixes #2334 .
Fixes #2335 .
Fixes #2336 .
2020-08-17 17:26:36 +02:00
Zachary Snow
2ee0b8ebea
Propagate const_fold through generate blocks and branches
2020-08-09 17:21:08 -04:00
Zachary Snow
96ec9acf84
Allow %0s $display format specifier
2020-08-09 17:19:49 -04:00
Marcelina Kościelnicka
5693386a4e
Remove now-redundant dff2dffs pass.
2020-08-07 13:21:34 +02:00
Marcelina Kościelnicka
a0e99a9f3f
peepopt: Remove now-redundant dffmux pattern.
2020-08-07 13:21:34 +02:00
Marcelina Kościelnicka
9a4f420b4b
Replace opt_rmdff with opt_dff.
2020-08-07 13:21:03 +02:00
Marcelina Kościelnicka
c1ed1c28be
peeopt.shiftmul: Add a signedness check.
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Fixes #2332 .
2020-08-05 21:01:20 +02:00
Marcelina Kościelnicka
b4a4cb081d
techmap.CONSTMAP: Handle outputs before inputs.
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Fixes #2321 .
2020-08-05 12:28:18 +02:00
Marcelina Kościelnicka
e89cc9c02f
peepopt.muldiv: Add a signedness check.
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Fixes #2318 .
2020-08-04 16:30:24 +02:00
Lukasz Dalek
daee2d967f
Add test for subarray access on multidimensional arrays
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Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
2020-08-03 17:07:33 +02:00
Lukasz Dalek
6e78f3a197
Test multirange (unpacked) arrays size
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Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
2020-08-03 15:34:55 +02:00
Zachary Snow
c3e95eb1ab
Fix generate scoping issues
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- expand_genblock defers prefixing of items within named sub-blocks
- Allow partially-qualified references to local scopes
- Handle shadowing within generate blocks
- Resolve generate scope references within tasks and functions
- Apply generate scoping to genvars
- Resolves #2214 , resolves #1456
2020-07-31 20:32:47 -06:00
Marcelina Kościelnicka
18ad56ef41
Add dffunmap pass.
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To be used with backends that cannot deal with fancy FF types (like blif
or smt).
2020-07-31 00:59:51 +02:00
Marcelina Kościelnicka
6cd135a5eb
opt_expr: Remove -clkinv option, make it the default.
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Adds -noclkinv option just in case the old behavior was actually useful
to someone.
2020-07-31 00:08:15 +02:00
Marcelina Kościelnicka
cf60699884
synth_ice40: Use opt_dff.
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The main part is converting ice40_dsp to recognize the new FF types
created in opt_dff instead of trying to recognize the mux patterns on
its own.
The fsm call has been moved upwards because the passes cannot deal with
$dffe/$sdff*, and other optimizations don't help it much anyway.
2020-07-30 22:26:20 +02:00
Marcelina Kościelnicka
8501342fc5
synth_xilinx: Use opt_dff.
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The main part is converting xilinx_dsp to recognize the new FF types
created in opt_dff instead of trying to recognize the patterns on its
own.
The fsm call has been moved upwards because the passes cannot deal with
$dffe/$sdff*, and other optimizations don't help it much anyway.
2020-07-30 22:26:09 +02:00
Marcelina Kościelnicka
af6623ebb8
Add opt_dff pass.
2020-07-30 18:27:04 +02:00
Marcelina Kościelnicka
dc18bf1969
opt_expr: Fix handling of $_XNOR_ cells with A = B.
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Fixes #2311 .
2020-07-29 12:41:43 +02:00
clairexen
66afed6f55
Merge pull request #2306 from YosysHQ/mwk/equiv_induct-undef
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equiv_induct: Fix up assumption for $equiv cells in -undef mode.
2020-07-28 12:56:22 +02:00
Marcelina Kościelnicka
a1a0abf52a
equiv_induct: Fix up assumption for $equiv cells in -undef mode.
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Before this fix, equiv_induct only assumed that one of the following is
true:
- defined value of A is equal to defined value of B
- A is undefined
This lets through valuations where A is defined, B is undefined, and
the defined (meaningless) value of B happens to match the defined value
of A. Instead, tighten this up to OR of the following:
- defined value of A is equal to defined value of B, and B is not
undefined
- A is undefined
2020-07-27 18:36:13 +02:00
Dan Ravensloft
a2fb84fd0c
intel_alm: direct M10K instantiation
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This reverts commit a3a90f6377
.
2020-07-27 15:39:06 +02:00
Dan Ravensloft
62311b7ec0
intel_alm: increase abc9 -W
2020-07-26 23:56:54 +02:00
clairexen
9bcde4d82b
Merge pull request #2299 from zachjs/arg-loop
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Avoid generating wires for function args which are constant
2020-07-26 21:34:55 +02:00
Zachary Snow
f69daf4830
Allow blocks with declarations within constant functions
2020-07-25 10:16:12 -06:00
Zachary Snow
59c4ad8ed3
Avoid generating wires for function args which are constant
2020-07-24 21:18:24 -06:00
Marcelina Kościelnicka
1c8483b7dd
zinit: Refactor to use FfInitVals.
2020-07-24 11:22:31 +02:00
Marcelina Kościelnicka
abe4e9e607
clk2fflogic: Support all FF types.
2020-07-24 03:19:48 +02:00
Marcelina Kościelnicka
0c6d0d4b5d
satgen: Add support for dffe, sdff, sdffe, sdffce cells.
2020-07-24 03:19:21 +02:00
clairexen
c0ad522cf6
Merge pull request #2285 from YosysHQ/mwk/techmap-cellname
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techmap: Add _TECHMAP_CELLNAME_ special parameter.
2020-07-23 18:39:42 +02:00
Dan Ravensloft
4d9d90079c
intel_alm: add additional ABC9 timings
2020-07-23 11:57:07 +01:00
Marcelina Kościelnicka
dc07ae9677
techmap: Add _TECHMAP_CELLNAME_ special parameter.
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This parameter will resolve to the name of the cell being mapped. The
first user of this parameter will be synth_intel_alm's Quartus output,
which requires a unique (and preferably descriptive) name passed as
a cell parameter for the memory cells.
2020-07-21 15:00:54 +02:00
Zachary Snow
f285f7b769
Allow reals as constant function parameters
2020-07-19 20:27:09 -06:00
Miodrag Milanović
910f421324
Merge pull request #2238 from YosysHQ/mwk/dfflegalize-anlogic
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anlogic: Use dfflegalize.
2020-07-16 18:07:58 +02:00
clairexen
021ce8e596
Merge pull request #2257 from antmicro/fix-conflicts
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Restore #2203 and #2244 and fix parser conflicts
2020-07-15 11:49:09 +02:00
Marcelina Kościelnicka
3050454d6e
anlogic: Use dfflegalize.
2020-07-14 05:02:50 +02:00
Lofty
a3a90f6377
Revert "intel_alm: direct M10K instantiation"
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This reverts commit 09ecb9b2cf
.
2020-07-13 18:05:38 +02:00
Marcelina Kościelnicka
347dd01c2f
xilinx: Fix srl regression.
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Of standard yosys cells, xilinx_srl only works on $_DFF_?_ and
$_DFFE_?P_, which get upgraded to $_SDFFE_?P?P_ by dfflegalize at the
point where xilinx_srl is called for non-abc9. Fix this by running
ff_map.v first, resulting in FDRE cells, which are handled correctly.
2020-07-12 23:41:27 +02:00
Kamil Rakoczy
de649b9194
Revert "Revert PRs #2203 and #2244."
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This reverts commit 9c120b89ac
.
2020-07-10 09:59:48 +02:00
whitequark
9c120b89ac
Revert PRs #2203 and #2244 .
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This reverts commit 7e83a51fc9
.
This reverts commit b422f2e4d0
.
This reverts commit 7cb56f34b0
.
This reverts commit 6f9be939bd
.
This reverts commit 76a34dc5f3
.
2020-07-09 19:36:32 +00:00
Marcelina Kościelnicka
7ed9d18907
dfflibmap: Refactor to use dfflegalize internally.
2020-07-09 18:51:03 +02:00
Marcelina Kościelnicka
32d2cc8c28
clkbufmap: improve input pad handling.
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- allow inserting only the input pad cell
- do not insert the usual buffer if the input pad already acts as a
buffer
2020-07-09 18:48:01 +02:00
clairexen
802671b22e
Merge pull request #2244 from antmicro/logic
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Add logic type support to parameters
2020-07-09 18:39:30 +02:00
Marcelina Kościelnicka
03e28f7ab4
clk2fflogic: Consistently treat async control signals as negative hold.
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This fixes some dfflegalize equivalence checks, and breaks others — and
I strongly suspect the others are due to bad support for multiple
async inputs in `proc` (in particular, lack of proper support for
dlatchsr and sketchy circuits on dffsr control inputs).
2020-07-09 18:12:47 +02:00
Marcelina Kościelnicka
e9c2c1b717
dfflegalize: Add special support for const-D latches.
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Those can be created by `opt_dff` when optimizing `$adff` with const
clock, or with D == Q. Make dfflegalize do the opposite transform
when such dlatches would be otherwise unimplementable.
2020-07-09 18:11:32 +02:00
Marcelina Kościelnicka
c73ebeb90e
gowin: Use dfflegalize.
2020-07-06 12:27:46 +02:00
Kamil Rakoczy
b422f2e4d0
Add logic param and integer bad syntax tests
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Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
2020-07-06 09:18:48 +02:00
Dan Ravensloft
09ecb9b2cf
intel_alm: direct M10K instantiation
2020-07-05 23:28:59 +02:00
Dan Ravensloft
7f45cab27a
synth_gowin: ABC9 support
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This adds ABC9 support for synth_gowin; drastically improving
synthesis quality.
2020-07-05 22:07:17 +02:00
Dan Ravensloft
0d4c2f0a65
intel_alm: add Cyclone 10 GX tests
2020-07-05 21:36:38 +02:00
Marcelina Kościelnicka
7afcb72c98
opt_expr: Fix crash on $mul optimization with more zeros removed than Y has.
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Fixes #2221 .
2020-07-05 06:31:58 +02:00
Dan Ravensloft
b004f09018
intel_alm: DSP inference
2020-07-05 05:39:20 +02:00
Marcelina Kościelnicka
3ca2de0f77
synth_intel_alm: Use dfflegalize.
2020-07-04 22:56:16 +02:00
Dan Ravensloft
c6765443fd
Improve MISTRAL_FF specify rules
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Co-authored-by: Eddie Hung <eddie@fpgeh.com>
2020-07-04 19:45:10 +02:00
Eddie Hung
52fbaeca07
tests: update fsm.ys resource count
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Suspect it is to do with map/set ordering in techmap; should
be fixed by #1862 ?
2020-07-04 19:45:10 +02:00
clairexen
5428666151
Merge pull request #2186 from YosysHQ/mwk/dfflegalize
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Add dfflegalize pass.
2020-07-02 17:46:11 +02:00
clairexen
7450ee7f8a
Merge pull request #2203 from antmicro/fix-grammar
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Signed and macro grammar update
2020-07-01 16:41:32 +02:00
clairexen
8ce4f8790e
Merge pull request #2179 from splhack/static-cast
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Support SystemVerilog Static Cast
2020-07-01 16:40:20 +02:00
Marcelina Kościelnicka
6b42819a37
dfflegalize: Add tests.
2020-07-01 01:57:15 +02:00
Zachary Snow
27cec16cda
Allow constant function calls in for loops and generate if and case
2020-06-29 16:06:17 -06:00
Kamil Rakoczy
76a34dc5f3
Add signed/unsigned tests
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Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
2020-06-26 15:38:20 +02:00
Kamil Rakoczy
39c39848a2
Add sub-assign and and-assign tests
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Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
2020-06-25 14:32:05 +02:00
Kamil Rakoczy
470df03f3d
Move combined assign tests to single file
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Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
2020-06-25 14:19:16 +02:00
Kamil Rakoczy
f6d06c9f7b
Add xor-assignment test
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Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
2020-06-24 14:46:21 +02:00
Kamil Rakoczy
a5ca4eeefb
Add or-assignment and plus-assignment tests
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Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
2020-06-24 11:56:26 +02:00
Marcelina Kościelnicka
88e7f90663
Update dff2dffe, dff2dffs, zinit to new FF types.
2020-06-23 18:24:53 +02:00
Kazuki Sakamoto
6bf75be73b
static cast: add tests
2020-06-19 17:40:38 -07:00
whitequark
7191dd16f9
Use C++11 final/override keywords.
2020-06-18 23:34:52 +00:00
Dan Ravensloft
8b4eb78849
intel_alm: fix DFFE matching
2020-06-11 19:55:51 +02:00
diego
d68a8f9e2b
Removing trailing whitespace
2020-06-10 10:35:40 -05:00
Claire Wolf
b3b515087d
Fix tests/opt/opt_rmdff
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This only passed before because "prep" was also running opt_rmdff
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-06-09 22:48:26 +02:00
diego
3c2a1171ff
Adding latch tests for shift&mask AST dynamic part-select enhancements
2020-06-09 15:17:01 -05:00
Peter Crozier
01ec681373
Support 2D bit arrays in structures. Optimise array indexing.
2020-06-08 20:34:52 +01:00
Peter Crozier
76c499db71
Support packed arrays in struct/union.
2020-06-07 18:33:11 +01:00
Claire Wolf
7112f187cd
Add missing .gitignore file
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-06-04 22:25:47 +02:00
clairexen
352731df4e
Merge pull request #2041 from PeterCrozier/struct
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Implementation of SV structs.
2020-06-04 18:26:07 +02:00
Eddie Hung
69850204c4
Merge pull request #2077 from YosysHQ/eddie/abc9_dff_improve
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abc9: -dff improvements
2020-06-04 08:15:25 -07:00
Eddie Hung
45cd323055
Merge pull request #2082 from YosysHQ/eddie/abc9_scc_fixes
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abc9: fixes around handling combinatorial loops
2020-06-03 17:35:46 -07:00
Peter Crozier
0d3f7ea011
Merge branch 'master' into struct
2020-06-03 17:19:28 +01:00
Eddie Hung
8a11019d38
tests: tidy up testcase
2020-06-03 08:41:55 -07:00
Eddie Hung
46ed0db2ec
Merge pull request #2080 from YosysHQ/eddie/fix_test_warnings
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tests: reduce test warnings
2020-06-03 08:37:07 -07:00
Miodrag Milanovic
0a88f002e5
allow range for mux test
2020-06-01 13:48:19 +02:00
Eddie Hung
ea4374a223
abc9_ops: update messaging (credit to @Xiretza for spotting)
2020-05-30 08:57:48 -07:00
Eddie Hung
d3b53bc495
abc9_ops: -reintegrate use SigMap to remove (* init *) from $_DFF_[NP]_
2020-05-29 17:17:40 -07:00
clairexen
0a14e1e837
Merge pull request #2029 from whitequark/fix-simplify-memory-sv_logic
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ast/simplify: don't bitblast async ROMs declared as `logic`
2020-05-29 16:52:11 +02:00
Xiretza
6a2bac21d3
Expand tests/simple/constmuldivmod.v
2020-05-28 22:59:04 +02:00
whitequark
abac0ab28e
Merge pull request #2091 from boqwxp/printattrs
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Add `printattrs` command to print attributes of currently selected objects.
2020-05-28 10:25:34 +00:00
Alberto Gonzalez
6228b10c9f
printattrs: Add test.
2020-05-27 08:00:00 +00:00
Eddie Hung
1dce798dc5
tests: add ecp5 latch testcase with -abc9
2020-05-25 16:39:16 -07:00
Eddie Hung
a7f2ef6d34
Merge pull request #2078 from YosysHQ/eddie/xilinx_sim_tidy
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xilinx: tidy up cells_sim.v a little
2020-05-25 14:21:10 -07:00
Eddie Hung
08221edbc1
tests: xilinx macc test to have initval, shorten BMC depth for runtime
2020-05-25 10:09:05 -07:00
Eddie Hung
60aa804915
tests: fix some test warnings
2020-05-25 10:07:58 -07:00
Eddie Hung
9c6d216a06
tests: add test for abc9 -dff removing a redundant flop entirely
2020-05-25 08:43:33 -07:00
Eddie Hung
8dd93e389e
tests: add testcase for abc9 -dff preserving flop names
2020-05-25 08:43:33 -07:00
Eddie Hung
95dcd7e785
test: add attribute-before-stmt test from @nakengelhardt
2020-05-25 07:36:53 -07:00
Eddie Hung
1c117ac023
verilog: do not warn for attributes on null statements
2020-05-25 07:36:53 -07:00
Eddie Hung
29d84339bf
tests: add an generate-else test too
2020-05-25 07:36:53 -07:00
Eddie Hung
589775538c
tests: add #2037 testcase
2020-05-25 07:36:53 -07:00
Eddie Hung
33b03ce904
xaiger: add testcase
2020-05-24 08:48:23 -07:00
Eddie Hung
574812d9a5
Merge pull request #2057 from YosysHQ/eddie/fix_task_attr
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verilog: support attributes before (not after) task identifier (but 13 s/r conflicts)
2020-05-21 11:00:36 -07:00
Marcelina Kościelnicka
aee439360b
Add force_downto and force_upto wire attributes.
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Fixes #2058 .
2020-05-19 01:42:40 +02:00
Eddie Hung
2d573a0ff6
Merge pull request #1926 from YosysHQ/eddie/abc9_auto_dff
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abc9: support seq synthesis when module has (* abc9_flop *) and bypass non-combinatorial (* abc9_box *)
2020-05-18 08:06:50 -07:00
Eddie Hung
e7fd8912f0
tests: attributes before task enable
2020-05-14 16:09:41 -07:00
Eddie Hung
73b7ea713c
Merge pull request #1994 from YosysHQ/eddie/fix_bug1758
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opt_expr: improve single-bit $and/$or/$xor/$xnor cells; gate cells too
2020-05-14 11:56:22 -07:00
Eddie Hung
13f9d65b6f
abc9: preserve $_DFF_?_.Q's (* init *); rely on clean to remove it
2020-05-14 10:33:57 -07:00
Eddie Hung
7cd3f4a79b
abc9_ops: add -prep_bypass for auto bypass boxes; refactor
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Eliminate need for abc9_{,un}map.v in xilinx
-prep_dff_{hier,unmap} -> -prep_hier
2020-05-14 10:33:56 -07:00
Eddie Hung
722540dbf9
abc9: not enough to techmap_fail on (* init=1 *), hide them using $__
2020-05-14 10:33:56 -07:00
Eddie Hung
5ad3a85288
abc9: test to use box file instead of auto
2020-05-14 10:33:56 -07:00
Eddie Hung
48052ad813
abc9: add flop boxes to basic $_DFF_P_ and $_DFF_N_ too
2020-05-14 10:33:56 -07:00
Eddie Hung
8d7b3c06b2
abc9: suppress warnings when no compatible + used flop boxes formed
2020-05-14 10:33:56 -07:00
Eddie Hung
cdd250ef16
xilinx: update abc9_dff tests
2020-05-14 10:33:56 -07:00
Eddie Hung
762b6ad74a
xilinx: remove no-longer-relevant test
2020-05-14 10:33:56 -07:00
Eddie Hung
5bcde7ccc3
Merge pull request #2045 from YosysHQ/eddie/fix2042
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verilog: error if no direction given for task arguments, default to input in SV mode
2020-05-14 09:45:54 -07:00
Claire Wolf
140e9a8e06
Merge pull request #2050 from YosysHQ/eddie/opt_clean_fixes
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opt_clean: remove (* init *) regardless of -purge, remove (* init *) when consistent with sigmap, clean to behave identically
2020-05-14 18:31:16 +02:00
Claire Wolf
ee0beb481d
Merge pull request #2027 from YosysHQ/eddie/verilog_neg_upto
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ast: swap range regardless of range_left >= 0
2020-05-14 18:06:18 +02:00
Eddie Hung
56a5b1d2da
test: add another testcase as per @nakengelhardt
2020-05-14 08:36:36 -07:00
Eddie Hung
5be4b00a0d
opt_clean: improve warning message
2020-05-14 00:59:38 -07:00
Eddie Hung
aa4a69f89b
opt_clean: add init test
2020-05-14 00:31:08 -07:00
Eddie Hung
0d2c33f9f4
tests: update/extend task argument tests
2020-05-13 10:11:45 -07:00
Peter Crozier
17f050d3c6
Allow structs within structs.
2020-05-12 17:20:34 +01:00
Peter Crozier
f482c9c016
Generalise structs and add support for packed unions.
2020-05-12 14:25:33 +01:00
Eddie Hung
e5ce5a4fd5
tests: add #2042 testcase
2020-05-11 11:05:19 -07:00
Eddie Hung
b11cf67a81
Setup tests/verilog properly
2020-05-11 10:31:02 -07:00
Eddie Hung
49e64ad492
test: update opt_expr_alu test
2020-05-08 11:12:58 -07:00
Eddie Hung
495acf9815
tests: opt_expr tests that depend on consumex
2020-05-08 11:07:11 -07:00
Peter Crozier
0b6b47ca67
Implement SV structs.
2020-05-08 14:40:49 +01:00
Dan Ravensloft
5b779f7f4e
intel_alm: direct LUTRAM cell instantiation
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By instantiating the LUTRAM cell directly, we avoid a trip through
altsyncram, which speeds up Quartus synthesis time. This also gives
a little more flexibility, as Yosys can build RAMs out of individual
32x1 LUTRAM cells.
While working on this, I discovered that the mem_init0 parameter of
<family>_mlab_cell gets ignored by Quartus.
2020-05-07 21:03:13 +02:00
Claire Wolf
0610424940
Merge pull request #2005 from YosysHQ/claire/fix1990
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Add "nowrshmsk" attribute, fix shift-and-mask bit slice write for signed offset
2020-05-07 18:11:48 +02:00
Eddie Hung
a299e606f8
Merge pull request #2028 from zachjs/master
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verilog: allow null gen-if then block
2020-05-06 12:10:28 -07:00
Zachary Snow
8f9bba1bbf
verilog: allow null gen-if then block
2020-05-06 08:43:02 -04:00
Eddie Hung
004999218f
techlibs/common: more robustness when *_WIDTH = 0
2020-05-05 08:01:27 -07:00
Eddie Hung
7a62ee57b4
Merge pull request #2024 from YosysHQ/eddie/primitive_src
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verilog: set src attribute for primitives
2020-05-05 06:49:18 -07:00
whitequark
66d0ed2bcc
ast/simplify: don't bitblast async ROMs declared as `logic`.
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Fixes #2020 .
2020-05-05 04:16:59 +00:00
Eddie Hung
2e911bc806
test: add failing test
2020-05-04 12:18:02 -07:00
Eddie Hung
eb5eb60fd4
verilog: fix specify src attribute
2020-05-04 10:53:06 -07:00
Eddie Hung
ad8e7878f6
tests: add tests for primitives' src
2020-05-04 10:21:47 -07:00
Claire Wolf
5c82c19b4b
Merge pull request #2014 from YosysHQ/claire/fixoptalu
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Fix the other "opt_expr -fine" bug introduced in 213a89558
2020-05-03 11:56:29 +02:00
Eddie Hung
db13852ed6
test: add test for #2014
2020-05-02 14:22:37 -07:00
Eddie Hung
2e78daf1ca
tests: aiger test for wire->start_offset != 0
2020-05-02 10:00:32 -07:00
Claire Wolf
f38d76efbf
Bugfix in partsel.v signed indices test cases
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-05-02 11:21:01 +02:00
Claire Wolf
749c2ff84a
Add tests based on the test case from #1990
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-05-02 11:21:01 +02:00
Eddie Hung
7f9ecddb7f
Add testcase for #2010
2020-05-01 14:07:33 -07:00
Eddie Hung
7f203cb019
tests: fsm to use a randomly-generated seed
2020-04-24 14:31:33 -07:00
Eddie Hung
b5f38f8342
opt_expr: const_xnor replacement to pad Y with 1'b1
2020-04-24 14:13:45 -07:00
Eddie Hung
ebd6fa945d
tests: opt_expr update xnor/xor tests
2020-04-24 11:16:25 -07:00
Eddie Hung
90b71eb84b
opt_expr: do not group by X, more fixes
2020-04-23 18:15:07 -07:00
Eddie Hung
b84415094c
tests: add opt_expr tests
2020-04-23 15:58:36 -07:00
Dan Ravensloft
3d149aff73
intel_alm: work around a Quartus ICE
2020-04-23 11:03:28 +02:00