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Author SHA1 Message Date
Eddie Hung 33b03ce904 xaiger: add testcase 2020-05-24 08:48:23 -07:00
Eddie Hung 574812d9a5
Merge pull request #2057 from YosysHQ/eddie/fix_task_attr 
verilog: support attributes before (not after) task identifier (but 13 s/r conflicts)
 2020-05-21 11:00:36 -07:00
Marcelina Kościelnicka aee439360b Add force_downto and force_upto wire attributes. 
Fixes #2058.
 2020-05-19 01:42:40 +02:00
Eddie Hung 2d573a0ff6
Merge pull request #1926 from YosysHQ/eddie/abc9_auto_dff 
abc9: support seq synthesis when module has (* abc9_flop *) and bypass non-combinatorial (* abc9_box *)
 2020-05-18 08:06:50 -07:00
Eddie Hung e7fd8912f0 tests: attributes before task enable 2020-05-14 16:09:41 -07:00
Eddie Hung 73b7ea713c
Merge pull request #1994 from YosysHQ/eddie/fix_bug1758 
opt_expr: improve single-bit $and/$or/$xor/$xnor cells; gate cells too
 2020-05-14 11:56:22 -07:00
Eddie Hung 13f9d65b6f abc9: preserve $_DFF_?_.Q's (* init *); rely on clean to remove it 2020-05-14 10:33:57 -07:00
Eddie Hung 7cd3f4a79b abc9_ops: add -prep_bypass for auto bypass boxes; refactor 
Eliminate need for abc9_{,un}map.v in xilinx
-prep_dff_{hier,unmap} -> -prep_hier
 2020-05-14 10:33:56 -07:00
Eddie Hung 722540dbf9 abc9: not enough to techmap_fail on (* init=1 *), hide them using $__ 2020-05-14 10:33:56 -07:00
Eddie Hung 5ad3a85288 abc9: test to use box file instead of auto 2020-05-14 10:33:56 -07:00
Eddie Hung 48052ad813 abc9: add flop boxes to basic $_DFF_P_ and $_DFF_N_ too 2020-05-14 10:33:56 -07:00
Eddie Hung 8d7b3c06b2 abc9: suppress warnings when no compatible + used flop boxes formed 2020-05-14 10:33:56 -07:00
Eddie Hung cdd250ef16 xilinx: update abc9_dff tests 2020-05-14 10:33:56 -07:00
Eddie Hung 762b6ad74a xilinx: remove no-longer-relevant test 2020-05-14 10:33:56 -07:00
Eddie Hung 5bcde7ccc3
Merge pull request #2045 from YosysHQ/eddie/fix2042 
verilog: error if no direction given for task arguments, default to input in SV mode
 2020-05-14 09:45:54 -07:00
Claire Wolf 140e9a8e06
Merge pull request #2050 from YosysHQ/eddie/opt_clean_fixes 
opt_clean: remove (* init *) regardless of -purge, remove (* init *) when consistent with sigmap, clean to behave identically
 2020-05-14 18:31:16 +02:00
Claire Wolf ee0beb481d
Merge pull request #2027 from YosysHQ/eddie/verilog_neg_upto 
ast: swap range regardless of range_left >= 0
 2020-05-14 18:06:18 +02:00
Eddie Hung 56a5b1d2da test: add another testcase as per @nakengelhardt 2020-05-14 08:36:36 -07:00
Eddie Hung 5be4b00a0d opt_clean: improve warning message 2020-05-14 00:59:38 -07:00
Eddie Hung aa4a69f89b opt_clean: add init test 2020-05-14 00:31:08 -07:00
Eddie Hung 0d2c33f9f4 tests: update/extend task argument tests 2020-05-13 10:11:45 -07:00
Peter Crozier 17f050d3c6 Allow structs within structs. 2020-05-12 17:20:34 +01:00
Peter Crozier f482c9c016 Generalise structs and add support for packed unions. 2020-05-12 14:25:33 +01:00
Eddie Hung e5ce5a4fd5 tests: add #2042 testcase 2020-05-11 11:05:19 -07:00
Eddie Hung b11cf67a81 Setup tests/verilog properly 2020-05-11 10:31:02 -07:00
Eddie Hung 49e64ad492 test: update opt_expr_alu test 2020-05-08 11:12:58 -07:00
Eddie Hung 495acf9815 tests: opt_expr tests that depend on consumex 2020-05-08 11:07:11 -07:00
Peter Crozier 0b6b47ca67 Implement SV structs. 2020-05-08 14:40:49 +01:00
Dan Ravensloft 5b779f7f4e intel_alm: direct LUTRAM cell instantiation 
By instantiating the LUTRAM cell directly, we avoid a trip through
altsyncram, which speeds up Quartus synthesis time. This also gives
a little more flexibility, as Yosys can build RAMs out of individual
32x1 LUTRAM cells.

While working on this, I discovered that the mem_init0 parameter of
<family>_mlab_cell gets ignored by Quartus.
 2020-05-07 21:03:13 +02:00
Claire Wolf 0610424940
Merge pull request #2005 from YosysHQ/claire/fix1990 
Add "nowrshmsk" attribute, fix shift-and-mask bit slice write for signed offset
 2020-05-07 18:11:48 +02:00
Eddie Hung a299e606f8
Merge pull request #2028 from zachjs/master 
verilog: allow null gen-if then block
 2020-05-06 12:10:28 -07:00
Zachary Snow 8f9bba1bbf verilog: allow null gen-if then block 2020-05-06 08:43:02 -04:00
Eddie Hung 004999218f techlibs/common: more robustness when *_WIDTH = 0 2020-05-05 08:01:27 -07:00
Eddie Hung 7a62ee57b4
Merge pull request #2024 from YosysHQ/eddie/primitive_src 
verilog: set src attribute for primitives
 2020-05-05 06:49:18 -07:00
whitequark 66d0ed2bcc ast/simplify: don't bitblast async ROMs declared as `logic`. 
Fixes #2020.
 2020-05-05 04:16:59 +00:00
Eddie Hung 2e911bc806 test: add failing test 2020-05-04 12:18:02 -07:00
Eddie Hung eb5eb60fd4 verilog: fix specify src attribute 2020-05-04 10:53:06 -07:00
Eddie Hung ad8e7878f6 tests: add tests for primitives' src 2020-05-04 10:21:47 -07:00
Claire Wolf 5c82c19b4b
Merge pull request #2014 from YosysHQ/claire/fixoptalu 
Fix the other "opt_expr -fine" bug introduced in 213a89558
 2020-05-03 11:56:29 +02:00
Eddie Hung db13852ed6 test: add test for #2014 2020-05-02 14:22:37 -07:00
Eddie Hung 2e78daf1ca tests: aiger test for wire->start_offset != 0 2020-05-02 10:00:32 -07:00
Claire Wolf f38d76efbf Bugfix in partsel.v signed indices test cases 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-05-02 11:21:01 +02:00
Claire Wolf 749c2ff84a Add tests based on the test case from #1990 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-05-02 11:21:01 +02:00
Eddie Hung 7f9ecddb7f Add testcase for #2010 2020-05-01 14:07:33 -07:00
Eddie Hung 7f203cb019 tests: fsm to use a randomly-generated seed 2020-04-24 14:31:33 -07:00
Eddie Hung b5f38f8342 opt_expr: const_xnor replacement to pad Y with 1'b1 2020-04-24 14:13:45 -07:00
Eddie Hung ebd6fa945d tests: opt_expr update xnor/xor tests 2020-04-24 11:16:25 -07:00
Eddie Hung 90b71eb84b opt_expr: do not group by X, more fixes 2020-04-23 18:15:07 -07:00
Eddie Hung b84415094c tests: add opt_expr tests 2020-04-23 15:58:36 -07:00
Dan Ravensloft 3d149aff73 intel_alm: work around a Quartus ICE 2020-04-23 11:03:28 +02:00
Eddie Hung 988d47af85 tests: read +/xilinx/cell_sim.v before xilinx_dsp test 2020-04-22 17:50:30 -07:00
Eddie Hung db09e96dff test: ice40_dsp test to read +/ice40/cells_sim.v for default params 2020-04-22 16:35:35 -07:00
Eddie Hung f582eb14af xilinx: xilinx_dffopt to read cells_sim.v; fix test 2020-04-22 16:25:23 -07:00
Eddie Hung fa9df06c9d
Merge pull request #1949 from YosysHQ/eddie/select_blackbox 
select: do not select inside black-/white- boxes unless '=' prefix used
 2020-04-22 15:35:05 -07:00
Eddie Hung db27f2f378
Merge pull request #1973 from YosysHQ/eddie/fix1966 
tests: fix various/plugin.sh when PREFIX != /usr/local/share
 2020-04-22 10:19:30 -07:00
Eddie Hung 281cd10717 tests: update select black/white-box tests 2020-04-22 10:16:14 -07:00
Eddie Hung 28623f19ee
Merge pull request #1950 from YosysHQ/eddie/design_import 
design: -import to not count black/white-boxes as candidates for top
 2020-04-22 09:32:13 -07:00
Eddie Hung 634b5e2d9f tests: use `yosys-config --datdir` instead of hard-coded 2020-04-22 08:29:45 -07:00
Claire Wolf c32b4bded5
Merge pull request #1976 from YosysHQ/dave/fix-sim-const 
sim: Fix handling of constant-connected cell inputs at startup
 2020-04-22 16:57:34 +02:00
Marcelina Kościelnicka 846c79b312 hierarchy: Convert positional parameters to named. 
Fixes #1821.
 2020-04-21 19:09:00 +02:00
Claire Wolf 9e1afde7a0
Merge pull request #1851 from YosysHQ/claire/bitselwrite 
Improved rewrite code for writing to bit slice
 2020-04-21 18:46:52 +02:00
David Shah abf81c7639 sim: Fix handling of constant-connected cell inputs at startup 
Signed-off-by: David Shah <dave@ds0.me>
 2020-04-21 08:58:52 +01:00
Eddie Hung 38ee59184c tests: remove write_ilang 2020-04-20 15:42:29 -07:00
Eddie Hung caf4071c8b Remove '-ignore_unknown_cells' option from 'sat' 2020-04-20 11:58:23 -07:00
Eddie Hung a1573058e9 Simplify test case script 2020-04-20 11:54:10 -07:00
Eddie Hung 99a0958601 Remove ununsed files 2020-04-20 11:53:48 -07:00
diego 22f440506b Modifications of tests as per Eddie's request 2020-04-20 12:45:35 -05:00
Eddie Hung 34d8ff8b56 abc9: add testcase reduced from #1970 2020-04-20 09:38:29 -07:00
diego 50581d5a94 Wrong fixed value 2020-04-17 10:15:22 -05:00
Eddie Hung 9eace8f360 design: add test 2020-04-16 12:48:40 -07:00
Eddie Hung 2ddfb61e65 select: add test for not selecting inside black/white boxes 2020-04-16 12:45:04 -07:00
diego 87910732f1 Adding tests for dynamic part select optimisation 2020-04-16 13:31:05 -05:00
Eddie Hung 2623e335cc tests: add select -unset tests 2020-04-16 10:51:58 -07:00
Eddie Hung e8a841467f tests: add design -delete tests 2020-04-16 08:05:18 -07:00
David Shah 2b57c06360
Merge pull request #1943 from YosysHQ/dave/fix-1919 
ast: Fix handling of identifiers in the global scope
 2020-04-16 13:48:20 +01:00
Marcelina Kościelnicka 2f8541a92e opt_expr: Fix X and CO outputs for $alu identity-mapping rules. 2020-04-16 11:48:29 +02:00
David Shah 4d02505820 ast: Fix handling of identifiers in the global scope 
Signed-off-by: David Shah <dave@ds0.me>
 2020-04-16 10:30:07 +01:00
Eddie Hung 33b0ac9269
Merge pull request #1933 from YosysHQ/eddie/zinit_more 
zinit: handle $__DFFS?E?_[NP][NP][01] too
 2020-04-15 08:36:25 -07:00
Claire Wolf 4ee8fc1473
Merge pull request #1930 from YosysHQ/claire/fix1876 
Fix handling of ternary with constant condition
 2020-04-15 16:01:19 +02:00
Dan Ravensloft 2e37e62e6b synth_intel_alm: alternative synthesis for Intel FPGAs 
By operating at a layer of abstraction over the rather clumsy Intel primitives,
we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping.

This also makes the primitives much easier to manipulate, and more descriptive
(no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6).
 2020-04-15 11:40:41 +02:00
Eddie Hung 383fe4a4bc tests: zinit for new types 2020-04-14 13:08:37 -07:00
Marcelina Kościelnicka 6c16fd760b opt_expr: Add more $alu optimizations. 
Detect the places in the $alu where the carry bit is constant (due to
const A[i] == B[i] ^ BI) and split it into smaller $alu at these points.

Also, make the existing const-carry detection for low bits more generic
(now handles cases where both BI and CI are constant, but not equal to
one another).

Fixes #1912.
 2020-04-14 21:48:13 +02:00
Eddie Hung e7121cc15c tests: add testcases from #1876 2020-04-14 12:39:10 -07:00
Marcelina Kościelnicka 7a36728b2f dffinit: Avoid setting init parameter to zero-length value. 
Fixes #1704.
 2020-04-14 19:52:19 +02:00
whitequark f41c7ccfff
Merge pull request #1879 from jjj11x/jjj11x/package_decl 
support using previously declared types/localparams/parameters in package
 2020-04-14 12:40:00 +00:00
Eddie Hung b75c5bf743 zinit: resolve one more comment by @mwkmwkmwk 2020-04-13 15:25:37 -07:00
Eddie Hung c6afce7638 zinit: fix review comments from @mwkmwkmwk 2020-04-13 15:16:51 -07:00
Eddie Hung 091297b9ee tests: zinit on $adff 2020-04-13 14:29:44 -07:00
Eddie Hung 3c5a9411b1 Add testcase for $_DFF_[NP][NP][01]_ 2020-04-13 13:16:49 -07:00
Marcelina Kościelnicka 840bb17089 opt_expr: Optimize multiplications with low 0 bits in operands. 
Fixes #1500.
 2020-04-13 16:52:22 +02:00
Xiretza 7f1d83c5db Add .gitignore to tests/select/ 2020-04-12 22:45:45 +02:00
whitequark 93ef516d91
Merge pull request #1603 from whitequark/ice40-ram_style 
ice40/ecp5: add support for both 1364.1 and Synplify/LSE RAM/ROM attributes
 2020-04-10 14:51:01 +00:00
Eddie Hung f11dd6e208 tests: add a quick plugin test 2020-04-09 09:45:20 -07:00
Jeff Wang 249876b614 support using previously declared types/localparams/params in package 
(parameters in systemverilog packages can't actually be overridden, so
allowing parameters in addition to localparams doesn't actually add any
new functionality, but it's useful to be able to use the parameter
keyword also)
 2020-04-07 00:38:15 -04:00
Eddie Hung d61a6b81fc
Merge pull request #1648 from YosysHQ/eddie/cmp2lcu 
"techmap -map +/cmp2lcu.v" for decomposing arithmetic compares to $lcu
 2020-04-03 16:28:25 -07:00
Eddie Hung 92d70cafec +/cmp2lcu.v to work efficiently for fully/partially constant inputs 2020-04-03 14:28:22 -07:00
Eddie Hung f68d723cdc Refactor +/cmp2lcu.v into recursive techmap 2020-04-03 14:28:22 -07:00
Eddie Hung 9b63700678 techmap +/cmp2lcu.v for decomposing arithmetic compares to $lcu 2020-04-03 14:28:22 -07:00
whitequark 763401fc82 ecp5: do not map FFRAM if explicitly requested otherwise. 2020-04-03 05:51:40 +00:00
whitequark ebee746ad2 ice40: do not map FFRAM if explicitly requested otherwise. 2020-04-03 05:51:40 +00:00
Marcin Kościelnicki 2d3753d730 iopadmap: Fix z assignment to inout port 
Fixes #1841.
 2020-04-02 18:15:04 +02:00
Eddie Hung 4ae7f3a8ed
Merge pull request #1790 from YosysHQ/eddie/opt_expr_xor 
opt_expr: optimise $xor/$xnor/$_XOR_/$_XNOR_ -s with constant inputs
 2020-04-01 14:17:01 -07:00
Eddie Hung e79bc45975
Merge pull request #1789 from YosysHQ/eddie/opt_expr_alu 
opt_expr: improve performance on $alu and $sub
 2020-04-01 14:11:09 -07:00
Claire Wolf 926a010b49
Merge pull request #1848 from YosysHQ/eddie/fix_dynslice 
ast: simplify to fully populate dynamic slicing case transformation
 2020-04-01 08:38:14 +02:00
Eddie Hung 1bb5a5215f
Merge pull request #1761 from YosysHQ/eddie/opt_merge_speedup 
opt_merge: speedup
 2020-03-31 14:50:32 -07:00
Eddie Hung 3df66027e0 Add dynamic slicing Verilog testcase 2020-03-31 11:51:31 -07:00
N. Engelhardt d5e2061687
Merge pull request #1811 from PeterCrozier/typedef_scope 
Support module/package/interface/block scope for typedef names.
 2020-03-30 13:55:39 +02:00
Rupert Swarbrick 044ca9dde4 Add support for SystemVerilog-style `define to Verilog frontend 
This patch should support things like

  `define foo(a, b = 3, c)   a+b+c

  `foo(1, ,2)

which will evaluate to 1+3+2. It also spots mistakes like

  `foo(1)

(the 3rd argument doesn't have a default value, so a call site is
required to set it).

Most of the patch is a simple parser for the format in preproc.cc, but
I've also taken the opportunity to wrap up the "name -> definition"
map in a type, rather than use multiple std::map's.

Since this type needs to be visible to code that touches defines, I've
pulled it (and the frontend_verilog_preproc declaration) out into a
new file at frontends/verilog/preproc.h and included that where
necessary.

Finally, the patch adds a few tests in tests/various to check that we
are parsing everything correctly.
 2020-03-27 16:08:26 +00:00
Claire Wolf 590d8eccb7
Merge pull request #1806 from YosysHQ/mwk/techmap-replace-fix 
techmap: Fix cell names with _TECHMAP_REPLACE_.*
 2020-03-26 19:03:37 +01:00
Peter Crozier ecc22f7fed Support module/package/interface/block scope for typedef names. 2020-03-23 20:07:22 +00:00
N. Engelhardt 3e46faa58c
Merge pull request #1763 from boqwxp/issue1762 
Closes #1762. Adds warnings for `select` arguments not matching any object and for `add` command when no modules selected
 2020-03-23 20:14:13 +01:00
Alberto Gonzalez 0da65d498b
Do not warn on empty selection with prefixed `arg_memb`. 
Co-Authored-By: N. Engelhardt <nak@symbioticeda.com>
 2020-03-23 17:50:11 +00:00
Alberto Gonzalez ca4e5dd56e
Suppress warnings for empty `select` arguments when `-count` or `-assert-*` options are set. 2020-03-23 17:30:53 +00:00
Alberto Gonzalez 1b333d49ef
Add tests for `select` command warnings. 2020-03-23 17:30:53 +00:00
N. Engelhardt b86905d952
Merge pull request #1803 from Grazfather/typedef 
Support standard typedef grammar (Fixed)
 2020-03-23 13:43:35 +01:00
Marcin Kościelnicki c2bf11e42a techmap: Fix cell names with _TECHMAP_REPLACE_.* 
Fixes #1804.
 2020-03-23 11:17:07 +01:00
Peter 6d8d6b402f Revert typedef tests to standard grammar. 2020-03-22 18:20:46 -07:00
Eddie Hung 6274f0b075 opt_expr: add failing $xnor test 2020-03-20 14:38:50 -07:00
David Shah fa77fb857b Add test for abc9+mince issue 
Signed-off-by: David Shah <dave@ds0.me>
 2020-03-20 20:35:28 +00:00
Eddie Hung 317c18fc6f Simplify breaking tests/arch/*/fsm.ys tests 2020-03-20 11:25:17 -07:00
Eddie Hung 81ca776ea4 opt_expr: add $xor/$xnor/$_XOR_/$_XNOR_ tests 2020-03-19 16:59:11 -07:00
Eddie Hung 5e2562f1a2 opt_expr: add $alu tests 2020-03-19 14:57:10 -07:00
Marcin Kościelnicki e91368a5f4 fsm_extract: Initialize celltypes with full design. 
Fixes #1781.
 2020-03-19 18:51:21 +01:00
N. Engelhardt e03f725ef2
Merge pull request #1774 from boqwxp/exec 
Add `exec` command to allow running shell commands from inside Yosys scripts
 2020-03-19 13:14:43 +01:00
N. Engelhardt 644deb708d fix argument order for macOS compatibility 2020-03-18 15:11:49 +01:00
Eddie Hung 9f30d7f843 opt_merge: speedup 2020-03-16 12:43:54 -07:00
Alberto Gonzalez a09b260c01
Add test for `exec` command. 2020-03-16 07:52:58 +00:00
Miodrag Milanović 569e834df2
Merge pull request #1759 from zeldin/constant_with_comment_redux 
refixed parsing of constant with comment between size and value
 2020-03-14 13:34:59 +02:00
Marcus Comstedt dd562f29e7 Add regression tests for new handling of comments in constants 2020-03-14 11:41:09 +01:00
Miodrag Milanović faf4ee69de
Merge pull request #1754 from boqwxp/precise_locations 
Set AST node source location in more parser rules.
 2020-03-14 11:18:39 +02:00
Miodrag Milanovic 5b73e7c63a Added back tests for logger 2020-03-13 15:00:18 +01:00
Eddie Hung 3ada82639f verilog: add test 2020-03-11 06:51:03 -07:00
David Shah ddcd87b577
Merge pull request #1721 from YosysHQ/dave/tribuf-unused 
deminout: Don't demote inouts with unused bits
 2020-03-10 13:51:40 +00:00
Claire Wolf a7cc4673c3 Fix partsel expr bit width handling and add test case 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-03-08 16:12:12 +01:00
N. Engelhardt 88494e81f5 rpc test: make frontend listen before launching yosys & introduce safeguard if yosys errors 2020-03-06 15:29:01 +01:00
Eddie Hung 3c2e910bb3 tests: extend tests/arch/run-tests.sh for defines 2020-03-05 08:08:32 -08:00
David Shah 5cae9c6e16 deminout: Don't demote inouts with unused bits 
Signed-off-by: David Shah <dave@ds0.me>
 2020-03-04 18:44:38 +00:00
Claire Wolf b597f85b13
Merge pull request #1718 from boqwxp/precise_locations 
Closes #1717. Add more precise Verilog source location information to AST and RTLIL nodes.
 2020-03-03 08:38:32 -08:00
Claire Wolf 879124333f
Merge pull request #1519 from YosysHQ/eddie/submod_po 
submod: several bugfixes
 2020-03-03 08:19:06 -08:00
Marcelina Kościelnicka 968956badb
iopadmap: Look harder for already-present buffers. (#1731) 
iopadmap: Look harder for already-present buffers.

Fixes #1720.
 2020-03-02 21:40:09 +01:00
Eddie Hung 4f889b2f57
Merge pull request #1724 from YosysHQ/eddie/abc9_specify 
abc9: auto-generate *.lut/*.box files and arrival/required times from specify entries
 2020-03-02 12:32:27 -08:00
Eddie Hung 5bba9c3640 ast: fixes #1710; do not generate RTLIL for unreachable ternary 2020-02-27 16:55:55 -08:00
Eddie Hung a179d918ec Revert "Fix tests/arch/xilinx/fsm.ys to count flops only" 
This reverts commit 68f903c6dd7403a4cf280cf71ee02d20345938b5.
 2020-02-27 10:17:29 -08:00
Eddie Hung f858219c4e Cleanup tests 2020-02-27 10:17:29 -08:00
Eddie Hung 717fb492b3 Update bug1630.ys to use -lut 4 instead of lut file 2020-02-27 10:17:29 -08:00
Eddie Hung bc97e64b21 Fix tests/arch/xilinx/fsm.ys to count flops only 2020-02-27 10:17:29 -08:00
Eddie Hung 977262c803 Update simple_abc9 tests 2020-02-27 10:17:29 -08:00
Alberto Gonzalez f80fe8dc22
Change attribute search value to specify precise location instead of simple line number. 2020-02-24 02:41:08 +00:00
Alberto Gonzalez 2c2f092c90
Change attribute search value to specify precise location instead of simple line number. 2020-02-24 01:39:36 +00:00
Eddie Hung 760096e8d2
Merge pull request #1703 from YosysHQ/eddie/specify_improve 
Improve specify parser
 2020-02-21 09:15:17 -08:00
Claire Wolf cd044a2bb6
Merge pull request #1642 from jjj11x/jjj11x/sv-enum 
Enum support
 2020-02-20 18:17:25 +01:00
Eddie Hung 1d401a7991 clean: ignore specify-s inside cells when determining whether to keep 2020-02-19 10:45:10 -08:00
Jeff Wang d12ba42a74 add attributes for enumerated values in ilang 
- information also useful for strongly-typed enums (not implemented)
- resolves enum values in ilang part of #1594
- still need to output enums to VCD (or better yet FST) files
 2020-02-17 04:42:42 -05:00
Marcin Kościelnicki cd60f079d6 tests/aiger: Add missing .gitignore 2020-02-15 19:52:21 +01:00
Miodrag Milanović c7af1b22ba
Merge pull request #1701 from nakengelhardt/rpc-test 
make rpc frontend unix socket test less fragile
 2020-02-14 12:06:37 +01:00
Eddie Hung d20c1dac73 verilog: ignore ranges too without -specify 2020-02-13 17:58:43 -08:00
Eddie Hung 3065d4092e Fine tune #1699 tests 2020-02-13 15:14:58 -08:00
Eddie Hung 6b58c1820c verilog: improve specify support when not in -specify mode 2020-02-13 13:27:15 -08:00
Eddie Hung 2e51dc1856 verilog: ignore '&&&' when not in -specify mode 2020-02-13 13:06:13 -08:00
Eddie Hung b523ecf2f4 specify: system timing checks to accept min:typ:max triple 2020-02-13 12:42:15 -08:00
Eddie Hung 7cfdf4ffa7 verilog: fix $specify3 check 2020-02-13 12:42:04 -08:00
Eddie Hung ebb11bcea4 iopadmap: move \init attributes from outpad output to its input 2020-02-13 12:05:14 -08:00
N. Engelhardt c2467fdd55 make rpc frontend unix socket test less fragile 2020-02-13 20:52:22 +01:00
N. Engelhardt e069259a53
Merge pull request #1679 from thasti/delay-parsing 
Fix crash on wire declaration with delay
 2020-02-13 12:01:27 +01:00
Eddie Hung d4ff5b2d00
Merge pull request #1670 from rodrigomelo9/master 
$readmem[hb] file inclusion is now relative to the Verilog file
 2020-02-10 08:31:01 -08:00
Marcin Kościelnicki 89adef352f xilinx: Add support for LUT RAM on LUT4-based devices. 
There are multiple other kinds of RAMs supported on these devices, but
RAM16X1D is the only dual-port one.

Fixes #1549
 2020-02-07 09:03:22 +01:00
Marcin Kościelnicki d48950d92d xilinx: Initial support for LUT4 devices. 
Adds support for mapping logic, including LUTs, wide LUTs, and carry
chains.

Fixes #1547
 2020-02-07 09:03:22 +01:00
whitequark 081d9318bc ecp5: add support for both 1364.1 and LSE RAM/ROM attributes. 
This commit tries to carefully follow the documented behavior of LSE
and Synplify. It will use `syn_ramstyle` attribute if there are any
write ports, and `syn_romstyle` attribute otherwise.
  * LSE supports both `syn_ramstyle` and `syn_romstyle`.
  * Synplify only supports `syn_ramstyle`, with same values as LSE.
  * Synplify also supports `syn_rw_conflict_logic`, which is not
    documented as supported for LSE.

Limitations of the Yosys implementation:
  * LSE/Synplify support `syn_ramstyle="block_ram,no_rw_check"`
    syntax to turn off insertion of transparency logic. There is
    currently no way to support multiple valued attributes in
    memory_bram. It is also not clear if that is a good idea, since
    it can cause sim/synth mismatches.
  * LSE/Synplify/1364.1 support block ROM inference from full case
    statements. Yosys does not currently perform this transformation.
  * LSE/Synplify propagate `syn_ramstyle`/`syn_romstyle` attributes
    from the module to the inner memories. There is currently no way
    to do this in Yosys (attrmvcp only works on cells and wires).
 2020-02-06 16:52:51 +00:00
whitequark 3f4460a186 ice40: match memory inference attribute values case insensitive. 
LSE/Synplify use case insensitive matching.
 2020-02-06 14:58:20 +00:00
whitequark fc28bf55aa ice40: add support for both 1364.1 and LSE RAM/ROM attributes. 
This commit tries to carefully follow the documented behavior of LSE
and Synplify. It will use `syn_ramstyle` attribute if there are any
write ports, and `syn_romstyle` attribute otherwise.
  * LSE supports both `syn_ramstyle` and `syn_romstyle`.
  * Synplify only supports `syn_ramstyle`, with same values as LSE.
  * Synplify also supports `syn_rw_conflict_logic`, which is not
    documented as supported for LSE.

Limitations of the Yosys implementation:
  * LSE/Synplify appear to interpret attribute values insensitive
    to case. There is currently no way to do this in Yosys (attrmap
    can only change case of attribute names).
  * LSE/Synplify support `syn_ramstyle="block_ram,no_rw_check"`
    syntax to turn off insertion of transparency logic. There is
    currently no way to support multiple valued attributes in
    memory_bram. It is also not clear if that is a good idea, since
    it can cause sim/synth mismatches.
  * LSE/Synplify/1364.1 support block ROM inference from full case
    statements. Yosys does not currently perform this transformation.
  * LSE/Synplify propagate `syn_ramstyle`/`syn_romstyle` attributes
    from the module to the inner memories. There is currently no way
    to do this in Yosys (attrmvcp only works on cells and wires).
 2020-02-06 14:58:20 +00:00
whitequark 29d130dee9 ice40: remove impossible test. 
iCE40 does not have LUTRAM. This was erroneously added in commit
caab66111e, and tested for BRAM,
essentially a duplicate of the "dpram.ys" test.
 2020-02-06 14:58:20 +00:00
Rodrigo Alejandro Melo 9da5936c05 Added 'set -e' into tests/memfile/run-test.sh 
Also added two checks for situations where the execution must fail.

Signed-off-by: Rodrigo Alejandro Melo <rmelo@inti.gob.ar>
 2020-02-06 10:45:40 -03:00
Eddie Hung 4c1d3a126d shiftx2mux: fix select out of bounds 2020-02-05 16:41:09 -08:00
Eddie Hung 505557e93e
Merge pull request #1576 from YosysHQ/eddie/opt_merge_init 
opt_merge: discard \init of '$' cells with 'Q' port when merging
 2020-02-05 14:56:26 -08:00
Eddie Hung 6eb7e925a1
Merge pull request #1650 from YosysHQ/eddie/shiftx2mux 
techmap LSB-first for compatible $shift/$shiftx cells
 2020-02-05 14:55:57 -08:00
Eddie Hung 0b308c6835 abc9_ops: -reintegrate to use derived_type for box_ports 2020-02-05 14:46:48 -08:00
Eddie Hung b6a1f627b5 Merge remote-tracking branch 'origin/master' into eddie/shiftx2mux 2020-02-05 10:47:31 -08:00
Eddie Hung 5ebdc0f8e0
Merge pull request #1638 from YosysHQ/eddie/fix1631 
clk2fflogic: work for bit-level $_DFF_* and $_DFFSR_*
 2020-02-05 19:31:18 +01:00
Stefan Biereigel 90c78f1f85 add testcase for #1614 2020-02-03 21:29:54 +01:00
Rodrigo A. Melo 665a967d87
Merge branch 'master' into master 2020-02-03 11:07:51 -03:00
Marcelina Kościelnicka 34d2fbd2f9
Add opt_lut_ins pass. (#1673) 2020-02-03 14:57:17 +01:00
Rodrigo Alejandro Melo 313a425bd5 Merge branch 'master' of https://github.com/YosysHQ/yosys 
Solved a conflict into the CHANGELOG

Signed-off-by: Rodrigo Alejandro Melo <rmelo@inti.gob.ar>
 2020-02-03 10:56:41 -03:00
David Shah ebe1d7d5ab sv: More tests for wildcard port connections 
Signed-off-by: David Shah <dave@ds0.me>
 2020-02-02 16:12:33 +00:00
David Shah 7e741714df hierarchy: Correct handling of wildcard port connections with default values 
Signed-off-by: David Shah <dave@ds0.me>
 2020-02-02 16:12:33 +00:00
David Shah a210675d71 sv: Add tests for wildcard port connections 
Signed-off-by: David Shah <dave@ds0.me>
 2020-02-02 16:12:33 +00:00
Rodrigo Alejandro Melo 8217f579b7 Removed 'synth' into tests/memfile/run-test.sh 
Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
 2020-02-02 12:34:27 -03:00
Rodrigo Alejandro Melo 9b49f1bc46 Added content1.dat into tests/memfile 
Modified run-test.sh to use it.

Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
 2020-02-02 12:18:34 -03:00
David Shah 9f5613100b
Merge pull request #1647 from YosysHQ/dave/sprintf 
ast: Add support for $sformatf system function
 2020-02-02 14:53:46 +00:00
Rodrigo Alejandro Melo eaaba6e091 Added tests/memfile to 'make test' with an extra testcase 
Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
 2020-02-01 22:44:06 -03:00
Rodrigo Alejandro Melo 43396fae2c Added a test for the Memory Content File inclusion using $readmemb 
Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
 2020-02-01 17:41:10 -03:00
Eddie Hung 136842b1ef Merge branch 'master' into eddie/submod_po 2020-02-01 02:14:19 -08:00
Miodrag Milanović 71d148bcaa
Merge pull request #1559 from YosysHQ/efinix_test_fix 
Fix for non-deterministic test
 2020-01-29 11:18:06 +01:00
Eddie Hung d004953772 Add "help -all" and "help -celltypes" sanity test 2020-01-28 18:11:34 -08:00
Eddie Hung a855f23f22 Merge remote-tracking branch 'origin/master' into eddie/opt_merge_init 2020-01-28 12:46:18 -08:00
Eddie Hung 7939727d14
Merge pull request #1660 from YosysHQ/eddie/abc9_unpermute_luts 
Unpermute LUT ordering for ice40/ecp5/xilinx
 2020-01-28 11:55:51 -08:00
Miodrag Milanovic 94191a93dd Updated test to use assert-max 2020-01-28 18:26:10 +01:00
Claire Wolf 4ddaa70fd6
Merge pull request #1567 from YosysHQ/eddie/sat_init_warning 
sat: suppress 'Warning: ignoring initial value on non-register: ...' when init[i] = 1'bx
 2020-01-28 17:40:28 +01:00
N. Engelhardt 086c133ea5
Merge pull request #1573 from YosysHQ/eddie/xilinx_tristate 
synth_xilinx: error out if tristate without '-iopad'
 2020-01-28 17:24:54 +01:00
Eddie Hung cfb0366a18 Import tests from #1628 2020-01-27 13:56:16 -08:00
Eddie Hung 48f3f5213e
Merge pull request #1619 from YosysHQ/eddie/abc9_refactor 
Refactor `abc9` pass
 2020-01-27 13:29:15 -08:00
Eddie Hung af8281d2f5
Merge pull request #1656 from YosysHQ/eddie/ice40_abc9_warnings 
ice40: reduce ABC9 internal fanout warnings with a param for CI->I3
 2020-01-27 09:54:04 -08:00
Eddie Hung b178761551 ice40: reduce ABC9 internal fanout warnings with a param for CI->I3 2020-01-24 11:59:48 -08:00
Eddie Hung 2d795fb8c0 simple_abc9 tests to discard whitebox before write for sim 2020-01-23 22:07:43 -08:00
Eddie Hung dca1c806ec simple_abc9 tests to discard whitebox before write for sim 2020-01-23 19:55:11 -08:00
Eddie Hung e471b330ac abc_box_id -> abc9_box_id in test 2020-01-23 19:12:19 -08:00
Eddie Hung 11e50c0e9e Test for (* keep *)-ed abc9_box_id 2020-01-23 18:56:25 -08:00
Eddie Hung 48aec34e0d abc_box_id -> abc9_box_id in test 2020-01-23 18:53:14 -08:00
Eddie Hung 5aaa19f1ab Update tests with reduced area 2020-01-21 16:50:04 -08:00
Eddie Hung 3d9737c1bd Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor 2020-01-21 16:27:40 -08:00
Eddie Hung 8d1b736c4f Move from +/shiftx2mux.v into +/techmap.v; cleanup 2020-01-21 15:19:41 -08:00
Eddie Hung 7977574995 New techmap +/shiftx2mux.v which decomposes LSB first; better for ABC 2020-01-21 15:19:41 -08:00
Eddie Hung cd8f55a911 write_xaiger: fix for (* keep *) on flop output 2020-01-21 09:43:04 -08:00
David Shah 22c967e35e ast: Add support for $sformatf system function 
Signed-off-by: David Shah <dave@ds0.me>
 2020-01-19 21:20:17 +00:00
Eddie Hung 6a163b5ddd xilinx_dsp: another typo; move xilinx specific test 2020-01-17 17:07:03 -08:00
Eddie Hung db68e4c2a7 ice40_dsp: fix typo 2020-01-17 16:08:04 -08:00
Eddie Hung 5507c328ff Add #1644 testcase 2020-01-17 15:57:52 -08:00
Eddie Hung ad6c49fff1 ice40_dsp: add test 2020-01-17 15:38:26 -08:00
Jeff Wang 8ef5c7d48c scoped enum tests 2020-01-16 18:13:30 -05:00
Jeff Wang caf35896da enum in package test 2020-01-16 18:09:03 -05:00
Jeff Wang febe7706a2 simple enum test 2020-01-16 18:09:03 -05:00
Eddie Hung 2245afa142 More rigorous test 2020-01-16 09:15:42 -08:00
Eddie Hung 03ce2c72bb Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor 2020-01-15 16:42:16 -08:00
Eddie Hung 5918ede9bd abc9: aAdd test to check $_NOT_s are absorbed 2020-01-15 14:36:05 -08:00
Eddie Hung e30b6bbbf8 clk2fflogic: work for bit-level $_DFF_* and $_DFFSR_* 2020-01-15 09:51:31 -08:00
Eddie Hung 53a99ade9c Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor 2020-01-14 11:46:56 -08:00
Eddie Hung 61ffd2d199
Merge pull request #1633 from YosysHQ/eddie/fix_autoname 
autoname: do not rename ports
 2020-01-14 11:40:54 -08:00
Eddie Hung 9fa0e03cc9
Merge pull request #1632 from YosysHQ/eddie/fix1630 
read_aiger: uniquify wires with $aiger<autoidx> prefix
 2020-01-14 11:40:40 -08:00
Miodrag Milanović 9fbeb57bbd
Merge pull request #1623 from YosysHQ/mmicko/edif_attr 
Export wire properties in EDIF
 2020-01-14 19:19:32 +01:00
Eddie Hung 00964e999d autoname: add testcase with $-prefix-ed port 2020-01-14 10:13:03 -08:00
Eddie Hung 565d349dc9 Add #1630 testcase 2020-01-13 21:27:53 -08:00
Eddie Hung a6d4ea7463 abc9: respect (* keep *) on cells 2020-01-13 19:21:11 -08:00
Eddie Hung 9ec948f396 write_xaiger: add support and test for (* keep *) on wires 2020-01-13 19:07:55 -08:00
Eddie Hung ca2f3db53f
Merge pull request #1620 from YosysHQ/eddie/abc9_scratchpad 
abc9: add some scripts/options into "scratchpad"
 2020-01-13 09:04:20 -08:00
Eddie Hung ae619ba87a Add #1626 testcase 2020-01-12 15:21:26 -08:00
Eddie Hung c063436eea Merge remote-tracking branch 'origin/master' into eddie/abc9_scratchpad 2020-01-11 17:02:20 -08:00
Miodrag Milanovic ccfe1e5909 this one is fine 2020-01-10 15:20:50 +01:00
Miodrag Milanovic af852a0ea8 Fix tests 2020-01-10 14:48:01 +01:00
Eddie Hung a10016ccc5 Add abc9 sanity test 2020-01-09 18:17:06 -08:00
Eddie Hung 94ab3791ce Merge remote-tracking branch 'origin/master' into eddie/abc9_mfs 2020-01-07 15:44:18 -08:00
Eddie Hung 0d3f10d3cc Add testcases 2020-01-07 11:44:20 -08:00
Eddie Hung 7c878bf397 tests/aiger: write Yosys output 2020-01-07 11:44:03 -08:00
Eddie Hung 3df869cc7c Add testcase from #1459 2020-01-06 16:22:22 -08:00
Eddie Hung 6e866030c2 Combine tests to check multiple clock domains 2020-01-02 14:38:59 -08:00
Eddie Hung b454735bea Merge remote-tracking branch 'origin/master' into xaig_dff 2020-01-02 12:44:06 -08:00
Eddie Hung 9e5ff30d05
Merge pull request #1606 from YosysHQ/eddie/improve_tests 
Fix a few issues in tests/arch/*
 2020-01-01 13:31:46 -08:00
Eddie Hung 52fe1e0c44 Revert insertion of 'reg', leave note behind 2020-01-01 09:05:46 -08:00
Miodrag Milanovic a1344ec06e Added a test case 2020-01-01 16:24:30 +01:00
Eddie Hung 713484fa66 Do not do call equiv_opt when no sim model exists 2019-12-31 18:40:30 -08:00
Eddie Hung a59016b146 Fix warnings 2019-12-31 18:40:11 -08:00
Eddie Hung c082329af3 Call equiv_opt with -multiclock and -assert 2019-12-31 18:39:32 -08:00