Eddie Hung
3ac4977b70
Add +/xilinx/cells_box.v containing models for ABC boxes
2019-04-16 11:21:03 -07:00
Eddie Hung
8c6cf07acf
Revert "Add abc_box_id attribute to MUXF7/F8 cells"
...
This reverts commit 8fbbd9b129
.
2019-04-16 11:14:59 -07:00
Eddie Hung
8fbbd9b129
Add abc_box_id attribute to MUXF7/F8 cells
2019-04-15 22:25:09 -07:00
Eddie Hung
538592067e
Merge branch 'xaig' into xc7mux
2019-04-15 22:04:20 -07:00
Eddie Hung
04e466d5e4
Add support for synth_xilinx -abc9 and ignore abc9 -dress opt
2019-04-12 12:28:37 -07:00
Keith Rothman
1f9235ede5
Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra.
...
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-04-12 09:35:15 -07:00
Eddie Hung
233edf00fe
Fix cells_map.v some more
2019-04-11 10:48:14 -07:00
Eddie Hung
8658b56a08
More fine tuning
2019-04-11 10:08:05 -07:00
Eddie Hung
0ec8564099
Fix cells_map.v
2019-04-11 10:04:58 -07:00
Eddie Hung
bca3779657
Fix typo
2019-04-11 09:25:19 -07:00
Eddie Hung
87b8d29a90
Juggle opt calls in synth_xilinx
2019-04-11 09:13:39 -07:00
Eddie Hung
cd7b2de27f
WIP for cells_map.v -- maybe working?
2019-04-10 18:05:09 -07:00
Eddie Hung
3d577586fd
Try splitting $shiftx with Y_WIDTH > 1 into Y_WIDTH = 1
2019-04-10 16:15:23 -07:00
Eddie Hung
3f5dab0d09
Fix for when B_SIGNED = 1
2019-04-10 14:51:10 -07:00
Eddie Hung
32561332b2
Update doc for synth_xilinx
2019-04-10 14:48:58 -07:00
Eddie Hung
17a02df05c
ff_map.v after abc
2019-04-10 12:36:06 -07:00
Eddie Hung
1ec949d5ed
Tidy up
2019-04-10 09:02:42 -07:00
Eddie Hung
526aef9c2a
Move map_cells to before map_luts
2019-04-10 08:50:31 -07:00
Eddie Hung
e0b46eb4cb
WIP for $shiftx to wide mux
2019-04-10 08:49:55 -07:00
Eddie Hung
4dac9818bd
Update LUT delays
2019-04-10 08:49:39 -07:00
Eddie Hung
9a6da9a79a
synth_* with -retime option now calls abc with -D 1 as well
2019-04-10 08:32:53 -07:00
Eddie Hung
3e368593eb
Add cells.lut to techlibs/xilinx/
2019-04-09 14:33:37 -07:00
Eddie Hung
fd88ab5c83
synth_xilinx to call abc with -lut +/xilinx/cells.lut
2019-04-09 14:32:39 -07:00
Eddie Hung
b9e19071b8
Add delays to cells.box
2019-04-09 14:32:10 -07:00
Keith Rothman
e107ccdde8
Fix LUT6_2 definition.
...
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-04-09 11:43:19 -07:00
Eddie Hung
f2042fc7c4
synth_xilinx with abc9 to use -box
2019-04-09 11:01:46 -07:00
Eddie Hung
2ae26b986c
Add techlibs/xilinx/cells.box
2019-04-09 10:58:58 -07:00
Eddie Hung
3fc474aa73
Add support for synth_xilinx -abc9 and ignore abc9 -dress opt
2019-04-09 10:06:44 -07:00
Keith Rothman
5e0339855f
Add additional cells sim models for core 7-series primatives.
...
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-04-09 09:01:53 -07:00
Eddie Hung
1d526b7f06
Call shregmap twice -- once for variable, another for fixed
2019-04-05 17:35:49 -07:00
Eddie Hung
a5f33b5409
Move dffinit til after abc
2019-04-05 16:20:43 -07:00
Eddie Hung
0364a5d811
Merge branch 'eddie/fix_retime' into xc7srl
2019-04-05 15:46:18 -07:00
Eddie Hung
9758701574
Move techamp t:$_DFF_?N? to before abc call
2019-04-05 15:39:05 -07:00
Eddie Hung
23a6533e98
Retry
2019-04-05 15:31:54 -07:00
Eddie Hung
8b6085254a
Resolve @daveshah1 comment, update synth_xilinx help
2019-04-05 15:15:13 -07:00
Eddie Hung
ff0912c75e
synth_xilinx to techmap FFs after abc call, otherwise -retime fails
2019-04-05 14:43:06 -07:00
Eddie Hung
544843da71
techmap inside map_cells stage
2019-04-05 12:55:52 -07:00
Eddie Hung
7b7ddbdba7
Merge branch 'map_cells_before_map_luts' into xc7srl
2019-04-04 08:13:34 -07:00
Eddie Hung
e3f20b17af
Missing techmap entry in help
2019-04-04 08:13:10 -07:00
Eddie Hung
2fb02247a7
Use soft-logic, not LUT3 instantiation
2019-04-04 08:10:40 -07:00
Eddie Hung
572603409c
Merge branch 'map_cells_before_map_luts' into xc7srl
2019-04-04 07:54:42 -07:00
Eddie Hung
d9cb787391
synth_xilinx to map_cells before map_luts
2019-04-04 07:48:13 -07:00
Eddie Hung
77755b5a66
Cleanup comments
2019-04-04 07:41:40 -07:00
Eddie Hung
736e19f02d
t:$dff* -> t:$dff t:$dffe
2019-04-04 07:39:19 -07:00
Eddie Hung
0e2d929cea
-nosrl meant when -nobram
2019-04-03 08:28:07 -07:00
Eddie Hung
ff385a5ad0
Remove duplicate STARTUPE2
2019-04-03 08:14:09 -07:00
Eddie Hung
88630cd02c
Disable shregmap in synth_xilinx if -retime
2019-04-03 07:14:20 -07:00
Eddie Hung
f9fb05cf66
synth_xilinx to use shregmap with -minlen 3
2019-03-25 13:18:55 -07:00
Eddie Hung
46753cf89f
Merge remote-tracking branch 'origin/master' into xc7srl
2019-03-22 13:10:42 -07:00
David Shah
46f6a60d58
xilinx: Add keep attribute where appropriate
...
Signed-off-by: David Shah <dave@ds0.me>
2019-03-22 13:57:17 +00:00
Eddie Hung
4cc6b3e942
Add '-nosrl' option to synth_xilinx
2019-03-21 15:04:44 -07:00
Eddie Hung
81c207fb9b
Fine tune cells_map.v
2019-03-20 10:55:14 -07:00
Eddie Hung
505e4c2d59
Revert $__SHREG_ to orig; use $__XILINX_SHREG for variable length
2019-03-19 21:58:05 -07:00
Eddie Hung
5445cd4d00
Add support for variable length Xilinx SRL > 128
2019-03-19 17:44:33 -07:00
Eddie Hung
ae2a625d05
Restore original synth_xilinx commands
2019-03-19 16:14:08 -07:00
Eddie Hung
9156e18f92
Fix spacing
2019-03-19 16:12:32 -07:00
Eddie Hung
f239cb821e
Fix INIT for variable length SRs that have been bumped up one
2019-03-19 14:54:43 -07:00
Eddie Hung
24553326dd
Merge remote-tracking branch 'origin/master' into xc7srl
2019-03-19 13:11:30 -07:00
Clifford Wolf
fe1fb1336b
Add Xilinx negedge FFs to synth_xilinx dffinit call, fixes #873
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-19 20:30:28 +01:00
Eddie Hung
fadeadb8c8
Only accept <128 for variable length, only if $shiftx exclusive
2019-03-16 08:51:13 -07:00
Eddie Hung
29a8d4745e
Cleanup synth_xilinx
2019-03-15 23:01:40 -07:00
Eddie Hung
06f8f2654a
Working
2019-03-15 19:13:40 -07:00
Eddie Hung
e7ef7fa443
Reverse bits in INIT parameter for Xilinx, since MSB is shifted first
2019-03-14 09:38:42 -07:00
Eddie Hung
af5706c2a3
Misspell
2019-03-14 09:06:56 -07:00
Eddie Hung
8af9979aab
Revert "Add shregmap -init_msb_first and use in synth_xilinx"
...
This reverts commit 26ecbc1aee
.
2019-03-14 09:01:48 -07:00
Eddie Hung
f1a8e8a480
Merge remote-tracking branch 'origin/master' into xc7srl
2019-03-14 08:59:19 -07:00
Eddie Hung
26ecbc1aee
Add shregmap -init_msb_first and use in synth_xilinx
2019-03-14 08:10:02 -07:00
Eddie Hung
79b4a275ce
Fix cells_map for SRL
2019-03-14 08:09:48 -07:00
Eddie Hung
edca2f1163
Move shregmap until after first techmap
2019-03-13 17:13:52 -07:00
Eddie Hung
24f129ddfb
Refactor $__SHREG__ in cells_map.v
2019-03-13 16:17:54 -07:00
Clifford Wolf
bfcd46dbd3
Merge pull request #842 from litghost/merge_upstream
...
Changes required for VPR place and route in synth_xilinx
2019-03-05 15:33:19 -08:00
Clifford Wolf
13844c7658
Use "write_edif -pvector bra" for Xilinx EDIF files
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-05 15:16:13 -08:00
Keith Rothman
228f132ec3
Revert BRAM WRITE_MODE changes.
...
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-03-04 09:22:22 -08:00
Keith Rothman
3e16f75bc6
Revert FF models to include IS_x_INVERTED parameters.
...
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-03-01 14:41:21 -08:00
Keith Rothman
5ebeca12eb
Use singular for disabling of DRAM or BRAM inference.
...
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-03-01 14:35:14 -08:00
Keith Rothman
eccaf101d8
Modify arguments to match existing style.
...
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-03-01 12:14:27 -08:00
Keith Rothman
3090951d54
Changes required for VPR place and route synth_xilinx.
...
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-03-01 12:02:27 -08:00
Eddie Hung
1da0909662
Remove SRL16/32 from cells_xtra
2019-02-28 13:56:45 -08:00
Eddie Hung
73ddab6960
Add SRL16 and SRL32 sim models
2019-02-28 13:56:22 -08:00
Eddie Hung
8aab7fe7e6
Fix SRL16/32 techmap off-by-one
2019-02-28 13:56:00 -08:00
Eddie Hung
fe4d6898de
synth_xilinx to call shregmap with enable support
2019-02-28 11:17:13 -08:00
Eddie Hung
68f38f2ee0
synth_xilinx to use shregmap with -params too
2019-02-28 10:21:05 -08:00
Eddie Hung
c9ab18889a
synth_xilinx to now have shregmap call after dff2dffe
2019-02-28 09:32:29 -08:00
Eddie Hung
c29f0c5048
Add techmap rule for $__SHREG_DFF_P_ to SRL16/32
2019-02-28 09:31:24 -08:00
whitequark
efa278e232
Fix typographical and grammatical errors and inconsistencies.
...
The initial list of hits was generated with the codespell command
below, and each hit was evaluated and fixed manually while taking
context into consideration.
DIRS="kernel/ frontends/ backends/ passes/ techlibs/"
DIRS="${DIRS} libs/ezsat/ libs/subcircuit"
codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint
More hits were found by looking through comments and strings manually.
2019-01-02 13:12:17 +00:00
Eddie Hung
99a14b0e37
Add support for Xilinx PS7 block
2018-11-10 12:45:07 -08:00
Tim 'mithro' Ansell
b111ea1228
xilinx: Still map LUT7/LUT8 to Xilinx specific primitives.
...
Then if targeting vpr map all the Xilinx specific LUTs back into generic
Yosys LUTs.
2018-10-08 16:52:12 -07:00
Clifford Wolf
5f1fea08d5
Add inout ports to cells_xtra.v
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-10-04 11:30:55 +02:00
Tim Ansell
ad975fb694
xilinx: Adding missing inout IO port to IOBUF
2018-10-03 16:38:32 -07:00
Henner Zeller
3aa4484a3c
Consistent use of 'override' for virtual methods in derived classes.
...
o Not all derived methods were marked 'override', but it is a great
feature of C++11 that we should make use of.
o While at it: touched header files got a -*- c++ -*- for emacs to
provide support for that language.
o use YS_OVERRIDE for all override keywords (though we should probably
use the plain keyword going forward now that C++11 is established)
2018-07-20 23:51:06 -07:00
Tim 'mithro' Ansell
d6bdefd2e9
Improving vpr output support.
...
* Support output BLIF for Xilinx architectures.
* Support using .names in BLIF for Xilinx architectures.
* Use the same `NO_LUT` define in both `synth_ice40` and
`synth_xilinx`.
2018-04-18 16:55:12 -07:00
Larry Doolittle
efaef82f75
Squelch trailing whitespace, including meta-whitespace
2018-03-11 16:03:41 +01:00
Clifford Wolf
6991c132b5
Add Xilinx RAM64X1D and RAM128X1D simulation models
2018-03-07 17:31:48 +01:00
Clifford Wolf
8a69759306
Add techlibs/xilinx/lut2lut.v
2017-07-10 12:09:05 +02:00
Clifford Wolf
0bc95f1e04
Added "yosys -D" feature
2016-04-21 23:28:37 +02:00
Clifford Wolf
ff5c61b120
Added black box modules for all the 7-series design elements (as listed in ug953)
2016-03-19 11:09:10 +01:00
Clifford Wolf
a75f94ec4a
Run dffsr2dff in synth_xilinx
2016-02-13 08:20:19 +01:00
Clifford Wolf
17372d8abd
Added "abc -luts" option, Improved Xilinx logic mapping
2016-02-01 12:40:32 +01:00
Clifford Wolf
864808992b
Bugfix in Xilinx LUT mapping
2015-10-30 13:58:03 +01:00
Clifford Wolf
f42218682d
Added examples/ top-level directory
2015-10-13 15:41:20 +02:00
Clifford Wolf
924d9d6e86
Added read-enable to memory model
2015-09-25 12:23:11 +02:00
Clifford Wolf
c475deec6c
Switched to Python 3
2015-08-22 09:59:33 +02:00
Clifford Wolf
9596fe74de
Another bugfix for ice40 and xilinx brams_init make rules
2015-08-16 21:39:34 +02:00
Clifford Wolf
aedcfd6fd3
Fixed Makefile rules for generated share files
2015-08-16 21:15:07 +02:00
Clifford Wolf
e4ef000b70
Adjust makefiles to work with out-of-tree builds
...
This is based on work done by Larry Doolittle
2015-08-12 15:04:44 +02:00
Clifford Wolf
6c84341f22
Fixed trailing whitespaces
2015-07-02 11:14:30 +02:00
Clifford Wolf
c329233f0d
Added output args to synth_ice40
2015-05-26 17:08:53 +02:00
Clifford Wolf
61512b6f41
Verific build fixes
2015-05-17 08:19:52 +02:00
Clifford Wolf
3481f46d1e
Improved xilinx "bram1" test
2015-04-09 17:12:12 +02:00
Clifford Wolf
7319951145
Added memory_bram "make_outreg" feature
2015-04-09 16:08:54 +02:00
Clifford Wolf
229825e1b8
Xilinx DRAMS: RAM64X1D, RAM128X1D
2015-04-09 13:37:07 +02:00
Clifford Wolf
b00cad81d7
Towards DRAM support in Xilinx flow
2015-04-09 08:17:14 +02:00
Clifford Wolf
8520b7fbe0
Added support for initialized xilinx brams
2015-04-06 17:07:10 +02:00
Clifford Wolf
d19866615b
Added Xilinx test case for initialized brams
2015-04-06 13:27:11 +02:00
Clifford Wolf
4389d9306e
Added Xilinx bram black-box modules
2015-04-06 08:44:30 +02:00
Clifford Wolf
c52a4cdeed
Added "dffinit", Support for initialized Xilinx DFF
2015-04-04 19:00:15 +02:00
Clifford Wolf
4d34d031f9
Added "stat" to "synth" and "synth_xilinx"
2015-02-15 13:25:15 +01:00
Clifford Wolf
881dcd8af9
Added final checks to "synth" and "synth_xilinx"
2015-02-15 13:00:00 +01:00
Clifford Wolf
853e949c0e
Disabled (unused) Xilinx tristate buffers
2015-02-04 16:33:59 +01:00
Clifford Wolf
bebbf2e5a4
no support for 6-series xilinx devices
2015-02-01 23:06:44 +01:00
Clifford Wolf
3cbfa3815e
Removed old XST-based xilinx examples
2015-02-01 17:10:46 +01:00
Clifford Wolf
816fe6bbe0
Added Xilinx example for Basys3 board
2015-02-01 17:09:34 +01:00
Clifford Wolf
1b159bc955
Added missing ports and parameters to xilinx brams
2015-02-01 15:42:59 +01:00
Clifford Wolf
909a95182b
Fixed xilinx FDSE sim model
2015-01-24 11:03:22 +01:00
Clifford Wolf
d29d26f882
Various cleanups in xilinx techlib
2015-01-18 19:43:54 +01:00
Clifford Wolf
8d295730e5
Refactoring of memory_bram and xilinx brams
2015-01-18 19:05:29 +01:00
Clifford Wolf
279a18c9a3
Added synth_xilinx -retime -flatten
2015-01-17 20:47:18 +01:00
Clifford Wolf
7031231145
Added MUXCY and XORCY support to synth_xilinx
2015-01-17 15:39:54 +01:00
Clifford Wolf
dff8bd3b2a
Added dff2dffe to synth_xilinx
2015-01-16 15:49:15 +01:00
Clifford Wolf
7bde74cd2a
Added more FF types to xilinx/cells.v
2015-01-16 15:24:54 +01:00
Clifford Wolf
6b09153320
Fixed xilinx bram clock inverted config
2015-01-16 15:11:56 +01:00
Clifford Wolf
fd8c8d4fd3
Added FF cells to xilinx/cells_sim.v
2015-01-16 14:59:40 +01:00
Clifford Wolf
b197279f3c
Added Xilinx MUXF7 and MUXF8 support
2015-01-15 13:50:04 +01:00
Clifford Wolf
153d3dd4e0
Various cleanups in synth_xilinx command
2015-01-13 13:20:32 +01:00
Clifford Wolf
1d96277f5d
Added add_share_file Makefile macro
2015-01-08 00:23:18 +01:00
Clifford Wolf
38dfc5c580
added minimalistic xilinx sim models
2015-01-08 00:05:11 +01:00
Clifford Wolf
d1e38693d5
More Xilinx bram cleanups
2015-01-07 01:59:36 +01:00
Clifford Wolf
584c5f3937
Cleanups in xilinx bram descriptions
2015-01-07 01:28:18 +01:00
Clifford Wolf
08c13f635c
Xilinx RAMB36/RAMB18 memory_bram support complete
2015-01-06 23:54:33 +01:00
Clifford Wolf
ec2eef89fa
Towards Xilinx bram support
2015-01-06 23:21:52 +01:00
Clifford Wolf
7cc5192125
small fix in xilinx/brams.v
2015-01-06 17:21:18 +01:00
Clifford Wolf
9474928672
Towards Xilinx bram support
2015-01-06 15:26:33 +01:00
Clifford Wolf
4a0b3a5423
Various small improvements to synth_xilinx
2015-01-06 14:37:50 +01:00
Clifford Wolf
081e1a49f8
Towards Xilinx bram support
2015-01-06 14:26:51 +01:00
Clifford Wolf
9c7f47bbd5
Towards Xilinx bram support
2015-01-06 13:33:51 +01:00
Clifford Wolf
9ea2511fe8
Towards Xilinx bram support
2015-01-05 13:59:04 +01:00
Clifford Wolf
8898897f7b
Towards Xilinx bram support
2015-01-04 14:23:30 +01:00
Clifford Wolf
327a5d42b6
Progress in memory_bram
2014-12-31 22:50:08 +01:00
Clifford Wolf
94e6b70736
Added memory_bram (not functional yet)
2014-12-31 16:53:53 +01:00
Clifford Wolf
f9a307a50b
namespace Yosys
2014-09-27 16:17:53 +02:00
Clifford Wolf
b64b38eea2
Renamed $lut ports to follow A-Y naming scheme
2014-08-15 14:18:40 +02:00
Clifford Wolf
b17d6531c8
Added "make PRETTY=1"
2014-07-24 17:15:01 +02:00
Clifford Wolf
20175afd29
Added "techmap -share_map" option
2013-11-24 19:50:25 +01:00
Clifford Wolf
ae798d3fd5
Fixed xilinx/example_sim_counter test bench
2013-11-24 17:55:46 +01:00
Clifford Wolf
532091afcb
Added more generic _TECHMAP_ wire mechanism to techmap pass
2013-11-23 15:58:06 +01:00
James Walmsley
40b3551b45
[EXAMPLES] Ported the mojo counter example to Zynq ZED board.
...
Will be adding a tutorial on this to verilog.james.walms.co.uk in a few days.
2013-10-27 21:48:39 +01:00
Clifford Wolf
88cd2eadf5
Cleanups in xilinx examples
2013-10-27 09:58:53 +01:00
Clifford Wolf
4a3669d871
Added synth_xilinx command
2013-10-27 09:51:06 +01:00
Clifford Wolf
90b016716b
Moved simple xilinx counter sim example to subdir
2013-10-27 09:30:17 +01:00
Clifford Wolf
02f321b6fc
Xilinx mojo_counter example is now working
2013-10-27 08:21:56 +01:00
Clifford Wolf
d635f8adaa
Renamed techlibs/xilinx7 to techlibs/xilinx
2013-10-26 22:29:40 +02:00