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Author SHA1 Message Date
Tim Edwards 6bed433856 One additional small change to the signal buffer layouts to avoid 
a collision with the lower three right-hand side I/O cells that
was discovered by LVS.
 2022-10-17 15:51:43 -04:00
Mohamed Shalan c0db032dbf
Merge pull request #275 from efabless/gpio_control_block-fixes 
Gpio control block fixes
 2022-10-17 20:56:10 +02:00
Mohamed Shalan 3fbc52ecbf
Merge pull request #276 from efabless/caravel_redesign-digital_pll-fanout 
reharden!: digital_pll
 2022-10-17 20:50:01 +02:00
mo-hosni 2d147966b9 Update housekeeping views and openlane configuration 2022-10-17 11:37:24 -07:00
kareem e5d9788a43 reharden!: digital_pll 
~ enable synth buffering to fix fanout
~ add *buf_1* to no synth list
~ add attribute (* keep *) to the oscillator as dont
touch for yosys

!need to verify that the oscillator remains untouched
 2022-10-17 10:56:01 -07:00
kareem d241ca64c2 add substrateCut layer on top of gpio_logic_high in gpio_control_block 2022-10-17 10:25:04 -07:00
kareem d416d222b2 sync mag and lef with gds 2022-10-17 06:15:52 -07:00
Marwan Abbas 4421fc614d fixed DRC errors in PDN 2022-10-17 14:10:07 +02:00
kareem 394546731f update caravel pdn 
~ change pr boundary to origin to (0,0)
~ sync lef and mag with gds
 2022-10-17 03:51:21 -07:00
marwaneltoukhy 2d28c973ee added views for caravel with power routing 2022-10-16 19:08:56 -07:00
marwaneltoukhy 9fe77b5dd7 Merge branch 'caravel_redesign-top-level' of github.com:efabless/caravel into caravel_redesign-top-level 2022-10-16 18:56:57 -07:00
Marwan Abbas f699e3323c fixed DRC error and connections to spare logic block 2022-10-17 03:56:34 +02:00
marwaneltoukhy 7ec1eeb010 Merge branch 'caravel_redesign' into caravel_redesign-top-level 2022-10-16 18:39:39 -07:00
Tim Edwards 69d353f65c Corrected the verilog and the layout for the caravan version of the 
signal buffering (verilog was missing one of the buffers, and the
layout had some of the labels at the top accidentally erased).
 2022-10-16 21:06:27 -04:00
Marwan Abbas fed2eeb4ab fixed DRC error and connected wrapper 2022-10-17 02:39:32 +02:00
Marwan Abbas 37d2a9d463 connected rest of buffers to power 2022-10-17 01:15:46 +02:00
kareem 736e58186e Merge branch 'caravel_redesign-top-level' of github.com:efabless/caravel into caravel_redesign-top-level 2022-10-16 15:45:57 -07:00
kareem 2409207178 reharden: caravel 
~ add non functional blocks - like caravel_motto
 2022-10-16 15:44:27 -07:00
Tim Edwards f7e2dc80a6 Made a minor correction to the layout to remove an extra unused 
buffer.  This does not affect ongoing top-level routing work, but
is needed for LVS.
 2022-10-16 17:57:14 -04:00
Passant ae6356cf2b update caravel top-level power routing [wip] 2022-10-16 14:43:38 -07:00
kareem 704f19b6c7 reharden: caravel 
~ correct placement for spare_logic_block
~ add changes from buffering macro
 2022-10-16 12:56:41 -07:00
kareem 7ff92e121f Merge remote-tracking branch 'origin/fix_top_buffers_again' into caravel_redesign-top-level 2022-10-16 11:18:54 -07:00
Tim Edwards 48ae31205c Another change to the pin endpoint positions to make sure that they 
have at least 0.28um spacing to the next wire.  Not sure that this
is going to solve the router errors, though.
 2022-10-16 14:15:12 -04:00
kareem 2a3493ed65 Merge branch 'fix_top_buffers_again' into caravel_redesign-top-level 2022-10-16 10:03:54 -07:00
Tim Edwards c5e7c67d60 Once again. . . Rewrote the RTL verilog so that only signals 
being buffered pass through the buffer macros.  Removed the
straight-through signals from the layout, and renumbered the
vectors in the buffer cells, which no longer match the numbering
at the top level (unfortunately).
 2022-10-16 12:49:44 -04:00
kareem b9a2e697d5 Merge branch 'fix_top_buffers_again' into caravel_redesign-top-level 2022-10-16 08:00:37 -07:00
Tim Edwards 589f351dcb Additional modification to move pins up into an uncongested area 
above housekeeping, because the upper GPIO pins are in the wrong
place relative to the new GPIO signal routing below the SoC.
Added pins for the pass-through connections.  Unconnected/
unrouted OEB pins are still not present and probably should be
removed from the RTL.
 2022-10-16 10:52:53 -04:00
kareem 38e78abfd5 Merge branch 'fix_top_buffers_again' into caravel_redesign-top-level 2022-10-16 07:24:15 -07:00
Tim Edwards 43b8f9d4fe Merge branch 'caravel_redesign' into fix_top_buffers_again 
Updating to the most recent caravel_redesign branch version.
 2022-10-16 10:05:36 -04:00
kareem aa2dfe9421 Merge branch 'fix_top_buffers_again' of github.com:efabless/caravel into fix_top_buffers_again 2022-10-16 07:01:55 -07:00
kareem fc0701003c reharden: caravel 
- based on second iteration of the buffer macro
- change config with updated placement of spare logic macros
and power routing cell
 2022-10-16 06:58:46 -07:00
Tim Edwards dcc3c56b83 Some additional corrections to the gpio_signal_buffering cells. 
Corrected one instance where a buffer had incorrectly been replaced
with a decap cell.  Moved the left-hand side in by 0.6um to clear
the chip_io connections on the left-hand side.  Corrected a small
DRC error in a route position at the bottom.
 2022-10-16 09:50:20 -04:00
kareem f5a8382395 Merge branch 'caravel_redesign' into fix_top_buffers_again 2022-10-16 05:55:23 -07:00
Marwan Abbas 6c6fa6b502
Merge pull request #255 from efabless/caravel_power_routing-sync-views 
caravel_power_routing updates
 2022-10-16 14:15:19 +02:00
kareem 914971d253 + add pr boundary for caravel_power_routing 
based on feedback from tim in order to generate a lef view
with a zero origin and avoid any hacks

+ add caravel_power_routing lef
+ sync caravel_power_routing gds and mag
 2022-10-16 04:41:29 -07:00
Marwan Abbas cb051054af
Merge pull request #254 from mo-hosni/hk_without_lables 
housekeeping without labels
 2022-10-16 13:38:02 +02:00
mo-hosni 3f0bddbcc6 update openlane views 2022-10-16 03:45:30 -07:00
mo-hosni 22dde425ac add mgmt_protect views and openlane files 2022-10-16 03:14:55 -07:00
kareem 507446e719 Merge branch 'caravel_redesign' into fix_top_buffers_again 2022-10-16 02:01:52 -07:00
Tim Edwards a77a45babe Adjustments to the top level buffering cells to do various things 
like avoid obstructions in the padframe and power routing, add
decap, and separate coupling wires to reduce capacitance.
 2022-10-15 17:35:17 -04:00
mo-hosni 953eca32d1 updated power routing for mgmt_core_wrapper and mgmt_protect 2022-10-15 09:18:28 -07:00
kareem 5d5d019ea1 Revert "add buff_flash_clkrst" 
This reverts commit 2675487322.
 2022-10-15 08:47:02 -07:00
Tim Edwards 3db846b119 Fixes issues with the GPIO signal buffering by applying a bounding 
box to the layout, so that LEF and DEF positions are correct.
 2022-10-15 10:31:35 -04:00
mo-hosni 2675487322 add buff_flash_clkrst 2022-10-15 06:38:42 -07:00
Marwan Abbas 316f2dbb58
Merge pull request #238 from mo-hosni/update_mgmt_protect 
Update mgmt protect
 2022-10-15 11:27:59 +02:00
mo-hosni 3361c8787d Add mgmt_protect views and openlane files 2022-10-15 01:46:22 -07:00
passant5 8c0e4f7403
Merge branch 'caravel_redesign' into add_top_level_buffers 2022-10-15 00:28:14 +02:00
Tim Edwards 1f5a158077 Essentially the same commit as the last one, but setting the metal 
3 horizontal bus width to 0.5um, as requested, rather than 0.6um.
 2022-10-14 16:36:42 -04:00
Tim Edwards 276580feb4 Updated the metal 3 horizontal power stripes on the mgmt_protect_hv 
layout to make them 0.6um (up from 0.3um wide).
 2022-10-14 16:28:07 -04:00
Tim Edwards 92e2f5e8a4 Added layout views (.mag, GDS, DEF, and LEF) for the caravan 
variant of the top level GPIO signal buffering (module
gpio_signal_buffering_alt).
 2022-10-14 16:06:11 -04:00
Tim Edwards aff5817f30 Rewrote the layout for mgmt_protect_hv after correcting the pins, 
which had not been correctly annotated for ports and so were
marked only as plain labels, causing issues when using the cell
as a macro inside mgmt_protect.
 2022-10-14 15:11:52 -04:00
mo-hosni 0e01725608 add housekeeping views 2022-10-14 09:26:34 -07:00
kareem aadfb57609 reharden: caravel_clocking 
~ align pdn with top level
~ move spefs and sdfs output corners to signoff/*/openlane-signoff
 2022-10-14 05:24:49 -07:00
Tim Edwards 46d44793e2 Added layout for the gpio_signal_buffering module, including GDS, 
LEF, DEF, and magic views.
 2022-10-13 21:59:10 -04:00
kareem 6452f14de0 reimplement caravel with latest blocks updates and a buffer macro 2022-10-13 13:34:47 -07:00
Marwan Abbas f7299933ee
Merge pull request #217 from mo-hosni/buff_flash_clkrst 
Buff flash clkrst
 2022-10-13 20:53:18 +02:00
Marwan Abbas 14856fea6d
Merge pull request #216 from mo-hosni/housekeeping_final_views 
Housekeeping final views
 2022-10-13 20:47:09 +02:00
Marwan Abbas e72f819020
Merge pull request #210 from mo-hosni/final_views 
mgmt_protect final views
 2022-10-13 20:33:57 +02:00
Marwan Abbas 08ac55bed8
Merge pull request #214 from efabless/caravel_clocking-buffering 
Caravel clocking reharden
 2022-10-13 20:13:45 +02:00
kareem c922241c3f reharden: caravel_clocking 
+ add custom interactive script to insert a buffer on user_clk output
and have a large buffer on core_clk
~ change pdn config to match top level
~ change sdc
~ change openlane configuration
 2022-10-13 10:54:04 -07:00
mo-hosni 889aa7e308 add buff_flash_clkrst 2022-10-13 10:35:51 -07:00
mo-hosni 0389423ea6 add housekeeping 2022-10-13 10:15:05 -07:00
mo-hosni 1aaebf5cbb add mgmt_protect 2022-10-13 10:11:45 -07:00
kareem 59743f4832 change buf16 to clkbuf16 and reimplement 2022-10-13 06:54:55 -07:00
kareem d26c071594 push digital_pll gds 2022-10-13 06:24:27 -07:00
kareem 9ccb0ff2ed reharden!: caravel 
~ reimplement based on updated views of the macros
~ change interactive script to call label_macro_pins
~ extract all spef and sdf corners using timing-scripts repo

!important same work arounds as before
 2022-10-12 04:45:08 -07:00
Mohamed Shalan 98951388d0
Merge pull request #179 from efabless/chip_io_fix_ports 
Fixes the .mag, LEF, DEF, and GDS views of chip_io and chip_io_alt
 2022-10-12 11:37:24 +02:00
mo-hosni 76f8d37496 Rehardened housekeeping to fix Antenna violations. 2022-10-11 16:41:50 -07:00
Tim Edwards a2feddf714 Corrected the layout views of chip_io and chip_io_alt, which were 
missing some of the labels for the power supplies (they were
accidentally erased during layout re-work).
 2022-10-11 11:39:03 -04:00
mo-hosni df05079b6f update houskeepong powere netlst and fixed some antenna violations 2022-10-11 01:46:23 -07:00
kareem 16fba569ad updated caravel gds that was missed in the last caravel update push 2022-10-10 08:35:13 -07:00
Mohamed Hosni 40098f693e
Merge branch 'efabless:caravel_redesign' into caravel_redesign 2022-10-10 05:08:33 -07:00
Mohamed Hosni fa441babea
Merge branch 'efabless:caravel_redesign' into caravel_redesign 2022-10-10 01:24:24 -07:00
mo-hosni 7a7690ba10 Update housekeeping 2022-10-10 01:21:51 -07:00
mo-hosni 7e5891dd9f Update mgmt_protect 2022-10-10 01:19:40 -07:00
Tim Edwards 2459b3583e Updated all views of chip_io and chip_io_alt based on the abstract 
view of constant_block which was recently merged into the repository.
The constant_block instance positions and connections were modified
slightly to avoid routing over obstruction areas.
 2022-10-09 14:20:43 -04:00
Mohamed Shalan 7538c8c776
Merge pull request #161 from efabless/chip_io_rework 2022-10-09 16:31:28 +02:00
Tim Edwards eceb71ee04 Added GDS, DEF, and LEF views of both chip_io and chip_io_alt. 2022-10-08 22:24:38 -04:00
mo-hosni da9e607760 added constant_block gds 2022-10-08 12:13:09 -07:00
mo-hosni b88648bbae compress gds 2022-10-07 17:03:21 -07:00
Mohamed Hosni 5c38e38767
Merge branch 'efabless:caravel_redesign' into caravel_redesign 2022-10-07 16:52:16 -07:00
kareem 6d1d618974 reharden!: gpio_control_block 
- rtl updated
~ add one column to the right to pass placement congestion
~ density adjusted (probably has no effect)
+ manually add isosubstrate layer in mag and gds from older iterations

!important still need to run dynamic simulations
!important depends on some updates to openlane
!important need to be able to recreate using newer openlane versions
 2022-10-07 05:02:14 -07:00
mo-hosni e0695fd86e modified power routing for new mgmt_protect and housekeeping 2022-10-05 17:23:12 -07:00
mo-hosni 9c850bf94b rehardened housekeeping 2022-10-05 12:35:03 -07:00
mo-hosni fcc009e65a rehardeneded mgmt_protect 2022-10-05 12:26:24 -07:00
Marwan Abbas 8adae5acd5 Added gds to caravel_power_routing that was generated from mag file using magic 2022-10-05 19:01:59 +02:00
kareem aaa3b863e5 reharden!: gpio_control_clock 
- add met5 obs to avoid drc with the top level pdn

!important: still need to use the latest openlane to replicate
 2022-10-05 07:03:11 -07:00
kareem acf92c3460 views: update gpio_control_block gds 2022-09-27 07:42:32 -07:00
R. Timothy Edwards d882f42803
Fix the simple_por to (logically) isolate the 1.8V and 3.3V grounds. (#90) 
* Fix the simple_por to (logically) isolate the 1.8V and 3.3V grounds.
This commit does the following:
(1) Corrects the xschem simple_por schematic to separate the 1.8V and 3.3V grounds.
(2) Corrects the xschem simple_por symbol to separate the 1.8V and 3.3V grounds.
(3) Corrects the xschem testbench to connect to both grounds of simple_por.
(4) Corrects the simple_por layout to remove the 1.8V logic from the
    3.3V ground and connect it instead to the 1.8V ground.
(5) Extends the top-level power routing of caravel and caravan to
    make a better connection to the simple_por 1.8V ground.
(6) Adds an LVS script to properly check the simple_por layout against the
    xschem-generated schematic netlist.

NOTE: None of these modifications change the function of any circuit.  The
1.8V and 3.3V ground nets are only logically separated in the netlists but
share the substrate.  This fix cleanly defines the 1.8V and 3.3V grounds
within the simple_por, where they were previously mingled.  It also ensures
that the full LVS for caravel and caravan can now include the simple_por at
the transistor level and still pass.

* Updated the GDS of simple_por (previously did not remove GDS_FILE
from the .mag file and so it just overwrote the original GDS file
with itself).

* Corrected a route to simple_por in the top level of both caravel
and caravan that was shorting to the extra metals put on top of
the substrate contact across the top (bottom, in the top level)
of the simple_por layout.
 2022-05-08 22:51:29 -07:00
Kareem Farid 9ddb806293
gpio_control_block constrains fix (#69) 
Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
 2022-04-15 11:50:54 -07:00
Kareem Farid c84e1393e7
updates to top level caravel (#59) 
* REVERT ME: temporarily match simple_por pin in verilog with lef

* - update configs
- add patch file for power routing def

* - update the following caravel toplevel views
    - gl
    - mag
    - def
- add caravel power routing def

* Apply automatic changes to Manifest and README.rst

* update gl mag and def for caravel

* Revert "REVERT ME: temporarily match simple_por pin in verilog with lef"

This reverts commit b70c27c69f.

* update caravel gds

* Apply automatic changes to Manifest and README.rst

* Added text and logo cells back into the caravel top level.  Put an
isolated ground marker layer on the xres_buf layout.  Corrected
the power supply pin names on the gate level verilog netlist of
simple_por in caravel.v.  Updated the copyright block text.
Corrected DRC errors in the top level routing.

Co-authored-by: Tim Edwards <tim@opencircuitdesign.com>
 2022-04-08 09:31:33 -07:00
Kareem Farid dcebeed7e7
Mgmt protect update (#58) 
* - add openlane patch file to for input buffering workaround
- update configuration of mgmt protect

* mgmt_protect updated

* mgmt_protect updated

* remove some via3 to fix power shorts

Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
 2022-04-08 09:29:49 -07:00
Kareem Farid e3b9a99154
- update gpio_control_block config (#57) 
- update gpio_control_block views
- gitignore gds/*gds
 2022-04-08 09:27:51 -07:00
Tim Edwards 53abff5bbf This commit fixes the issue with the user ID programming block not 
getting changed by "make ship" because the build is done in a place
where the path pointer to the user_id_programming GDS still points
back to the original caravel repository, not the user project
repository.  The user_id_programming GDS was removed (no longer used),
the user_id_programming.mag file was modified to remove the path
pointer to the GDS, and the set_user_id.py script was modified to
make changes directly to the user_id_programming.mag file instead of
the GDS.  An additional method was added to the set_user_id.py script
to modify the gate-level verilog/gl/user_id_programming.v to make
the user ID correct for gate-level testbench simulations.
 2022-03-22 10:25:25 -04:00
manarabdelaty e408d08f93 [DATA] Update gpio_control_block 2021-12-24 22:53:42 +02:00
manarabdelaty 06f05bd296 [DATA] Update mgmt_protect block (lvs clean mag/gds) 2021-12-24 22:19:00 +02:00
manarabdelaty 0225f6b69c [DATA] Update mgmt_core mag/gds to add isosubstrate on the mgmt_protect_hv 2021-12-24 21:51:25 +02:00
manarabdelaty 981043cb7b [DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells 2021-12-24 21:06:58 +02:00
jeffdi 8907a3d239 adding user_project_wrapper empty files -- gds & lef 2021-12-16 13:56:36 -08:00
jeffdi 2bc184f5c1 Merge remote-tracking branch 'origin/main' into main 2021-12-16 12:29:44 -08:00
jeffdi d4e6ed5684 adding user_project_wrapper empty files -- gds & lef 2021-12-16 12:29:35 -08:00
manarabdelaty 92f1ab7ace [DATA] Update chip_io_alt.gds to match the mag view 2021-12-09 22:15:05 +02:00
manarabdelaty 2aa61e7bff [DATA] Update gpio_control_block gds to match the mag view 
- now has the substrate cut layer for isolating the two ground domains and passes LVS on the gds
 2021-12-08 15:14:04 +02:00
manarabdelaty db8cc0580b [DATA] Update GDS views for the chip_io/chip_io_alt/mgmt_protect_hv/mgmt_protect to match the mag view 2021-12-07 14:28:29 +02:00
manarabdelaty bd88221d17 [DATA] Update caravel_clocking 2021-12-07 13:36:56 +02:00
manarabdelaty 966b1f22bb [DATA] Update digital_pll 2021-12-07 13:19:02 +02:00
manarabdelaty aa766f9144 [DATA] Update caravel_clocking module 2021-12-05 19:44:28 +02:00
manarabdelaty ef1019b62a [DATA] Update caravel_clocking 2021-12-02 22:50:20 +02:00
manarabdelaty 85ad4b0e0f Merge branch 'main' of https://github.com/efabless/caravel_openframe into main 2021-12-02 21:20:59 +02:00
manarabdelaty 0067bd5b7c [DATA] Update caravel_clocking/digital_pll/housekeeping 2021-12-02 21:09:43 +02:00
jeffdi 5896df50a8 add files for seal ring 2021-12-01 22:35:39 -08:00
Jeff DiCorpo de041996a6 Merge branch 'main' of https://github.com/efabless/caravel_openframe into main 2021-12-01 17:27:24 -08:00
Jeff DiCorpo a2d5967b67 updating caravel.gds to final with mgmt core wrapper 2021-12-01 17:15:02 -08:00
jeffdi 0a09f3b5ac added missing scripts 2021-12-01 11:03:45 -08:00
manarabdelaty c4efcec989 [DATA] Update housekeeping views 2021-11-30 13:00:33 +02:00
manarabdelaty 8b1c5df909 [DATA] Update caravel_clocking module (timing clean) 2021-11-25 15:23:01 +02:00
manarabdelaty 05278ec738 [DATA] Update HK views (timing clean) 2021-11-25 12:54:22 +02:00
manarabdelaty 83e150bf25 [DATA] Add spare_logic_block 2021-11-24 20:36:23 +02:00
manarabdelaty aeffe4756a [DATA] Add caravan layout 2021-11-22 23:10:25 +02:00
manarabdelaty 38f64d08a3 [DATA] Add user_analog_project_wrapper and chip_io_alt gds/lef views 2021-11-22 23:08:25 +02:00
manarabdelaty 1c18c1dae9 [DATA] Update caravel 2021-11-20 17:28:59 +02:00
manarabdelaty 331fdee2bb [DATA] Update HK module (li1 routing: 249um) 2021-11-20 15:13:16 +02:00
manarabdelaty 5cd3843f00 [DATA] Update gpio_control_block (li1 used 2um) 2021-11-20 14:43:20 +02:00
manarabdelaty 37fb2d6766 [DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1) 2021-11-20 13:07:23 +02:00
manarabdelaty ededa9ed35 [DATA] Update caravel layout with the latest views for the mgmt_protect and mgmt_core 2021-11-19 16:51:28 +02:00
manarabdelaty 866755f228 [DATA] Update mgmt_protect mag/gds to remove the shorted power nets 2021-11-19 15:50:36 +02:00
manarabdelaty bf6ad67934 [DATA] Update gpio_control_block pin order to fix shorts at the top level 2021-11-19 13:13:24 +02:00
manarabdelaty 581a22de6a [DATA] Update mgmt_protect (removed all li1 routing ) 2021-11-19 13:11:18 +02:00
manarabdelaty 2574eada93 [DATA] Add initial caravel layout 2021-11-19 01:37:10 +02:00
manarabdelaty 61bf3c651e [DATA] Update mgmt_protect pin placement 2021-11-19 01:33:11 +02:00
manarabdelaty 53b3a9013e [DATA] Update HK pin placement 2021-11-19 01:30:14 +02:00
manarabdelaty 37a07e291b [DATA] Update digital_pll pin placement to have it align with the HK 2021-11-19 01:28:40 +02:00
manarabdelaty 1f55f46596 [DATA] Add chip_io views with the fixed clamped3 pad 2021-11-17 16:42:36 +02:00
manarabdelaty 1b300d7b59 [DATA] Add digital user project wrapper 2021-11-17 13:13:11 +02:00
manarabdelaty 098b4befb2 Add gds view for chip_io 2021-11-15 23:02:01 +02:00
manarabdelaty 46540437af [DATA] Add gds/lef/maglef/gl views for the user_id_programming block 2021-11-15 18:17:32 +02:00
manarabdelaty 10cf11fbf5 Add gds/lef views for simple_por 2021-11-15 18:08:22 +02:00
manarabdelaty 6203460f57 [DATA] Add views for xres_buf 2021-11-15 18:07:02 +02:00
manarabdelaty 72b2c724c9 [DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz 2021-11-15 15:50:43 +02:00
manarabdelaty 56f672bbd8 [DATA] Add HK views 2021-11-15 13:23:54 +02:00
manarabdelaty 89bb33fbc0 Merge branch 'main' of https://github.com/efabless/caravel_openframe into main 2021-11-08 13:35:16 +02:00
manarabdelaty bee7b4ed78 Add initial config for the digital_pll 2021-11-08 13:34:59 +02:00
Tim Edwards f53590d4b5 Split the layout of the GPIO defaults block into three versions, for the 
three parameterized values used in the RTL verilog.  Modified the
"user_defines.v" file to create verilog definitions that match the C-style
definitions from "defs.h", for convenience/simplicity.
 2021-11-06 13:28:26 -04:00
Tim Edwards 33140b67a5 Edited the gpio_defaults_block layout like the user_id_programming 
cell to have landing sites for vias on both the HI and LO pins of
each conb_1 cell, in preparation for via programming.
 2021-11-06 12:59:49 -04:00
manarabdelaty 59076d499a Update gpio_defaults_block to align the pins with the gpio_control_block 2021-11-05 23:27:32 +02:00
manarabdelaty 49c506f052 Update gpio_control_block after constrainting the clock period to be half the mgmt_core frequency 2021-11-05 18:36:43 +02:00
manarabdelaty e68664101c Update gpio_control_block 2021-11-05 16:54:55 +02:00
manarabdelaty 53b09f43d1 Add gpio_defaults_block views 2021-11-05 12:33:36 +02:00
manarabdelaty 78ce7265c1 Update gpio_control block 2021-11-04 17:58:58 +02:00
manarabdelaty cb9990f97e harden gpio_control_block 2021-11-04 16:19:12 +02:00