mirror of https://github.com/efabless/caravel.git
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
This commit is contained in:
manarabdelaty
parent
ededa9ed35
commit
37fb2d6766
File diff suppressed because it is too large
Load Diff
Binary file not shown.
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@ -12,19 +12,31 @@ MACRO caravel_clocking
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USE GROUND ;
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PORT
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LAYER met5 ;
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RECT 0.000 15.330 94.300 16.930 ;
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RECT 0.000 24.060 94.300 25.660 ;
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END
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PORT
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LAYER met5 ;
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RECT 0.000 31.705 94.300 33.305 ;
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RECT 0.000 40.960 94.300 42.560 ;
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END
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PORT
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LAYER met4 ;
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RECT 30.690 -0.240 32.290 49.200 ;
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RECT 23.270 -0.240 24.870 54.640 ;
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END
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PORT
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LAYER met4 ;
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RECT 62.185 -0.240 63.785 49.200 ;
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RECT 38.770 -0.240 40.370 54.640 ;
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END
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PORT
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LAYER met4 ;
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RECT 54.270 -0.240 55.870 54.640 ;
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END
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PORT
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LAYER met4 ;
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RECT 69.770 -0.240 71.370 54.640 ;
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END
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PORT
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LAYER met4 ;
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RECT 85.270 -0.240 86.870 54.640 ;
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END
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END VGND
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PIN VPWR
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@ -32,27 +44,35 @@ MACRO caravel_clocking
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USE POWER ;
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PORT
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LAYER met5 ;
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RECT 0.000 7.145 94.300 8.745 ;
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RECT 0.000 15.610 94.300 17.210 ;
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END
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PORT
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LAYER met5 ;
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RECT 0.000 23.520 94.300 25.120 ;
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RECT 0.000 32.510 94.300 34.110 ;
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END
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PORT
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LAYER met5 ;
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RECT 0.000 39.890 94.300 41.490 ;
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RECT 0.000 49.410 94.300 51.010 ;
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END
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PORT
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LAYER met4 ;
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RECT 14.945 -0.240 16.545 49.200 ;
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RECT 15.520 -0.240 17.120 54.640 ;
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END
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PORT
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LAYER met4 ;
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RECT 46.435 -0.240 48.035 49.200 ;
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RECT 31.020 -0.240 32.620 54.640 ;
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END
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PORT
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LAYER met4 ;
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RECT 77.930 -0.240 79.530 49.200 ;
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RECT 46.520 -0.240 48.120 54.640 ;
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END
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PORT
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LAYER met4 ;
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RECT 62.020 -0.240 63.620 54.640 ;
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END
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PORT
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LAYER met4 ;
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RECT 77.520 -0.240 79.120 54.640 ;
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END
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END VPWR
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PIN core_clk
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@ -177,6 +197,7 @@ MACRO caravel_clocking
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END user_clk
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OBS
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LAYER nwell ;
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RECT -0.190 50.265 94.490 53.095 ;
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RECT -0.190 44.825 94.490 47.655 ;
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RECT -0.190 39.385 94.490 42.215 ;
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RECT -0.190 33.945 94.490 36.775 ;
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@ -190,76 +211,73 @@ MACRO caravel_clocking
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RECT 0.145 -0.085 0.315 0.085 ;
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RECT 1.525 -0.085 1.695 0.085 ;
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RECT 7.045 -0.085 7.215 0.085 ;
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RECT 12.560 -0.055 12.680 0.055 ;
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RECT 10.735 -0.050 10.895 0.060 ;
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RECT 11.645 -0.085 11.815 0.085 ;
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RECT 13.485 -0.085 13.655 0.085 ;
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RECT 19.005 -0.085 19.175 0.085 ;
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RECT 24.525 -0.085 24.695 0.085 ;
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RECT 23.145 -0.085 23.315 0.085 ;
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RECT 26.365 -0.085 26.535 0.085 ;
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RECT 31.885 -0.085 32.055 0.085 ;
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RECT 35.575 -0.050 35.735 0.060 ;
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RECT 37.405 -0.085 37.575 0.085 ;
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RECT 28.480 -0.085 28.650 0.085 ;
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RECT 32.345 -0.085 32.515 0.085 ;
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RECT 37.875 -0.050 38.035 0.060 ;
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RECT 39.245 -0.085 39.415 0.085 ;
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RECT 42.005 -0.085 42.175 0.085 ;
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RECT 51.200 -0.055 51.320 0.055 ;
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RECT 43.845 -0.085 44.015 0.085 ;
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RECT 45.680 -0.085 45.850 0.085 ;
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RECT 46.145 -0.085 46.315 0.085 ;
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RECT 52.125 -0.085 52.295 0.085 ;
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RECT 55.350 -0.085 55.520 0.085 ;
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RECT 56.725 -0.085 56.895 0.085 ;
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RECT 62.245 -0.085 62.415 0.085 ;
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RECT 64.080 -0.055 64.200 0.055 ;
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RECT 55.345 -0.085 55.515 0.085 ;
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RECT 60.865 -0.085 61.035 0.085 ;
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RECT 65.005 -0.085 65.175 0.085 ;
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RECT 70.525 -0.085 70.695 0.085 ;
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RECT 76.045 -0.085 76.215 0.085 ;
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RECT 74.665 -0.085 74.835 0.085 ;
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RECT 77.885 -0.085 78.055 0.085 ;
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RECT 83.405 -0.085 83.575 0.085 ;
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RECT 84.785 -0.085 84.955 0.085 ;
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RECT 80.645 -0.085 80.815 0.085 ;
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RECT 88.005 -0.085 88.175 0.085 ;
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RECT 89.840 -0.055 89.960 0.055 ;
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RECT 90.775 -0.050 90.935 0.060 ;
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RECT 92.605 -0.085 92.775 0.085 ;
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RECT 90.765 -0.085 90.935 0.085 ;
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RECT 92.600 -0.055 92.720 0.055 ;
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RECT 93.985 -0.085 94.155 0.085 ;
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LAYER li1 ;
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RECT 0.000 0.085 95.075 49.045 ;
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RECT 0.000 0.085 94.300 54.485 ;
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LAYER li1 ;
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RECT 0.000 -0.085 94.300 0.085 ;
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LAYER li1 ;
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RECT 94.300 0.000 95.075 0.085 ;
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LAYER met1 ;
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RECT 0.000 0.000 95.135 49.200 ;
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RECT 0.000 -0.240 94.300 0.000 ;
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RECT 0.000 -0.240 94.300 54.640 ;
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LAYER met2 ;
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RECT 1.940 55.720 6.710 56.285 ;
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RECT 1.480 55.720 6.710 56.285 ;
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RECT 7.550 55.720 20.970 56.285 ;
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RECT 21.810 55.720 35.230 56.285 ;
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RECT 36.070 55.720 49.490 56.285 ;
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RECT 50.330 55.720 63.750 56.285 ;
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RECT 64.590 55.720 78.010 56.285 ;
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RECT 78.850 55.720 92.270 56.285 ;
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RECT 93.110 55.720 93.290 56.285 ;
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RECT 1.940 0.000 93.290 55.720 ;
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RECT 30.720 -0.240 32.260 0.000 ;
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RECT 62.215 -0.240 63.755 0.000 ;
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RECT 93.110 55.720 94.210 56.285 ;
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RECT 1.480 0.000 94.210 55.720 ;
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RECT 23.300 -0.240 24.840 0.000 ;
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RECT 38.800 -0.240 40.340 0.000 ;
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RECT 54.300 -0.240 55.840 0.000 ;
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RECT 69.800 -0.240 71.340 0.000 ;
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RECT 85.300 -0.240 86.840 0.000 ;
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LAYER met3 ;
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RECT 14.945 55.400 95.600 56.265 ;
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RECT 14.945 49.320 96.000 55.400 ;
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RECT 14.945 47.920 95.600 49.320 ;
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RECT 14.945 41.840 96.000 47.920 ;
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RECT 14.945 40.440 95.600 41.840 ;
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RECT 14.945 34.360 96.000 40.440 ;
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RECT 14.945 32.960 95.600 34.360 ;
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RECT 14.945 26.880 96.000 32.960 ;
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RECT 14.945 25.480 95.600 26.880 ;
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RECT 14.945 19.400 96.000 25.480 ;
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RECT 14.945 18.000 95.600 19.400 ;
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RECT 14.945 11.920 96.000 18.000 ;
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RECT 14.945 10.520 95.600 11.920 ;
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RECT 14.945 4.440 96.000 10.520 ;
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RECT 14.945 3.040 95.600 4.440 ;
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RECT 14.945 0.000 96.000 3.040 ;
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RECT 30.690 -0.165 32.290 0.000 ;
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RECT 62.185 -0.165 63.785 0.000 ;
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LAYER met4 ;
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RECT 48.035 -0.240 48.040 49.200 ;
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RECT 15.520 55.400 95.600 56.265 ;
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RECT 15.520 49.320 96.000 55.400 ;
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RECT 15.520 47.920 95.600 49.320 ;
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RECT 15.520 41.840 96.000 47.920 ;
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RECT 15.520 40.440 95.600 41.840 ;
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RECT 15.520 34.360 96.000 40.440 ;
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RECT 15.520 32.960 95.600 34.360 ;
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RECT 15.520 26.880 96.000 32.960 ;
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RECT 15.520 25.480 95.600 26.880 ;
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RECT 15.520 19.400 96.000 25.480 ;
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RECT 15.520 18.000 95.600 19.400 ;
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RECT 15.520 11.920 96.000 18.000 ;
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RECT 15.520 10.520 95.600 11.920 ;
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RECT 15.520 4.440 96.000 10.520 ;
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RECT 15.520 3.040 95.600 4.440 ;
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RECT 15.520 0.000 96.000 3.040 ;
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RECT 23.270 -0.165 24.870 0.000 ;
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RECT 38.770 -0.165 40.370 0.000 ;
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RECT 54.270 -0.165 55.870 0.000 ;
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RECT 69.770 -0.165 71.370 0.000 ;
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RECT 85.270 -0.165 86.870 0.000 ;
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END
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END caravel_clocking
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END LIBRARY
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40358
mag/caravel_clocking.mag
40358
mag/caravel_clocking.mag
File diff suppressed because it is too large
Load Diff
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@ -1,8 +1,9 @@
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magic
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tech sky130A
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magscale 1 2
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timestamp 1637274818
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timestamp 1637348275
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<< nwell >>
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rect -38 10053 18898 10619
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rect -38 8965 18898 9531
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rect -38 7877 18898 8443
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rect -38 6789 18898 7355
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@ -16,40 +17,34 @@ rect -38 261 18898 827
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rect 29 -17 63 17
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rect 305 -17 339 17
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rect 1409 -17 1443 17
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rect 2512 -11 2536 11
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rect 2147 -10 2179 12
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rect 2329 -17 2363 17
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rect 2697 -17 2731 17
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rect 3801 -17 3835 17
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rect 4905 -17 4939 17
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rect 4629 -17 4663 17
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rect 5273 -17 5307 17
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rect 6377 -17 6411 17
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rect 7115 -10 7147 12
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rect 7481 -17 7515 17
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rect 5696 -17 5730 17
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rect 6469 -17 6503 17
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rect 7575 -10 7607 12
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rect 7849 -17 7883 17
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rect 8401 -17 8435 17
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rect 10240 -11 10264 11
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rect 8769 -17 8803 17
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rect 9136 -17 9170 17
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rect 9229 -17 9263 17
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rect 10425 -17 10459 17
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rect 11070 -17 11104 17
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rect 11345 -17 11379 17
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rect 12449 -17 12483 17
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rect 12816 -11 12840 11
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rect 11069 -17 11103 17
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rect 12173 -17 12207 17
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rect 13001 -17 13035 17
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rect 14105 -17 14139 17
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rect 15209 -17 15243 17
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rect 14933 -17 14967 17
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rect 15577 -17 15611 17
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rect 16681 -17 16715 17
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rect 16957 -17 16991 17
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rect 16129 -17 16163 17
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rect 17601 -17 17635 17
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rect 17968 -11 17992 11
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rect 18155 -10 18187 12
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rect 18521 -17 18555 17
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rect 18153 -17 18187 17
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rect 18520 -11 18544 11
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rect 18797 -17 18831 17
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<< obsli1 >>
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rect 0 0 19015 9809
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rect 0 -17 18860 0
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rect 0 -17 18860 10897
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<< obsm1 >>
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rect 0 0 19027 9840
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rect 0 -48 18860 0
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rect 0 -48 18860 10928
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<< metal2 >>
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rect 1398 11200 1454 12000
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rect 4250 11200 4306 12000
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@ -59,17 +54,20 @@ rect 12806 11200 12862 12000
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rect 15658 11200 15714 12000
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rect 18510 11200 18566 12000
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<< obsm2 >>
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rect 388 11144 1342 11257
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rect 296 11144 1342 11257
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rect 1510 11144 4194 11257
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rect 4362 11144 7046 11257
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rect 7214 11144 9898 11257
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rect 10066 11144 12750 11257
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rect 12918 11144 15602 11257
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rect 15770 11144 18454 11257
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rect 18622 11144 18658 11257
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rect 388 0 18658 11144
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rect 6144 -48 6452 0
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rect 12443 -48 12751 0
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rect 18622 11144 18842 11257
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rect 296 0 18842 11144
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rect 4660 -48 4968 0
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rect 7760 -48 8068 0
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rect 10860 -48 11168 0
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rect 13960 -48 14268 0
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rect 17060 -48 17368 0
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<< metal3 >>
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rect 19200 11160 20000 11280
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rect 19200 9664 20000 9784
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@ -80,58 +78,74 @@ rect 19200 3680 20000 3800
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rect 19200 2184 20000 2304
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rect 19200 688 20000 808
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<< obsm3 >>
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rect 2989 11080 19120 11253
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rect 2989 9864 19200 11080
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rect 2989 9584 19120 9864
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rect 2989 8368 19200 9584
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rect 2989 8088 19120 8368
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rect 2989 6872 19200 8088
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rect 2989 6592 19120 6872
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rect 2989 5376 19200 6592
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rect 2989 5096 19120 5376
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rect 2989 3880 19200 5096
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rect 2989 3600 19120 3880
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rect 2989 2384 19200 3600
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rect 2989 2104 19120 2384
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rect 2989 888 19200 2104
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rect 2989 608 19120 888
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rect 2989 0 19200 608
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rect 6138 -33 6458 0
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rect 12437 -33 12757 0
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rect 3104 11080 19120 11253
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rect 3104 9864 19200 11080
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rect 3104 9584 19120 9864
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rect 3104 8368 19200 9584
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rect 3104 8088 19120 8368
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rect 3104 6872 19200 8088
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||||
rect 3104 6592 19120 6872
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rect 3104 5376 19200 6592
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rect 3104 5096 19120 5376
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rect 3104 3880 19200 5096
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rect 3104 3600 19120 3880
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rect 3104 2384 19200 3600
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rect 3104 2104 19120 2384
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rect 3104 888 19200 2104
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||||
rect 3104 608 19120 888
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||||
rect 3104 0 19200 608
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||||
rect 4654 -33 4974 0
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||||
rect 7754 -33 8074 0
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rect 10854 -33 11174 0
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rect 13954 -33 14274 0
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rect 17054 -33 17374 0
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<< metal4 >>
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rect 2989 -48 3309 9840
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rect 6138 -48 6458 9840
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rect 9287 -48 9607 9840
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rect 12437 -48 12757 9840
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rect 15586 -48 15906 9840
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<< obsm4 >>
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rect 9607 -48 9608 9840
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rect 3104 -48 3424 10928
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rect 4654 -48 4974 10928
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rect 6204 -48 6524 10928
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rect 7754 -48 8074 10928
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rect 9304 -48 9624 10928
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rect 10854 -48 11174 10928
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rect 12404 -48 12724 10928
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rect 13954 -48 14274 10928
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rect 15504 -48 15824 10928
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rect 17054 -48 17374 10928
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<< metal5 >>
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rect 0 7978 18860 8298
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rect 0 6341 18860 6661
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rect 0 4704 18860 5024
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rect 0 3066 18860 3386
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rect 0 1429 18860 1749
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rect 0 9882 18860 10202
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||||
rect 0 8192 18860 8512
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rect 0 6502 18860 6822
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rect 0 4812 18860 5132
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rect 0 3122 18860 3442
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<< labels >>
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rlabel metal5 s 0 3066 18860 3386 6 VGND
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rlabel metal5 s 0 4812 18860 5132 6 VGND
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port 1 nsew ground input
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rlabel metal5 s 0 6341 18860 6661 6 VGND
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rlabel metal5 s 0 8192 18860 8512 6 VGND
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port 1 nsew ground input
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rlabel metal4 s 6138 -48 6458 9840 6 VGND
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rlabel metal4 s 4654 -48 4974 10928 6 VGND
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port 1 nsew ground input
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rlabel metal4 s 12437 -48 12757 9840 6 VGND
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rlabel metal4 s 7754 -48 8074 10928 6 VGND
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port 1 nsew ground input
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rlabel metal5 s 0 1429 18860 1749 6 VPWR
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rlabel metal4 s 10854 -48 11174 10928 6 VGND
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port 1 nsew ground input
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rlabel metal4 s 13954 -48 14274 10928 6 VGND
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port 1 nsew ground input
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rlabel metal4 s 17054 -48 17374 10928 6 VGND
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port 1 nsew ground input
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rlabel metal5 s 0 3122 18860 3442 6 VPWR
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port 2 nsew power input
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rlabel metal5 s 0 4704 18860 5024 6 VPWR
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rlabel metal5 s 0 6502 18860 6822 6 VPWR
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port 2 nsew power input
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rlabel metal5 s 0 7978 18860 8298 6 VPWR
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rlabel metal5 s 0 9882 18860 10202 6 VPWR
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port 2 nsew power input
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rlabel metal4 s 2989 -48 3309 9840 6 VPWR
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rlabel metal4 s 3104 -48 3424 10928 6 VPWR
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port 2 nsew power input
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rlabel metal4 s 9287 -48 9607 9840 6 VPWR
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rlabel metal4 s 6204 -48 6524 10928 6 VPWR
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port 2 nsew power input
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rlabel metal4 s 15586 -48 15906 9840 6 VPWR
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rlabel metal4 s 9304 -48 9624 10928 6 VPWR
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port 2 nsew power input
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rlabel metal4 s 12404 -48 12724 10928 6 VPWR
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port 2 nsew power input
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rlabel metal4 s 15504 -48 15824 10928 6 VPWR
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port 2 nsew power input
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rlabel metal2 s 7102 11200 7158 12000 6 core_clk
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port 3 nsew signal output
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@ -168,7 +182,7 @@ string LEFclass BLOCK
|
|||
string FIXED_BBOX 0 0 20000 12000
|
||||
string LEFview TRUE
|
||||
string GDS_FILE /home/ma/ef/caravel_openframe/openlane/caravel_clocking/runs/caravel_clocking/results/magic/caravel_clocking.gds
|
||||
string GDS_END 1020802
|
||||
string GDS_START 357236
|
||||
string GDS_END 1066708
|
||||
string GDS_START 369068
|
||||
<< end >>
|
||||
|
||||
|
|
|
|||
|
|
@ -45,11 +45,16 @@ set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
|
|||
|
||||
set ::env(LEFT_MARGIN_MULT) 0
|
||||
set ::env(BOTTOM_MARGIN_MULT) 0
|
||||
set ::env(TOP_MARGIN_MULT) "2"
|
||||
|
||||
set ::env(CELL_PAD) 0
|
||||
|
||||
## PDN
|
||||
set ::env(FP_PDN_HPITCH) 16.9
|
||||
set ::env(FP_PDN_VPITCH) 15.5
|
||||
|
||||
## Placement
|
||||
set ::env(PL_TARGET_DENSITY) 0.94
|
||||
set ::env(PL_TARGET_DENSITY) 0.7
|
||||
|
||||
set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 1
|
||||
set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 1
|
||||
|
|
@ -60,6 +65,9 @@ set ::env(GLB_RT_ADJUSTMENT) 0
|
|||
set ::env(GLB_RT_MINLAYER) 2
|
||||
set ::env(GLB_RT_MAXLAYER) 6
|
||||
|
||||
# prevent signal routing on li1
|
||||
set ::env(GLB_RT_OBS) "li1 94.38500 0.09500 97.39500 55.21000"
|
||||
|
||||
set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) 1
|
||||
|
||||
## Diode Insertion
|
||||
|
|
|
|||
|
|
@ -1 +1 @@
|
|||
openlane 2021.09.09_03.00.48-66-gbdb1b56
|
||||
openlane 2021.09.09_03.00.48-71-ge0e6fbc
|
||||
|
|
|
|||
|
|
@ -1,2 +1,2 @@
|
|||
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
|
||||
0,/home/ma/ef/caravel_openframe/openlane/caravel_clocking,caravel_clocking,caravel_clocking,flow_completed,0h2m3s,-1,89000.0,0.006,44500.0,74.66,661.45,267,0,0,0,0,0,0,0,0,0,0,-1,5162,1877,-3.73,-5.42,-1,-5.02,-1,-24.41,-36.7,-1,-29.25,-1,2976421.0,0.0,29.23,16.28,1.81,0.0,0.0,202,252,67,117,0,0,0,200,0,0,0,0,0,0,0,4,72,71,6,36,70,0,106,90.9090909090909,11.0,10.0,DELAY 0,5,50,1,31.493333333333336,16.37333333333333,0.94,0,sky130_fd_sc_hd,0,3
|
||||
0,/home/ma/ef/caravel_openframe/openlane/caravel_clocking,caravel_clocking,caravel_clocking,flow_completed,0h2m49s,-1,89000.0,0.006,44500.0,67.18,627.26,267,0,0,0,0,0,0,0,0,0,0,-1,4950,1815,-3.73,-5.41,-1,-4.99,-1,-24.41,-36.68,-1,-28.88,-1,3295625.0,0.0,26.02,16.28,3.8,0.0,0.0,202,252,67,117,0,0,0,200,0,0,0,0,0,0,0,4,72,71,6,40,77,0,117,90.9090909090909,11.0,10.0,DELAY 0,5,50,1,15.5,16.9,0.7,0,sky130_fd_sc_hd,0,3
|
||||
|
|
|
|||
|
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Load Diff
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue