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caravel
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Merge branch 'efabless:caravel_redesign' into caravel_redesign

This commit is contained in:
Mohamed Hosni 2022-10-07 16:52:16 -07:00 committed by GitHub
parent e0695fd86e 7b271a7808
commit 5c38e38767
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GPG Key ID: 4AEE18F83AFDEB23
32 changed files with 17942 additions and 16943 deletions
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@ -1957,8 +1957,8 @@ COMPONENTS 90 ;
- gpio_control_in_2\[7\] gpio_control_block + FIXED ( 38155 3811000 ) N ;
- gpio_control_in_2\[8\] gpio_control_block + FIXED ( 38155 3595000 ) N ;
- gpio_control_in_2\[9\] gpio_control_block + FIXED ( 38155 3379000 ) N ;
- gpio_defaults_block_0\[0\] gpio_defaults_block + FIXED ( 3517335 670000 ) FN ;
- gpio_defaults_block_0\[1\] gpio_defaults_block + FIXED ( 3517335 896000 ) FN ;
- gpio_defaults_block_0 gpio_defaults_block + FIXED ( 3517335 670000 ) FN ;
- gpio_defaults_block_1 gpio_defaults_block + FIXED ( 3517335 896000 ) FN ;
- gpio_defaults_block_10 gpio_defaults_block + FIXED ( 3517335 3135000 ) FN ;
- gpio_defaults_block_11 gpio_defaults_block + FIXED ( 3517335 3360000 ) FN ;
- gpio_defaults_block_12 gpio_defaults_block + FIXED ( 3517335 3586000 ) FN ;
@ -1979,9 +1979,9 @@ COMPONENTS 90 ;
- gpio_defaults_block_27 gpio_defaults_block + FIXED ( 41835 3660000 ) N ;
- gpio_defaults_block_28 gpio_defaults_block + FIXED ( 41835 3444000 ) N ;
- gpio_defaults_block_29 gpio_defaults_block + FIXED ( 41835 3228000 ) N ;
- gpio_defaults_block_2\[0\] gpio_defaults_block + FIXED ( 3517335 1121000 ) FN ;
- gpio_defaults_block_2\[1\] gpio_defaults_block + FIXED ( 3517335 1347000 ) FN ;
- gpio_defaults_block_2\[2\] gpio_defaults_block + FIXED ( 3517335 1572000 ) FN ;
- gpio_defaults_block_2 gpio_defaults_block + FIXED ( 3517335 1121000 ) FN ;
- gpio_defaults_block_3 gpio_defaults_block + FIXED ( 3517335 1347000 ) FN ;
- gpio_defaults_block_4 gpio_defaults_block + FIXED ( 3517335 1572000 ) FN ;
- gpio_defaults_block_30 gpio_defaults_block + FIXED ( 41835 3012000 ) N ;
- gpio_defaults_block_31 gpio_defaults_block + FIXED ( 41835 2796000 ) N ;
- gpio_defaults_block_32 gpio_defaults_block + FIXED ( 41835 2158000 ) N ;
@ -3460,7 +3460,7 @@ NETS 2794 ;
NEW met4 ( 201020 3427540 ) ( * 3639020 )
NEW met3 ( 201020 3427540 ) M3M4_PR_M
NEW met3 ( 201020 3639020 ) M3M4_PR_M ;
- gpio_defaults\[0\] ( gpio_defaults_block_0\[0\] gpio_defaults[0] ) ( gpio_control_bidir_1\[0\] gpio_defaults[0] ) + USE SIGNAL
- gpio_defaults\[0\] ( gpio_defaults_block_0 gpio_defaults[0] ) ( gpio_control_bidir_1\[0\] gpio_defaults[0] ) + USE SIGNAL
+ ROUTED met2 ( 3546140 669460 0 ) ( * 670140 0 ) ;
- gpio_defaults\[100\] ( gpio_defaults_block_7 gpio_defaults[9] ) ( gpio_control_in_1a\[5\] gpio_defaults[9] ) + USE SIGNAL
+ ROUTED met2 ( 3525440 2463980 0 ) ( * 2464320 0 ) ;
@ -3482,7 +3482,7 @@ NETS 2794 ;
+ ROUTED met2 ( 3536940 2683620 0 ) ( * 2684300 0 ) ;
- gpio_defaults\[109\] ( gpio_defaults_block_8 gpio_defaults[5] ) ( gpio_control_in_1\[0\] gpio_defaults[5] ) + USE SIGNAL
+ ROUTED met2 ( 3534640 2683620 0 ) ( * 2684300 0 ) ;
- gpio_defaults\[10\] ( gpio_defaults_block_0\[0\] gpio_defaults[10] ) ( gpio_control_bidir_1\[0\] gpio_defaults[10] ) + USE SIGNAL
- gpio_defaults\[10\] ( gpio_defaults_block_0 gpio_defaults[10] ) ( gpio_control_bidir_1\[0\] gpio_defaults[10] ) + USE SIGNAL
+ ROUTED met2 ( 3523140 669460 0 ) ( * 670140 0 ) ;
- gpio_defaults\[110\] ( gpio_defaults_block_8 gpio_defaults[6] ) ( gpio_control_in_1\[0\] gpio_defaults[6] ) + USE SIGNAL
+ ROUTED met2 ( 3532340 2683620 0 ) ( * 2684300 0 ) ;
@ -3504,7 +3504,7 @@ NETS 2794 ;
+ ROUTED met2 ( 3543840 2908700 0 ) ( * 2909380 0 ) ;
- gpio_defaults\[119\] ( gpio_defaults_block_9 gpio_defaults[2] ) ( gpio_control_in_1\[1\] gpio_defaults[2] ) + USE SIGNAL
+ ROUTED met2 ( 3541540 2908700 0 ) ( * 2909380 0 ) ;
- gpio_defaults\[11\] ( gpio_defaults_block_0\[0\] gpio_defaults[11] ) ( gpio_control_bidir_1\[0\] gpio_defaults[11] ) + USE SIGNAL
- gpio_defaults\[11\] ( gpio_defaults_block_0 gpio_defaults[11] ) ( gpio_control_bidir_1\[0\] gpio_defaults[11] ) + USE SIGNAL
+ ROUTED met2 ( 3520840 669460 0 ) ( * 670140 0 ) ;
- gpio_defaults\[120\] ( gpio_defaults_block_9 gpio_defaults[3] ) ( gpio_control_in_1\[1\] gpio_defaults[3] ) + USE SIGNAL
+ ROUTED met2 ( 3539240 2908700 0 ) ( * 2909380 0 ) ;
@ -3526,7 +3526,7 @@ NETS 2794 ;
+ ROUTED met2 ( 3520840 2908700 0 ) ( * 2909380 0 ) ;
- gpio_defaults\[129\] ( gpio_defaults_block_9 gpio_defaults[12] ) ( gpio_control_in_1\[1\] gpio_defaults[12] ) + USE SIGNAL
+ ROUTED met2 ( 3518540 2908700 0 ) ( * 2909380 0 ) ;
- gpio_defaults\[12\] ( gpio_defaults_block_0\[0\] gpio_defaults[12] ) ( gpio_control_bidir_1\[0\] gpio_defaults[12] ) + USE SIGNAL
- gpio_defaults\[12\] ( gpio_defaults_block_0 gpio_defaults[12] ) ( gpio_control_bidir_1\[0\] gpio_defaults[12] ) + USE SIGNAL
+ ROUTED met2 ( 3518540 669460 0 ) ( * 670140 0 ) ;
- gpio_defaults\[130\] ( gpio_defaults_block_10 gpio_defaults[0] ) ( gpio_control_in_1\[2\] gpio_defaults[0] ) + USE SIGNAL
+ ROUTED met2 ( 3546140 3134460 0 ) ( * 3135140 0 ) ;
@ -3548,7 +3548,7 @@ NETS 2794 ;
+ ROUTED met2 ( 3527740 3134460 0 ) ( * 3135140 0 ) ;
- gpio_defaults\[139\] ( gpio_defaults_block_10 gpio_defaults[9] ) ( gpio_control_in_1\[2\] gpio_defaults[9] ) + USE SIGNAL
+ ROUTED met2 ( 3525440 3134460 0 ) ( * 3135140 0 ) ;
- gpio_defaults\[13\] ( gpio_defaults_block_0\[1\] gpio_defaults[0] ) ( gpio_control_bidir_1\[1\] gpio_defaults[0] ) + USE SIGNAL
- gpio_defaults\[13\] ( gpio_defaults_block_1 gpio_defaults[0] ) ( gpio_control_bidir_1\[1\] gpio_defaults[0] ) + USE SIGNAL
+ ROUTED met2 ( 3546140 895900 0 ) ( * 896580 0 ) ;
- gpio_defaults\[140\] ( gpio_defaults_block_10 gpio_defaults[10] ) ( gpio_control_in_1\[2\] gpio_defaults[10] ) + USE SIGNAL
+ ROUTED met2 ( 3523140 3134460 0 ) ( * 3135140 0 ) ;
@ -3570,7 +3570,7 @@ NETS 2794 ;
+ ROUTED met2 ( 3534640 3359540 0 ) ( * 3360220 0 ) ;
- gpio_defaults\[149\] ( gpio_defaults_block_11 gpio_defaults[6] ) ( gpio_control_in_1\[3\] gpio_defaults[6] ) + USE SIGNAL
+ ROUTED met2 ( 3532340 3359540 0 ) ( * 3360220 0 ) ;
- gpio_defaults\[14\] ( gpio_defaults_block_0\[1\] gpio_defaults[1] ) ( gpio_control_bidir_1\[1\] gpio_defaults[1] ) + USE SIGNAL
- gpio_defaults\[14\] ( gpio_defaults_block_1 gpio_defaults[1] ) ( gpio_control_bidir_1\[1\] gpio_defaults[1] ) + USE SIGNAL
+ ROUTED met2 ( 3543840 895900 0 ) ( * 896580 0 ) ;
- gpio_defaults\[150\] ( gpio_defaults_block_11 gpio_defaults[7] ) ( gpio_control_in_1\[3\] gpio_defaults[7] ) + USE SIGNAL
+ ROUTED met2 ( 3530040 3359540 0 ) ( * 3360220 0 ) ;
@ -3592,7 +3592,7 @@ NETS 2794 ;
+ ROUTED met2 ( 3541540 3585980 0 ) ( * 3586320 0 ) ;
- gpio_defaults\[159\] ( gpio_defaults_block_12 gpio_defaults[3] ) ( gpio_control_in_1\[4\] gpio_defaults[3] ) + USE SIGNAL
+ ROUTED met2 ( 3539240 3585980 0 ) ( * 3586320 0 ) ;
- gpio_defaults\[15\] ( gpio_defaults_block_0\[1\] gpio_defaults[2] ) ( gpio_control_bidir_1\[1\] gpio_defaults[2] ) + USE SIGNAL
- gpio_defaults\[15\] ( gpio_defaults_block_1 gpio_defaults[2] ) ( gpio_control_bidir_1\[1\] gpio_defaults[2] ) + USE SIGNAL
+ ROUTED met2 ( 3541540 895900 0 ) ( * 896580 0 ) ;
- gpio_defaults\[160\] ( gpio_defaults_block_12 gpio_defaults[4] ) ( gpio_control_in_1\[4\] gpio_defaults[4] ) + USE SIGNAL
+ ROUTED met2 ( 3536940 3585980 0 ) ( * 3586320 0 ) ;
@ -3614,7 +3614,7 @@ NETS 2794 ;
+ ROUTED met2 ( 3518540 3585980 0 ) ( * 3586320 0 ) ;
- gpio_defaults\[169\] ( gpio_defaults_block_13 gpio_defaults[0] ) ( gpio_control_in_1\[5\] gpio_defaults[0] ) + USE SIGNAL
+ ROUTED met2 ( 3546140 3810380 0 ) ( * 3811060 0 ) ;
- gpio_defaults\[16\] ( gpio_defaults_block_0\[1\] gpio_defaults[3] ) ( gpio_control_bidir_1\[1\] gpio_defaults[3] ) + USE SIGNAL
- gpio_defaults\[16\] ( gpio_defaults_block_1 gpio_defaults[3] ) ( gpio_control_bidir_1\[1\] gpio_defaults[3] ) + USE SIGNAL
+ ROUTED met2 ( 3539240 895900 0 ) ( * 896580 0 ) ;
- gpio_defaults\[170\] ( gpio_defaults_block_13 gpio_defaults[1] ) ( gpio_control_in_1\[5\] gpio_defaults[1] ) + USE SIGNAL
+ ROUTED met2 ( 3543840 3810380 0 ) ( * 3811060 0 ) ;
@ -3636,7 +3636,7 @@ NETS 2794 ;
+ ROUTED met2 ( 3525440 3810380 0 ) ( * 3811060 0 ) ;
- gpio_defaults\[179\] ( gpio_defaults_block_13 gpio_defaults[10] ) ( gpio_control_in_1\[5\] gpio_defaults[10] ) + USE SIGNAL
+ ROUTED met2 ( 3523140 3810380 0 ) ( * 3811060 0 ) ;
- gpio_defaults\[17\] ( gpio_defaults_block_0\[1\] gpio_defaults[4] ) ( gpio_control_bidir_1\[1\] gpio_defaults[4] ) + USE SIGNAL
- gpio_defaults\[17\] ( gpio_defaults_block_1 gpio_defaults[4] ) ( gpio_control_bidir_1\[1\] gpio_defaults[4] ) + USE SIGNAL
+ ROUTED met2 ( 3536940 895900 0 ) ( * 896580 0 ) ;
- gpio_defaults\[180\] ( gpio_defaults_block_13 gpio_defaults[11] ) ( gpio_control_in_1\[5\] gpio_defaults[11] ) + USE SIGNAL
+ ROUTED met2 ( 3520840 3810380 0 ) ( * 3811060 0 ) ;
@ -3658,7 +3658,7 @@ NETS 2794 ;
+ ROUTED met2 ( 3532340 4702540 0 ) ( * 4703220 0 ) ;
- gpio_defaults\[189\] ( gpio_defaults_block_14 gpio_defaults[7] ) ( gpio_control_in_1\[6\] gpio_defaults[7] ) + USE SIGNAL
+ ROUTED met2 ( 3530040 4702540 0 ) ( * 4703220 0 ) ;
- gpio_defaults\[18\] ( gpio_defaults_block_0\[1\] gpio_defaults[5] ) ( gpio_control_bidir_1\[1\] gpio_defaults[5] ) + USE SIGNAL
- gpio_defaults\[18\] ( gpio_defaults_block_1 gpio_defaults[5] ) ( gpio_control_bidir_1\[1\] gpio_defaults[5] ) + USE SIGNAL
+ ROUTED met2 ( 3534640 895900 0 ) ( * 896580 0 ) ;
- gpio_defaults\[190\] ( gpio_defaults_block_14 gpio_defaults[8] ) ( gpio_control_in_1\[6\] gpio_defaults[8] ) + USE SIGNAL
+ ROUTED met2 ( 3527740 4702540 0 ) ( * 4703220 0 ) ;
@ -3680,9 +3680,9 @@ NETS 2794 ;
+ ROUTED met2 ( 2810830 5138760 0 ) ( 2811290 * 0 ) ;
- gpio_defaults\[199\] ( gpio_defaults_block_15 gpio_defaults[4] ) ( gpio_control_in_1\[7\] gpio_defaults[4] ) + USE SIGNAL
+ ROUTED met2 ( 2810830 5136380 0 ) ( 2811290 * 0 ) ;
- gpio_defaults\[19\] ( gpio_defaults_block_0\[1\] gpio_defaults[6] ) ( gpio_control_bidir_1\[1\] gpio_defaults[6] ) + USE SIGNAL
- gpio_defaults\[19\] ( gpio_defaults_block_1 gpio_defaults[6] ) ( gpio_control_bidir_1\[1\] gpio_defaults[6] ) + USE SIGNAL
+ ROUTED met2 ( 3532340 895900 0 ) ( * 896580 0 ) ;
- gpio_defaults\[1\] ( gpio_defaults_block_0\[0\] gpio_defaults[1] ) ( gpio_control_bidir_1\[0\] gpio_defaults[1] ) + USE SIGNAL
- gpio_defaults\[1\] ( gpio_defaults_block_0 gpio_defaults[1] ) ( gpio_control_bidir_1\[0\] gpio_defaults[1] ) + USE SIGNAL
+ ROUTED met2 ( 3543840 669460 0 ) ( * 670140 0 ) ;
- gpio_defaults\[200\] ( gpio_defaults_block_15 gpio_defaults[5] ) ( gpio_control_in_1\[7\] gpio_defaults[5] ) + USE SIGNAL
+ ROUTED met2 ( 2810830 5134000 0 ) ( 2811290 * 0 ) ;
@ -3704,7 +3704,7 @@ NETS 2794 ;
+ ROUTED met2 ( 2553690 5145560 0 ) ( 2554150 * 0 ) ;
- gpio_defaults\[209\] ( gpio_defaults_block_16 gpio_defaults[1] ) ( gpio_control_in_1\[8\] gpio_defaults[1] ) + USE SIGNAL
+ ROUTED met2 ( 2553690 5143180 0 ) ( 2554150 * 0 ) ;
- gpio_defaults\[20\] ( gpio_defaults_block_0\[1\] gpio_defaults[7] ) ( gpio_control_bidir_1\[1\] gpio_defaults[7] ) + USE SIGNAL
- gpio_defaults\[20\] ( gpio_defaults_block_1 gpio_defaults[7] ) ( gpio_control_bidir_1\[1\] gpio_defaults[7] ) + USE SIGNAL
+ ROUTED met2 ( 3530040 895900 0 ) ( * 896580 0 ) ;
- gpio_defaults\[210\] ( gpio_defaults_block_16 gpio_defaults[2] ) ( gpio_control_in_1\[8\] gpio_defaults[2] ) + USE SIGNAL
+ ROUTED met2 ( 2553690 5140955 0 ) ( 2554150 * 0 ) ;
@ -3726,7 +3726,7 @@ NETS 2794 ;
+ ROUTED met2 ( 2553690 5122440 0 ) ( 2554150 * 0 ) ;
- gpio_defaults\[219\] ( gpio_defaults_block_16 gpio_defaults[11] ) ( gpio_control_in_1\[8\] gpio_defaults[11] ) + USE SIGNAL
+ ROUTED met2 ( 2553690 5120255 0 ) ( 2554150 * 0 ) ;
- gpio_defaults\[21\] ( gpio_defaults_block_0\[1\] gpio_defaults[8] ) ( gpio_control_bidir_1\[1\] gpio_defaults[8] ) + USE SIGNAL
- gpio_defaults\[21\] ( gpio_defaults_block_1 gpio_defaults[8] ) ( gpio_control_bidir_1\[1\] gpio_defaults[8] ) + USE SIGNAL
+ ROUTED met2 ( 3527740 895900 0 ) ( * 896580 0 ) ;
- gpio_defaults\[220\] ( gpio_defaults_block_16 gpio_defaults[12] ) ( gpio_control_in_1\[8\] gpio_defaults[12] ) + USE SIGNAL
+ ROUTED met2 ( 2553690 5118020 0 ) ( 2554150 * 0 ) ;
@ -3748,7 +3748,7 @@ NETS 2794 ;
+ ROUTED met2 ( 2168670 5129580 0 ) ( 2169130 * 0 ) ;
- gpio_defaults\[229\] ( gpio_defaults_block_17 gpio_defaults[8] ) ( gpio_control_in_1\[9\] gpio_defaults[8] ) + USE SIGNAL
+ ROUTED met2 ( 2168670 5127200 0 ) ( 2169130 * 0 ) ;
- gpio_defaults\[22\] ( gpio_defaults_block_0\[1\] gpio_defaults[9] ) ( gpio_control_bidir_1\[1\] gpio_defaults[9] ) + USE SIGNAL
- gpio_defaults\[22\] ( gpio_defaults_block_1 gpio_defaults[9] ) ( gpio_control_bidir_1\[1\] gpio_defaults[9] ) + USE SIGNAL
+ ROUTED met2 ( 3525440 895900 0 ) ( * 896580 0 ) ;
- gpio_defaults\[230\] ( gpio_defaults_block_17 gpio_defaults[9] ) ( gpio_control_in_1\[9\] gpio_defaults[9] ) + USE SIGNAL
+ ROUTED met2 ( 2168670 5124820 0 ) ( 2169130 * 0 ) ;
@ -3772,7 +3772,7 @@ NETS 2794 ;
+ ROUTED met2 ( 1831950 5136380 0 ) ( 1832410 * 0 ) ;
- gpio_defaults\[239\] ( gpio_defaults_block_18 gpio_defaults[5] ) ( gpio_control_in_1\[10\] gpio_defaults[5] ) + USE SIGNAL
+ ROUTED met2 ( 1831950 5134000 0 ) ( 1832410 * 0 ) ;
- gpio_defaults\[23\] ( gpio_defaults_block_0\[1\] gpio_defaults[10] ) ( gpio_control_bidir_1\[1\] gpio_defaults[10] ) + USE SIGNAL
- gpio_defaults\[23\] ( gpio_defaults_block_1 gpio_defaults[10] ) ( gpio_control_bidir_1\[1\] gpio_defaults[10] ) + USE SIGNAL
+ ROUTED met2 ( 3523140 895900 0 ) ( * 896580 0 ) ;
- gpio_defaults\[240\] ( gpio_defaults_block_18 gpio_defaults[6] ) ( gpio_control_in_1\[10\] gpio_defaults[6] ) + USE SIGNAL
+ ROUTED met2 ( 1831490 5130940 ) ( * 5131620 0 )
@ -3803,7 +3803,7 @@ NETS 2794 ;
- gpio_defaults\[249\] ( gpio_defaults_block_19 gpio_defaults[2] ) ( gpio_control_in_2\[0\] gpio_defaults[2] ) + USE SIGNAL
+ ROUTED met2 ( 1579870 5140955 0 ) ( 1580100 * )
NEW met2 ( 1580100 5140955 ) ( 1580330 * 0 ) ;
- gpio_defaults\[24\] ( gpio_defaults_block_0\[1\] gpio_defaults[11] ) ( gpio_control_bidir_1\[1\] gpio_defaults[11] ) + USE SIGNAL
- gpio_defaults\[24\] ( gpio_defaults_block_1 gpio_defaults[11] ) ( gpio_control_bidir_1\[1\] gpio_defaults[11] ) + USE SIGNAL
+ ROUTED met2 ( 3520840 895900 0 ) ( * 896580 0 ) ;
- gpio_defaults\[250\] ( gpio_defaults_block_19 gpio_defaults[3] ) ( gpio_control_in_2\[0\] gpio_defaults[3] ) + USE SIGNAL
+ ROUTED met2 ( 1579870 5138760 0 ) ( 1580100 * )
@ -3835,7 +3835,7 @@ NETS 2794 ;
- gpio_defaults\[259\] ( gpio_defaults_block_19 gpio_defaults[12] ) ( gpio_control_in_2\[0\] gpio_defaults[12] ) + USE SIGNAL
+ ROUTED met2 ( 1579870 5118020 0 ) ( 1580100 * )
NEW met2 ( 1580100 5118020 ) ( 1580330 * 0 ) ;
- gpio_defaults\[25\] ( gpio_defaults_block_0\[1\] gpio_defaults[12] ) ( gpio_control_bidir_1\[1\] gpio_defaults[12] ) + USE SIGNAL
- gpio_defaults\[25\] ( gpio_defaults_block_1 gpio_defaults[12] ) ( gpio_control_bidir_1\[1\] gpio_defaults[12] ) + USE SIGNAL
+ ROUTED met2 ( 3518540 895900 0 ) ( * 896580 0 ) ;
- gpio_defaults\[260\] ( gpio_defaults_block_20 gpio_defaults[0] ) ( gpio_control_in_2\[1\] gpio_defaults[0] ) + USE SIGNAL
+ ROUTED met2 ( 1321810 5145560 0 ) ( 1322270 * 0 ) ;
@ -3857,7 +3857,7 @@ NETS 2794 ;
+ ROUTED met2 ( 1321810 5127200 0 ) ( 1322270 * 0 ) ;
- gpio_defaults\[269\] ( gpio_defaults_block_20 gpio_defaults[9] ) ( gpio_control_in_2\[1\] gpio_defaults[9] ) + USE SIGNAL
+ ROUTED met2 ( 1321810 5124820 0 ) ( 1322270 * 0 ) ;
- gpio_defaults\[26\] ( gpio_defaults_block_2\[0\] gpio_defaults[0] ) ( gpio_control_in_1a\[0\] gpio_defaults[0] ) + USE SIGNAL
- gpio_defaults\[26\] ( gpio_defaults_block_2 gpio_defaults[0] ) ( gpio_control_in_1a\[0\] gpio_defaults[0] ) + USE SIGNAL
+ ROUTED met2 ( 3546140 1120980 0 ) ( * 1121320 0 ) ;
- gpio_defaults\[270\] ( gpio_defaults_block_20 gpio_defaults[10] ) ( gpio_control_in_2\[1\] gpio_defaults[10] ) + USE SIGNAL
+ ROUTED met2 ( 1321810 5122440 0 ) ( 1322270 * 0 ) ;
@ -3879,7 +3879,7 @@ NETS 2794 ;
+ ROUTED met2 ( 1064670 5134000 0 ) ( 1065130 * 0 ) ;
- gpio_defaults\[279\] ( gpio_defaults_block_21 gpio_defaults[6] ) ( gpio_control_in_2\[2\] gpio_defaults[6] ) + USE SIGNAL
+ ROUTED met2 ( 1064670 5131620 0 ) ( 1065130 * 0 ) ;
- gpio_defaults\[27\] ( gpio_defaults_block_2\[0\] gpio_defaults[1] ) ( gpio_control_in_1a\[0\] gpio_defaults[1] ) + USE SIGNAL
- gpio_defaults\[27\] ( gpio_defaults_block_2 gpio_defaults[1] ) ( gpio_control_in_1a\[0\] gpio_defaults[1] ) + USE SIGNAL
+ ROUTED met2 ( 3543840 1120980 0 ) ( * 1121320 0 ) ;
- gpio_defaults\[280\] ( gpio_defaults_block_21 gpio_defaults[7] ) ( gpio_control_in_2\[2\] gpio_defaults[7] ) + USE SIGNAL
+ ROUTED met2 ( 1064670 5129580 0 ) ( 1065130 * 0 ) ;
@ -3897,7 +3897,7 @@ NETS 2794 ;
- gpio_defaults\[287\] ( gpio_defaults_block_22 gpio_defaults[1] ) ( gpio_control_in_2\[3\] gpio_defaults[1] ) + USE SIGNAL ;
- gpio_defaults\[288\] ( gpio_defaults_block_22 gpio_defaults[2] ) ( gpio_control_in_2\[3\] gpio_defaults[2] ) + USE SIGNAL ;
- gpio_defaults\[289\] ( gpio_defaults_block_22 gpio_defaults[3] ) ( gpio_control_in_2\[3\] gpio_defaults[3] ) + USE SIGNAL ;
- gpio_defaults\[28\] ( gpio_defaults_block_2\[0\] gpio_defaults[2] ) ( gpio_control_in_1a\[0\] gpio_defaults[2] ) + USE SIGNAL
- gpio_defaults\[28\] ( gpio_defaults_block_2 gpio_defaults[2] ) ( gpio_control_in_1a\[0\] gpio_defaults[2] ) + USE SIGNAL
+ ROUTED met2 ( 3541540 1120980 0 ) ( * 1121320 0 ) ;
- gpio_defaults\[290\] ( gpio_defaults_block_22 gpio_defaults[4] ) ( gpio_control_in_2\[3\] gpio_defaults[4] ) + USE SIGNAL ;
- gpio_defaults\[291\] ( gpio_defaults_block_22 gpio_defaults[5] ) ( gpio_control_in_2\[3\] gpio_defaults[5] ) + USE SIGNAL ;
@ -3910,9 +3910,9 @@ NETS 2794 ;
- gpio_defaults\[298\] ( gpio_defaults_block_22 gpio_defaults[12] ) ( gpio_control_in_2\[3\] gpio_defaults[12] ) + USE SIGNAL ;
- gpio_defaults\[299\] ( gpio_defaults_block_23 gpio_defaults[0] ) ( gpio_control_in_2\[4\] gpio_defaults[0] ) + USE SIGNAL
+ ROUTED met2 ( 550850 5145560 0 ) ( 551310 * 0 ) ;
- gpio_defaults\[29\] ( gpio_defaults_block_2\[0\] gpio_defaults[3] ) ( gpio_control_in_1a\[0\] gpio_defaults[3] ) + USE SIGNAL
- gpio_defaults\[29\] ( gpio_defaults_block_2 gpio_defaults[3] ) ( gpio_control_in_1a\[0\] gpio_defaults[3] ) + USE SIGNAL
+ ROUTED met2 ( 3539240 1120980 0 ) ( * 1121320 0 ) ;
- gpio_defaults\[2\] ( gpio_defaults_block_0\[0\] gpio_defaults[2] ) ( gpio_control_bidir_1\[0\] gpio_defaults[2] ) + USE SIGNAL
- gpio_defaults\[2\] ( gpio_defaults_block_0 gpio_defaults[2] ) ( gpio_control_bidir_1\[0\] gpio_defaults[2] ) + USE SIGNAL
+ ROUTED met2 ( 3541540 669460 0 ) ( * 670140 0 ) ;
- gpio_defaults\[300\] ( gpio_defaults_block_23 gpio_defaults[1] ) ( gpio_control_in_2\[4\] gpio_defaults[1] ) + USE SIGNAL
+ ROUTED met2 ( 550850 5143180 0 ) ( 551310 * 0 ) ;
@ -3934,7 +3934,7 @@ NETS 2794 ;
+ ROUTED met2 ( 550850 5124820 0 ) ( 551310 * 0 ) ;
- gpio_defaults\[309\] ( gpio_defaults_block_23 gpio_defaults[10] ) ( gpio_control_in_2\[4\] gpio_defaults[10] ) + USE SIGNAL
+ ROUTED met2 ( 550850 5122440 0 ) ( 551310 * 0 ) ;
- gpio_defaults\[30\] ( gpio_defaults_block_2\[0\] gpio_defaults[4] ) ( gpio_control_in_1a\[0\] gpio_defaults[4] ) + USE SIGNAL
- gpio_defaults\[30\] ( gpio_defaults_block_2 gpio_defaults[4] ) ( gpio_control_in_1a\[0\] gpio_defaults[4] ) + USE SIGNAL
+ ROUTED met2 ( 3536940 1120980 0 ) ( * 1121320 0 ) ;
- gpio_defaults\[310\] ( gpio_defaults_block_23 gpio_defaults[11] ) ( gpio_control_in_2\[4\] gpio_defaults[11] ) + USE SIGNAL
+ ROUTED met2 ( 550850 5120255 0 ) ( 551310 * 0 ) ;
@ -3956,7 +3956,7 @@ NETS 2794 ;
+ ROUTED met2 ( 56810 4720900 0 ) ( * 4721580 0 ) ;
- gpio_defaults\[319\] ( gpio_defaults_block_24 gpio_defaults[7] ) ( gpio_control_in_2\[5\] gpio_defaults[7] ) + USE SIGNAL
+ ROUTED met2 ( 59110 4720900 0 ) ( * 4721580 0 ) ;
- gpio_defaults\[31\] ( gpio_defaults_block_2\[0\] gpio_defaults[5] ) ( gpio_control_in_1a\[0\] gpio_defaults[5] ) + USE SIGNAL
- gpio_defaults\[31\] ( gpio_defaults_block_2 gpio_defaults[5] ) ( gpio_control_in_1a\[0\] gpio_defaults[5] ) + USE SIGNAL
+ ROUTED met2 ( 3534640 1120980 0 ) ( * 1121320 0 ) ;
- gpio_defaults\[320\] ( gpio_defaults_block_24 gpio_defaults[8] ) ( gpio_control_in_2\[5\] gpio_defaults[8] ) + USE SIGNAL
+ ROUTED met2 ( 61410 4720900 0 ) ( * 4721580 0 ) ;
@ -3978,7 +3978,7 @@ NETS 2794 ;
+ ROUTED met2 ( 49910 4091900 0 ) ( * 4092580 0 ) ;
- gpio_defaults\[329\] ( gpio_defaults_block_25 gpio_defaults[4] ) ( gpio_control_in_2\[6\] gpio_defaults[4] ) + USE SIGNAL
+ ROUTED met2 ( 52210 4091900 0 ) ( * 4092580 0 ) ;
- gpio_defaults\[32\] ( gpio_defaults_block_2\[0\] gpio_defaults[6] ) ( gpio_control_in_1a\[0\] gpio_defaults[6] ) + USE SIGNAL
- gpio_defaults\[32\] ( gpio_defaults_block_2 gpio_defaults[6] ) ( gpio_control_in_1a\[0\] gpio_defaults[6] ) + USE SIGNAL
+ ROUTED met2 ( 3532340 1120980 0 ) ( * 1121320 0 ) ;
- gpio_defaults\[330\] ( gpio_defaults_block_25 gpio_defaults[5] ) ( gpio_control_in_2\[6\] gpio_defaults[5] ) + USE SIGNAL
+ ROUTED met2 ( 54510 4091900 0 ) ( * 4092580 0 ) ;
@ -4000,7 +4000,7 @@ NETS 2794 ;
+ ROUTED met2 ( 43010 3875660 0 ) ( * 3876340 0 ) ;
- gpio_defaults\[339\] ( gpio_defaults_block_26 gpio_defaults[1] ) ( gpio_control_in_2\[7\] gpio_defaults[1] ) + USE SIGNAL
+ ROUTED met2 ( 45310 3875660 0 ) ( * 3876340 0 ) ;
- gpio_defaults\[33\] ( gpio_defaults_block_2\[0\] gpio_defaults[7] ) ( gpio_control_in_1a\[0\] gpio_defaults[7] ) + USE SIGNAL
- gpio_defaults\[33\] ( gpio_defaults_block_2 gpio_defaults[7] ) ( gpio_control_in_1a\[0\] gpio_defaults[7] ) + USE SIGNAL
+ ROUTED met2 ( 3530040 1120980 0 ) ( * 1121320 0 ) ;
- gpio_defaults\[340\] ( gpio_defaults_block_26 gpio_defaults[2] ) ( gpio_control_in_2\[7\] gpio_defaults[2] ) + USE SIGNAL
+ ROUTED met2 ( 47610 3875660 0 ) ( * 3876340 0 ) ;
@ -4022,7 +4022,7 @@ NETS 2794 ;
+ ROUTED met2 ( 66010 3875660 0 ) ( * 3876340 0 ) ;
- gpio_defaults\[349\] ( gpio_defaults_block_26 gpio_defaults[11] ) ( gpio_control_in_2\[7\] gpio_defaults[11] ) + USE SIGNAL
+ ROUTED met2 ( 68310 3875660 0 ) ( * 3876340 0 ) ;
- gpio_defaults\[34\] ( gpio_defaults_block_2\[0\] gpio_defaults[8] ) ( gpio_control_in_1a\[0\] gpio_defaults[8] ) + USE SIGNAL
- gpio_defaults\[34\] ( gpio_defaults_block_2 gpio_defaults[8] ) ( gpio_control_in_1a\[0\] gpio_defaults[8] ) + USE SIGNAL
+ ROUTED met2 ( 3527740 1120980 0 ) ( * 1121320 0 ) ;
- gpio_defaults\[350\] ( gpio_defaults_block_26 gpio_defaults[12] ) ( gpio_control_in_2\[7\] gpio_defaults[12] ) + USE SIGNAL
+ ROUTED met2 ( 70610 3875660 0 ) ( * 3876340 0 ) ;
@ -4044,7 +4044,7 @@ NETS 2794 ;
+ ROUTED met2 ( 59110 3659420 0 ) ( * 3660100 0 ) ;
- gpio_defaults\[359\] ( gpio_defaults_block_27 gpio_defaults[8] ) ( gpio_control_in_2\[8\] gpio_defaults[8] ) + USE SIGNAL
+ ROUTED met2 ( 61410 3659420 0 ) ( * 3660100 0 ) ;
- gpio_defaults\[35\] ( gpio_defaults_block_2\[0\] gpio_defaults[9] ) ( gpio_control_in_1a\[0\] gpio_defaults[9] ) + USE SIGNAL
- gpio_defaults\[35\] ( gpio_defaults_block_2 gpio_defaults[9] ) ( gpio_control_in_1a\[0\] gpio_defaults[9] ) + USE SIGNAL
+ ROUTED met2 ( 3525440 1120980 0 ) ( * 1121320 0 ) ;
- gpio_defaults\[360\] ( gpio_defaults_block_27 gpio_defaults[9] ) ( gpio_control_in_2\[8\] gpio_defaults[9] ) + USE SIGNAL
+ ROUTED met2 ( 63710 3659420 0 ) ( * 3660100 0 ) ;
@ -4066,7 +4066,7 @@ NETS 2794 ;
+ ROUTED met2 ( 52210 3443860 0 ) ( * 3444540 0 ) ;
- gpio_defaults\[369\] ( gpio_defaults_block_28 gpio_defaults[5] ) ( gpio_control_in_2\[9\] gpio_defaults[5] ) + USE SIGNAL
+ ROUTED met2 ( 54510 3443860 0 ) ( * 3444540 0 ) ;
- gpio_defaults\[36\] ( gpio_defaults_block_2\[0\] gpio_defaults[10] ) ( gpio_control_in_1a\[0\] gpio_defaults[10] ) + USE SIGNAL
- gpio_defaults\[36\] ( gpio_defaults_block_2 gpio_defaults[10] ) ( gpio_control_in_1a\[0\] gpio_defaults[10] ) + USE SIGNAL
+ ROUTED met2 ( 3523140 1120980 0 ) ( * 1121320 0 ) ;
- gpio_defaults\[370\] ( gpio_defaults_block_28 gpio_defaults[6] ) ( gpio_control_in_2\[9\] gpio_defaults[6] ) + USE SIGNAL
+ ROUTED met2 ( 56810 3443860 0 ) ( * 3444540 0 ) ;
@ -4088,7 +4088,7 @@ NETS 2794 ;
+ ROUTED met2 ( 45310 3227620 0 ) ( * 3228300 0 ) ;
- gpio_defaults\[379\] ( gpio_defaults_block_29 gpio_defaults[2] ) ( gpio_control_in_2\[10\] gpio_defaults[2] ) + USE SIGNAL
+ ROUTED met2 ( 47610 3227620 0 ) ( * 3228300 0 ) ;
- gpio_defaults\[37\] ( gpio_defaults_block_2\[0\] gpio_defaults[11] ) ( gpio_control_in_1a\[0\] gpio_defaults[11] ) + USE SIGNAL
- gpio_defaults\[37\] ( gpio_defaults_block_2 gpio_defaults[11] ) ( gpio_control_in_1a\[0\] gpio_defaults[11] ) + USE SIGNAL
+ ROUTED met2 ( 3520840 1120980 0 ) ( * 1121320 0 ) ;
- gpio_defaults\[380\] ( gpio_defaults_block_29 gpio_defaults[3] ) ( gpio_control_in_2\[10\] gpio_defaults[3] ) + USE SIGNAL
+ ROUTED met2 ( 49910 3227620 0 ) ( * 3228300 0 ) ;
@ -4110,7 +4110,7 @@ NETS 2794 ;
+ ROUTED met2 ( 68310 3227620 0 ) ( * 3228300 0 ) ;
- gpio_defaults\[389\] ( gpio_defaults_block_29 gpio_defaults[12] ) ( gpio_control_in_2\[10\] gpio_defaults[12] ) + USE SIGNAL
+ ROUTED met2 ( 70610 3227620 0 ) ( * 3228300 0 ) ;
- gpio_defaults\[38\] ( gpio_defaults_block_2\[0\] gpio_defaults[12] ) ( gpio_control_in_1a\[0\] gpio_defaults[12] ) + USE SIGNAL
- gpio_defaults\[38\] ( gpio_defaults_block_2 gpio_defaults[12] ) ( gpio_control_in_1a\[0\] gpio_defaults[12] ) + USE SIGNAL
+ ROUTED met2 ( 3518540 1120980 0 ) ( * 1121320 0 ) ;
- gpio_defaults\[390\] ( gpio_defaults_block_30 gpio_defaults[0] ) ( gpio_control_in_2\[11\] gpio_defaults[0] ) + USE SIGNAL
+ ROUTED met2 ( 43010 3011380 0 ) ( * 3012060 0 ) ;
@ -4132,9 +4132,9 @@ NETS 2794 ;
+ ROUTED met2 ( 61410 3011380 0 ) ( * 3012060 0 ) ;
- gpio_defaults\[399\] ( gpio_defaults_block_30 gpio_defaults[9] ) ( gpio_control_in_2\[11\] gpio_defaults[9] ) + USE SIGNAL
+ ROUTED met2 ( 63710 3011380 0 ) ( * 3012060 0 ) ;
- gpio_defaults\[39\] ( gpio_defaults_block_2\[1\] gpio_defaults[0] ) ( gpio_control_in_1a\[1\] gpio_defaults[0] ) + USE SIGNAL
- gpio_defaults\[39\] ( gpio_defaults_block_3 gpio_defaults[0] ) ( gpio_control_in_1a\[1\] gpio_defaults[0] ) + USE SIGNAL
+ ROUTED met2 ( 3546140 1346740 0 ) ( * 1347420 0 ) ;
- gpio_defaults\[3\] ( gpio_defaults_block_0\[0\] gpio_defaults[3] ) ( gpio_control_bidir_1\[0\] gpio_defaults[3] ) + USE SIGNAL
- gpio_defaults\[3\] ( gpio_defaults_block_0 gpio_defaults[3] ) ( gpio_control_bidir_1\[0\] gpio_defaults[3] ) + USE SIGNAL
+ ROUTED met2 ( 3539240 669460 0 ) ( * 670140 0 ) ;
- gpio_defaults\[400\] ( gpio_defaults_block_30 gpio_defaults[10] ) ( gpio_control_in_2\[11\] gpio_defaults[10] ) + USE SIGNAL
+ ROUTED met2 ( 66010 3011380 0 ) ( * 3012060 0 ) ;
@ -4156,7 +4156,7 @@ NETS 2794 ;
+ ROUTED met2 ( 54510 2795820 0 ) ( * 2796500 0 ) ;
- gpio_defaults\[409\] ( gpio_defaults_block_31 gpio_defaults[6] ) ( gpio_control_in_2\[12\] gpio_defaults[6] ) + USE SIGNAL
+ ROUTED met2 ( 56810 2795820 0 ) ( * 2796500 0 ) ;
- gpio_defaults\[40\] ( gpio_defaults_block_2\[1\] gpio_defaults[1] ) ( gpio_control_in_1a\[1\] gpio_defaults[1] ) + USE SIGNAL
- gpio_defaults\[40\] ( gpio_defaults_block_3 gpio_defaults[1] ) ( gpio_control_in_1a\[1\] gpio_defaults[1] ) + USE SIGNAL
+ ROUTED met2 ( 3543840 1346740 0 ) ( * 1347420 0 ) ;
- gpio_defaults\[410\] ( gpio_defaults_block_31 gpio_defaults[7] ) ( gpio_control_in_2\[12\] gpio_defaults[7] ) + USE SIGNAL
+ ROUTED met2 ( 59110 2795820 0 ) ( * 2796500 0 ) ;
@ -4178,7 +4178,7 @@ NETS 2794 ;
+ ROUTED met2 ( 47610 2157980 0 ) ( * 2158320 0 ) ;
- gpio_defaults\[419\] ( gpio_defaults_block_32 gpio_defaults[3] ) ( gpio_control_in_2\[13\] gpio_defaults[3] ) + USE SIGNAL
+ ROUTED met2 ( 49910 2157980 0 ) ( * 2158320 0 ) ;
- gpio_defaults\[41\] ( gpio_defaults_block_2\[1\] gpio_defaults[2] ) ( gpio_control_in_1a\[1\] gpio_defaults[2] ) + USE SIGNAL
- gpio_defaults\[41\] ( gpio_defaults_block_3 gpio_defaults[2] ) ( gpio_control_in_1a\[1\] gpio_defaults[2] ) + USE SIGNAL
+ ROUTED met2 ( 3541540 1346740 0 ) ( * 1347420 0 ) ;
- gpio_defaults\[420\] ( gpio_defaults_block_32 gpio_defaults[4] ) ( gpio_control_in_2\[13\] gpio_defaults[4] ) + USE SIGNAL
+ ROUTED met2 ( 52210 2157980 0 ) ( * 2158320 0 ) ;
@ -4200,7 +4200,7 @@ NETS 2794 ;
+ ROUTED met2 ( 70610 2157980 0 ) ( * 2158320 0 ) ;
- gpio_defaults\[429\] ( gpio_defaults_block_33 gpio_defaults[0] ) ( gpio_control_in_2\[14\] gpio_defaults[0] ) + USE SIGNAL
+ ROUTED met2 ( 43010 1941740 0 ) ( * 1942420 0 ) ;
- gpio_defaults\[42\] ( gpio_defaults_block_2\[1\] gpio_defaults[3] ) ( gpio_control_in_1a\[1\] gpio_defaults[3] ) + USE SIGNAL
- gpio_defaults\[42\] ( gpio_defaults_block_3 gpio_defaults[3] ) ( gpio_control_in_1a\[1\] gpio_defaults[3] ) + USE SIGNAL
+ ROUTED met2 ( 3539240 1346740 0 ) ( * 1347420 0 ) ;
- gpio_defaults\[430\] ( gpio_defaults_block_33 gpio_defaults[1] ) ( gpio_control_in_2\[14\] gpio_defaults[1] ) + USE SIGNAL
+ ROUTED met2 ( 45310 1941740 0 ) ( * 1942420 0 ) ;
@ -4222,7 +4222,7 @@ NETS 2794 ;
+ ROUTED met2 ( 63710 1941740 0 ) ( * 1942420 0 ) ;
- gpio_defaults\[439\] ( gpio_defaults_block_33 gpio_defaults[10] ) ( gpio_control_in_2\[14\] gpio_defaults[10] ) + USE SIGNAL
+ ROUTED met2 ( 66010 1941740 0 ) ( * 1942420 0 ) ;
- gpio_defaults\[43\] ( gpio_defaults_block_2\[1\] gpio_defaults[4] ) ( gpio_control_in_1a\[1\] gpio_defaults[4] ) + USE SIGNAL
- gpio_defaults\[43\] ( gpio_defaults_block_3 gpio_defaults[4] ) ( gpio_control_in_1a\[1\] gpio_defaults[4] ) + USE SIGNAL
+ ROUTED met2 ( 3536940 1346740 0 ) ( * 1347420 0 ) ;
- gpio_defaults\[440\] ( gpio_defaults_block_33 gpio_defaults[11] ) ( gpio_control_in_2\[14\] gpio_defaults[11] ) + USE SIGNAL
+ ROUTED met2 ( 68310 1941740 0 ) ( * 1942420 0 ) ;
@ -4244,7 +4244,7 @@ NETS 2794 ;
+ ROUTED met2 ( 56810 1725500 0 ) ( * 1726180 0 ) ;
- gpio_defaults\[449\] ( gpio_defaults_block_34 gpio_defaults[7] ) ( gpio_control_in_2\[15\] gpio_defaults[7] ) + USE SIGNAL
+ ROUTED met2 ( 59110 1725500 0 ) ( * 1726180 0 ) ;
- gpio_defaults\[44\] ( gpio_defaults_block_2\[1\] gpio_defaults[5] ) ( gpio_control_in_1a\[1\] gpio_defaults[5] ) + USE SIGNAL
- gpio_defaults\[44\] ( gpio_defaults_block_3 gpio_defaults[5] ) ( gpio_control_in_1a\[1\] gpio_defaults[5] ) + USE SIGNAL
+ ROUTED met2 ( 3534640 1346740 0 ) ( * 1347420 0 ) ;
- gpio_defaults\[450\] ( gpio_defaults_block_34 gpio_defaults[8] ) ( gpio_control_in_2\[15\] gpio_defaults[8] ) + USE SIGNAL
+ ROUTED met2 ( 61410 1725500 0 ) ( * 1726180 0 ) ;
@ -4266,7 +4266,7 @@ NETS 2794 ;
+ ROUTED met2 ( 49910 1509940 0 ) ( * 1510620 0 ) ;
- gpio_defaults\[459\] ( gpio_defaults_block_35 gpio_defaults[4] ) ( gpio_control_bidir_2\[0\] gpio_defaults[4] ) + USE SIGNAL
+ ROUTED met2 ( 52210 1509940 0 ) ( * 1510620 0 ) ;
- gpio_defaults\[45\] ( gpio_defaults_block_2\[1\] gpio_defaults[6] ) ( gpio_control_in_1a\[1\] gpio_defaults[6] ) + USE SIGNAL
- gpio_defaults\[45\] ( gpio_defaults_block_3 gpio_defaults[6] ) ( gpio_control_in_1a\[1\] gpio_defaults[6] ) + USE SIGNAL
+ ROUTED met2 ( 3532340 1346740 0 ) ( * 1347420 0 ) ;
- gpio_defaults\[460\] ( gpio_defaults_block_35 gpio_defaults[5] ) ( gpio_control_bidir_2\[0\] gpio_defaults[5] ) + USE SIGNAL
+ ROUTED met2 ( 54510 1509940 0 ) ( * 1510620 0 ) ;
@ -4288,7 +4288,7 @@ NETS 2794 ;
+ ROUTED met2 ( 43010 1293700 0 ) ( * 1294380 0 ) ;
- gpio_defaults\[469\] ( gpio_defaults_block_36 gpio_defaults[1] ) ( gpio_control_bidir_2\[1\] gpio_defaults[1] ) + USE SIGNAL
+ ROUTED met2 ( 45310 1293700 0 ) ( * 1294380 0 ) ;
- gpio_defaults\[46\] ( gpio_defaults_block_2\[1\] gpio_defaults[7] ) ( gpio_control_in_1a\[1\] gpio_defaults[7] ) + USE SIGNAL
- gpio_defaults\[46\] ( gpio_defaults_block_3 gpio_defaults[7] ) ( gpio_control_in_1a\[1\] gpio_defaults[7] ) + USE SIGNAL
+ ROUTED met2 ( 3530040 1346740 0 ) ( * 1347420 0 ) ;
- gpio_defaults\[470\] ( gpio_defaults_block_36 gpio_defaults[2] ) ( gpio_control_bidir_2\[1\] gpio_defaults[2] ) + USE SIGNAL
+ ROUTED met2 ( 47610 1293700 0 ) ( * 1294380 0 ) ;
@ -4310,7 +4310,7 @@ NETS 2794 ;
+ ROUTED met2 ( 66010 1293700 0 ) ( * 1294380 0 ) ;
- gpio_defaults\[479\] ( gpio_defaults_block_36 gpio_defaults[11] ) ( gpio_control_bidir_2\[1\] gpio_defaults[11] ) + USE SIGNAL
+ ROUTED met2 ( 68310 1293700 0 ) ( * 1294380 0 ) ;
- gpio_defaults\[47\] ( gpio_defaults_block_2\[1\] gpio_defaults[8] ) ( gpio_control_in_1a\[1\] gpio_defaults[8] ) + USE SIGNAL
- gpio_defaults\[47\] ( gpio_defaults_block_3 gpio_defaults[8] ) ( gpio_control_in_1a\[1\] gpio_defaults[8] ) + USE SIGNAL
+ ROUTED met2 ( 3527740 1346740 0 ) ( * 1347420 0 ) ;
- gpio_defaults\[480\] ( gpio_defaults_block_36 gpio_defaults[12] ) ( gpio_control_bidir_2\[1\] gpio_defaults[12] ) + USE SIGNAL
+ ROUTED met2 ( 70610 1293700 0 ) ( * 1294380 0 ) ;
@ -4332,7 +4332,7 @@ NETS 2794 ;
+ ROUTED met2 ( 59110 1077460 0 ) ( * 1078140 0 ) ;
- gpio_defaults\[489\] ( gpio_defaults_block_37 gpio_defaults[8] ) ( gpio_control_bidir_2\[2\] gpio_defaults[8] ) + USE SIGNAL
+ ROUTED met2 ( 61410 1077460 0 ) ( * 1078140 0 ) ;
- gpio_defaults\[48\] ( gpio_defaults_block_2\[1\] gpio_defaults[9] ) ( gpio_control_in_1a\[1\] gpio_defaults[9] ) + USE SIGNAL
- gpio_defaults\[48\] ( gpio_defaults_block_3 gpio_defaults[9] ) ( gpio_control_in_1a\[1\] gpio_defaults[9] ) + USE SIGNAL
+ ROUTED met2 ( 3525440 1346740 0 ) ( * 1347420 0 ) ;
- gpio_defaults\[490\] ( gpio_defaults_block_37 gpio_defaults[9] ) ( gpio_control_bidir_2\[2\] gpio_defaults[9] ) + USE SIGNAL
+ ROUTED met2 ( 63710 1077460 0 ) ( * 1078140 0 ) ;
@ -4342,41 +4342,41 @@ NETS 2794 ;
+ ROUTED met2 ( 68310 1077460 0 ) ( * 1078140 0 ) ;
- gpio_defaults\[493\] ( gpio_defaults_block_37 gpio_defaults[12] ) ( gpio_control_bidir_2\[2\] gpio_defaults[12] ) + USE SIGNAL
+ ROUTED met2 ( 70610 1077460 0 ) ( * 1078140 0 ) ;
- gpio_defaults\[49\] ( gpio_defaults_block_2\[1\] gpio_defaults[10] ) ( gpio_control_in_1a\[1\] gpio_defaults[10] ) + USE SIGNAL
- gpio_defaults\[49\] ( gpio_defaults_block_3 gpio_defaults[10] ) ( gpio_control_in_1a\[1\] gpio_defaults[10] ) + USE SIGNAL
+ ROUTED met2 ( 3523140 1346740 0 ) ( * 1347420 0 ) ;
- gpio_defaults\[4\] ( gpio_defaults_block_0\[0\] gpio_defaults[4] ) ( gpio_control_bidir_1\[0\] gpio_defaults[4] ) + USE SIGNAL
- gpio_defaults\[4\] ( gpio_defaults_block_0 gpio_defaults[4] ) ( gpio_control_bidir_1\[0\] gpio_defaults[4] ) + USE SIGNAL
+ ROUTED met2 ( 3536940 669460 0 ) ( * 670140 0 ) ;
- gpio_defaults\[50\] ( gpio_defaults_block_2\[1\] gpio_defaults[11] ) ( gpio_control_in_1a\[1\] gpio_defaults[11] ) + USE SIGNAL
- gpio_defaults\[50\] ( gpio_defaults_block_3 gpio_defaults[11] ) ( gpio_control_in_1a\[1\] gpio_defaults[11] ) + USE SIGNAL
+ ROUTED met2 ( 3520840 1346740 0 ) ( * 1347420 0 ) ;
- gpio_defaults\[51\] ( gpio_defaults_block_2\[1\] gpio_defaults[12] ) ( gpio_control_in_1a\[1\] gpio_defaults[12] ) + USE SIGNAL
- gpio_defaults\[51\] ( gpio_defaults_block_3 gpio_defaults[12] ) ( gpio_control_in_1a\[1\] gpio_defaults[12] ) + USE SIGNAL
+ ROUTED met2 ( 3518540 1346740 0 ) ( * 1347420 0 ) ;
- gpio_defaults\[52\] ( gpio_defaults_block_2\[2\] gpio_defaults[0] ) ( gpio_control_in_1a\[2\] gpio_defaults[0] ) + USE SIGNAL
- gpio_defaults\[52\] ( gpio_defaults_block_4 gpio_defaults[0] ) ( gpio_control_in_1a\[2\] gpio_defaults[0] ) + USE SIGNAL
+ ROUTED met2 ( 3546140 1571820 0 ) ( * 1572500 0 ) ;
- gpio_defaults\[53\] ( gpio_defaults_block_2\[2\] gpio_defaults[1] ) ( gpio_control_in_1a\[2\] gpio_defaults[1] ) + USE SIGNAL
- gpio_defaults\[53\] ( gpio_defaults_block_4 gpio_defaults[1] ) ( gpio_control_in_1a\[2\] gpio_defaults[1] ) + USE SIGNAL
+ ROUTED met2 ( 3543840 1571820 0 ) ( * 1572500 0 ) ;
- gpio_defaults\[54\] ( gpio_defaults_block_2\[2\] gpio_defaults[2] ) ( gpio_control_in_1a\[2\] gpio_defaults[2] ) + USE SIGNAL
- gpio_defaults\[54\] ( gpio_defaults_block_4 gpio_defaults[2] ) ( gpio_control_in_1a\[2\] gpio_defaults[2] ) + USE SIGNAL
+ ROUTED met2 ( 3541540 1571820 0 ) ( * 1572500 0 ) ;
- gpio_defaults\[55\] ( gpio_defaults_block_2\[2\] gpio_defaults[3] ) ( gpio_control_in_1a\[2\] gpio_defaults[3] ) + USE SIGNAL
- gpio_defaults\[55\] ( gpio_defaults_block_4 gpio_defaults[3] ) ( gpio_control_in_1a\[2\] gpio_defaults[3] ) + USE SIGNAL
+ ROUTED met2 ( 3539240 1571820 0 ) ( * 1572500 0 ) ;
- gpio_defaults\[56\] ( gpio_defaults_block_2\[2\] gpio_defaults[4] ) ( gpio_control_in_1a\[2\] gpio_defaults[4] ) + USE SIGNAL
- gpio_defaults\[56\] ( gpio_defaults_block_4 gpio_defaults[4] ) ( gpio_control_in_1a\[2\] gpio_defaults[4] ) + USE SIGNAL
+ ROUTED met2 ( 3536940 1571820 0 ) ( * 1572500 0 ) ;
- gpio_defaults\[57\] ( gpio_defaults_block_2\[2\] gpio_defaults[5] ) ( gpio_control_in_1a\[2\] gpio_defaults[5] ) + USE SIGNAL
- gpio_defaults\[57\] ( gpio_defaults_block_4 gpio_defaults[5] ) ( gpio_control_in_1a\[2\] gpio_defaults[5] ) + USE SIGNAL
+ ROUTED met2 ( 3534640 1571820 0 ) ( * 1572500 0 ) ;
- gpio_defaults\[58\] ( gpio_defaults_block_2\[2\] gpio_defaults[6] ) ( gpio_control_in_1a\[2\] gpio_defaults[6] ) + USE SIGNAL
- gpio_defaults\[58\] ( gpio_defaults_block_4 gpio_defaults[6] ) ( gpio_control_in_1a\[2\] gpio_defaults[6] ) + USE SIGNAL
+ ROUTED met2 ( 3532340 1571820 0 ) ( * 1572500 0 ) ;
- gpio_defaults\[59\] ( gpio_defaults_block_2\[2\] gpio_defaults[7] ) ( gpio_control_in_1a\[2\] gpio_defaults[7] ) + USE SIGNAL
- gpio_defaults\[59\] ( gpio_defaults_block_4 gpio_defaults[7] ) ( gpio_control_in_1a\[2\] gpio_defaults[7] ) + USE SIGNAL
+ ROUTED met2 ( 3530040 1571820 0 ) ( * 1572500 0 ) ;
- gpio_defaults\[5\] ( gpio_defaults_block_0\[0\] gpio_defaults[5] ) ( gpio_control_bidir_1\[0\] gpio_defaults[5] ) + USE SIGNAL
- gpio_defaults\[5\] ( gpio_defaults_block_0 gpio_defaults[5] ) ( gpio_control_bidir_1\[0\] gpio_defaults[5] ) + USE SIGNAL
+ ROUTED met2 ( 3534640 669460 0 ) ( * 670140 0 ) ;
- gpio_defaults\[60\] ( gpio_defaults_block_2\[2\] gpio_defaults[8] ) ( gpio_control_in_1a\[2\] gpio_defaults[8] ) + USE SIGNAL
- gpio_defaults\[60\] ( gpio_defaults_block_4 gpio_defaults[8] ) ( gpio_control_in_1a\[2\] gpio_defaults[8] ) + USE SIGNAL
+ ROUTED met2 ( 3527740 1571820 0 ) ( * 1572500 0 ) ;
- gpio_defaults\[61\] ( gpio_defaults_block_2\[2\] gpio_defaults[9] ) ( gpio_control_in_1a\[2\] gpio_defaults[9] ) + USE SIGNAL
- gpio_defaults\[61\] ( gpio_defaults_block_4 gpio_defaults[9] ) ( gpio_control_in_1a\[2\] gpio_defaults[9] ) + USE SIGNAL
+ ROUTED met2 ( 3525440 1571820 0 ) ( * 1572500 0 ) ;
- gpio_defaults\[62\] ( gpio_defaults_block_2\[2\] gpio_defaults[10] ) ( gpio_control_in_1a\[2\] gpio_defaults[10] ) + USE SIGNAL
- gpio_defaults\[62\] ( gpio_defaults_block_4 gpio_defaults[10] ) ( gpio_control_in_1a\[2\] gpio_defaults[10] ) + USE SIGNAL
+ ROUTED met2 ( 3523140 1571820 0 ) ( * 1572500 0 ) ;
- gpio_defaults\[63\] ( gpio_defaults_block_2\[2\] gpio_defaults[11] ) ( gpio_control_in_1a\[2\] gpio_defaults[11] ) + USE SIGNAL
- gpio_defaults\[63\] ( gpio_defaults_block_4 gpio_defaults[11] ) ( gpio_control_in_1a\[2\] gpio_defaults[11] ) + USE SIGNAL
+ ROUTED met2 ( 3520840 1571820 0 ) ( * 1572500 0 ) ;
- gpio_defaults\[64\] ( gpio_defaults_block_2\[2\] gpio_defaults[12] ) ( gpio_control_in_1a\[2\] gpio_defaults[12] ) + USE SIGNAL
- gpio_defaults\[64\] ( gpio_defaults_block_4 gpio_defaults[12] ) ( gpio_control_in_1a\[2\] gpio_defaults[12] ) + USE SIGNAL
+ ROUTED met2 ( 3518540 1571820 0 ) ( * 1572500 0 ) ;
- gpio_defaults\[65\] ( gpio_defaults_block_5 gpio_defaults[0] ) ( gpio_control_in_1a\[3\] gpio_defaults[0] ) + USE SIGNAL
+ ROUTED met2 ( 3546140 1796900 0 ) ( * 1797580 0 ) ;
@ -4388,7 +4388,7 @@ NETS 2794 ;
+ ROUTED met2 ( 3539240 1796900 0 ) ( * 1797580 0 ) ;
- gpio_defaults\[69\] ( gpio_defaults_block_5 gpio_defaults[4] ) ( gpio_control_in_1a\[3\] gpio_defaults[4] ) + USE SIGNAL
+ ROUTED met2 ( 3536940 1796900 0 ) ( * 1797580 0 ) ;
- gpio_defaults\[6\] ( gpio_defaults_block_0\[0\] gpio_defaults[6] ) ( gpio_control_bidir_1\[0\] gpio_defaults[6] ) + USE SIGNAL
- gpio_defaults\[6\] ( gpio_defaults_block_0 gpio_defaults[6] ) ( gpio_control_bidir_1\[0\] gpio_defaults[6] ) + USE SIGNAL
+ ROUTED met2 ( 3532340 669460 0 ) ( * 670140 0 ) ;
- gpio_defaults\[70\] ( gpio_defaults_block_5 gpio_defaults[5] ) ( gpio_control_in_1a\[3\] gpio_defaults[5] ) + USE SIGNAL
+ ROUTED met2 ( 3534640 1796900 0 ) ( * 1797580 0 ) ;
@ -4410,7 +4410,7 @@ NETS 2794 ;
+ ROUTED met2 ( 3546140 2022660 0 ) ( * 2023340 0 ) ;
- gpio_defaults\[79\] ( gpio_defaults_block_6 gpio_defaults[1] ) ( gpio_control_in_1a\[4\] gpio_defaults[1] ) + USE SIGNAL
+ ROUTED met2 ( 3543840 2022660 0 ) ( * 2023340 0 ) ;
- gpio_defaults\[7\] ( gpio_defaults_block_0\[0\] gpio_defaults[7] ) ( gpio_control_bidir_1\[0\] gpio_defaults[7] ) + USE SIGNAL
- gpio_defaults\[7\] ( gpio_defaults_block_0 gpio_defaults[7] ) ( gpio_control_bidir_1\[0\] gpio_defaults[7] ) + USE SIGNAL
+ ROUTED met2 ( 3530040 669460 0 ) ( * 670140 0 ) ;
- gpio_defaults\[80\] ( gpio_defaults_block_6 gpio_defaults[2] ) ( gpio_control_in_1a\[4\] gpio_defaults[2] ) + USE SIGNAL
+ ROUTED met2 ( 3541540 2022660 0 ) ( * 2023340 0 ) ;
@ -4432,7 +4432,7 @@ NETS 2794 ;
+ ROUTED met2 ( 3523140 2022660 0 ) ( * 2023340 0 ) ;
- gpio_defaults\[89\] ( gpio_defaults_block_6 gpio_defaults[11] ) ( gpio_control_in_1a\[4\] gpio_defaults[11] ) + USE SIGNAL
+ ROUTED met2 ( 3520840 2022660 0 ) ( * 2023340 0 ) ;
- gpio_defaults\[8\] ( gpio_defaults_block_0\[0\] gpio_defaults[8] ) ( gpio_control_bidir_1\[0\] gpio_defaults[8] ) + USE SIGNAL
- gpio_defaults\[8\] ( gpio_defaults_block_0 gpio_defaults[8] ) ( gpio_control_bidir_1\[0\] gpio_defaults[8] ) + USE SIGNAL
+ ROUTED met2 ( 3527740 669460 0 ) ( * 670140 0 ) ;
- gpio_defaults\[90\] ( gpio_defaults_block_6 gpio_defaults[12] ) ( gpio_control_in_1a\[4\] gpio_defaults[12] ) + USE SIGNAL
+ ROUTED met2 ( 3518540 2022660 0 ) ( * 2023340 0 ) ;
@ -4454,7 +4454,7 @@ NETS 2794 ;
+ ROUTED met2 ( 3530040 2463980 0 ) ( * 2464320 0 ) ;
- gpio_defaults\[99\] ( gpio_defaults_block_7 gpio_defaults[8] ) ( gpio_control_in_1a\[5\] gpio_defaults[8] ) + USE SIGNAL
+ ROUTED met2 ( 3527740 2463980 0 ) ( * 2464320 0 ) ;
- gpio_defaults\[9\] ( gpio_defaults_block_0\[0\] gpio_defaults[9] ) ( gpio_control_bidir_1\[0\] gpio_defaults[9] ) + USE SIGNAL
- gpio_defaults\[9\] ( gpio_defaults_block_0 gpio_defaults[9] ) ( gpio_control_bidir_1\[0\] gpio_defaults[9] ) + USE SIGNAL
+ ROUTED met2 ( 3525440 669460 0 ) ( * 670140 0 ) ;
- gpio_in_core ( soc gpio_in_pad ) ( padframe gpio_in_core ) + USE SIGNAL
+ ROUTED met2 ( 2574390 210460 ) ( 2575770 * 0 )

5253
def/gpio_control_block.def
View File

File diff suppressed because it is too large Load Diff

BIN
gds/gpio_control_block.gds.gz
View File

Binary file not shown.

299
lef/gpio_control_block.lef
View File

@ -459,13 +459,25 @@ MACRO gpio_control_block
RECT 4.745 59.755 169.810 59.925 ;
LAYER li1 ;
RECT 0.000 59.585 169.810 59.755 ;
RECT 0.000 57.645 6.100 59.585 ;
RECT 0.000 58.605 6.505 59.585 ;
LAYER li1 ;
RECT 6.100 57.645 169.810 59.585 ;
RECT 6.505 58.605 169.810 59.585 ;
LAYER li1 ;
RECT 0.000 57.405 8.925 57.645 ;
RECT 0.000 58.445 6.585 58.605 ;
LAYER li1 ;
RECT 8.925 57.405 169.810 57.645 ;
RECT 6.585 58.445 169.810 58.605 ;
LAYER li1 ;
RECT 0.000 58.195 6.085 58.445 ;
LAYER li1 ;
RECT 6.085 58.195 169.810 58.445 ;
LAYER li1 ;
RECT 0.000 58.005 6.585 58.195 ;
LAYER li1 ;
RECT 6.585 58.005 169.810 58.195 ;
LAYER li1 ;
RECT 0.000 57.405 6.505 58.005 ;
LAYER li1 ;
RECT 6.505 57.405 169.810 58.005 ;
LAYER li1 ;
RECT 0.000 30.025 4.265 57.405 ;
LAYER li1 ;
@ -479,13 +491,37 @@ MACRO gpio_control_block
LAYER li1 ;
RECT 4.745 29.835 169.810 30.005 ;
LAYER li1 ;
RECT 0.000 29.665 16.795 29.835 ;
RECT 0.000 29.655 16.795 29.835 ;
LAYER li1 ;
RECT 16.795 29.665 169.810 29.835 ;
RECT 16.795 29.655 169.810 29.835 ;
LAYER li1 ;
RECT 0.000 27.455 6.065 29.665 ;
RECT 0.000 29.640 16.910 29.655 ;
LAYER li1 ;
RECT 6.065 27.455 169.810 29.665 ;
RECT 16.910 29.640 169.810 29.655 ;
LAYER li1 ;
RECT 0.000 29.395 8.925 29.640 ;
LAYER li1 ;
RECT 8.925 29.395 169.810 29.640 ;
LAYER li1 ;
RECT 0.000 29.095 7.545 29.395 ;
LAYER li1 ;
RECT 7.545 29.095 169.810 29.395 ;
LAYER li1 ;
RECT 0.000 28.925 7.845 29.095 ;
LAYER li1 ;
RECT 7.845 28.925 169.810 29.095 ;
LAYER li1 ;
RECT 0.000 28.305 6.125 28.925 ;
LAYER li1 ;
RECT 6.125 28.305 169.810 28.925 ;
LAYER li1 ;
RECT 0.000 27.785 7.845 28.305 ;
LAYER li1 ;
RECT 7.845 27.785 169.810 28.305 ;
LAYER li1 ;
RECT 0.000 27.455 7.625 27.785 ;
LAYER li1 ;
RECT 7.625 27.455 169.810 27.785 ;
LAYER li1 ;
RECT 0.000 27.285 16.795 27.455 ;
LAYER li1 ;
@ -495,57 +531,25 @@ MACRO gpio_control_block
LAYER li1 ;
RECT 4.745 27.115 169.810 27.285 ;
LAYER li1 ;
RECT 0.000 26.945 16.795 27.115 ;
RECT 0.000 26.095 16.795 27.115 ;
LAYER li1 ;
RECT 16.795 26.945 169.810 27.115 ;
RECT 16.795 26.095 169.810 27.115 ;
LAYER li1 ;
RECT 0.000 26.185 16.905 26.945 ;
RECT 0.000 25.475 16.705 26.095 ;
LAYER li1 ;
RECT 16.905 26.185 169.810 26.945 ;
RECT 16.705 25.475 169.810 26.095 ;
LAYER li1 ;
RECT 0.000 26.015 17.450 26.185 ;
RECT 0.000 24.565 16.795 25.475 ;
LAYER li1 ;
RECT 17.450 26.015 169.810 26.185 ;
LAYER li1 ;
RECT 0.000 25.835 16.795 26.015 ;
LAYER li1 ;
RECT 16.795 25.835 169.810 26.015 ;
LAYER li1 ;
RECT 0.000 25.465 16.645 25.835 ;
LAYER li1 ;
RECT 16.645 25.465 169.810 25.835 ;
LAYER li1 ;
RECT 0.000 25.285 16.795 25.465 ;
LAYER li1 ;
RECT 16.795 25.285 169.810 25.465 ;
LAYER li1 ;
RECT 0.000 25.115 17.450 25.285 ;
LAYER li1 ;
RECT 17.450 25.115 169.810 25.285 ;
LAYER li1 ;
RECT 0.000 24.735 16.905 25.115 ;
LAYER li1 ;
RECT 16.905 24.735 169.810 25.115 ;
LAYER li1 ;
RECT 0.000 24.565 16.795 24.735 ;
LAYER li1 ;
RECT 16.795 24.565 169.810 24.735 ;
RECT 16.795 24.565 169.810 25.475 ;
LAYER li1 ;
RECT 0.000 24.395 15.325 24.565 ;
LAYER li1 ;
RECT 15.325 24.395 169.810 24.565 ;
LAYER li1 ;
RECT 0.000 24.225 16.795 24.395 ;
RECT 0.000 21.845 16.795 24.395 ;
LAYER li1 ;
RECT 16.795 24.225 169.810 24.395 ;
LAYER li1 ;
RECT 0.000 22.015 16.645 24.225 ;
LAYER li1 ;
RECT 16.645 22.015 169.810 24.225 ;
LAYER li1 ;
RECT 0.000 21.845 16.795 22.015 ;
LAYER li1 ;
RECT 16.795 21.845 169.810 22.015 ;
RECT 16.795 21.845 169.810 24.395 ;
LAYER li1 ;
RECT 0.000 21.675 15.325 21.845 ;
LAYER li1 ;
@ -575,17 +579,9 @@ MACRO gpio_control_block
LAYER li1 ;
RECT 15.325 18.955 169.810 19.125 ;
LAYER li1 ;
RECT 0.000 18.785 16.795 18.955 ;
RECT 0.000 16.405 16.795 18.955 ;
LAYER li1 ;
RECT 16.795 18.785 169.810 18.955 ;
LAYER li1 ;
RECT 0.000 16.575 16.645 18.785 ;
LAYER li1 ;
RECT 16.645 16.575 169.810 18.785 ;
LAYER li1 ;
RECT 0.000 16.405 16.795 16.575 ;
LAYER li1 ;
RECT 16.795 16.405 169.810 16.575 ;
RECT 16.795 16.405 169.810 18.955 ;
LAYER li1 ;
RECT 0.000 16.235 15.325 16.405 ;
LAYER li1 ;
@ -615,53 +611,33 @@ MACRO gpio_control_block
LAYER li1 ;
RECT 15.325 13.515 169.810 13.685 ;
LAYER li1 ;
RECT 0.000 13.005 16.950 13.515 ;
RECT 0.000 12.675 16.910 13.515 ;
LAYER li1 ;
RECT 16.950 13.005 169.810 13.515 ;
RECT 16.910 12.675 169.810 13.515 ;
LAYER li1 ;
RECT 0.000 12.835 16.795 13.005 ;
RECT 0.000 12.115 16.795 12.675 ;
LAYER li1 ;
RECT 16.795 12.835 169.810 13.005 ;
RECT 16.795 12.115 169.810 12.675 ;
LAYER li1 ;
RECT 0.000 12.275 16.645 12.835 ;
RECT 0.000 10.965 16.910 12.115 ;
LAYER li1 ;
RECT 16.645 12.275 169.810 12.835 ;
LAYER li1 ;
RECT 0.000 11.775 16.795 12.275 ;
LAYER li1 ;
RECT 16.795 11.775 169.810 12.275 ;
LAYER li1 ;
RECT 0.000 10.965 16.950 11.775 ;
LAYER li1 ;
RECT 16.950 10.965 169.810 11.775 ;
RECT 16.910 10.965 169.810 12.115 ;
LAYER li1 ;
RECT 0.000 10.795 15.325 10.965 ;
LAYER li1 ;
RECT 15.325 10.795 169.810 10.965 ;
LAYER li1 ;
RECT 0.000 10.020 16.795 10.795 ;
RECT 0.000 10.625 16.795 10.795 ;
LAYER li1 ;
RECT 16.795 10.020 169.810 10.795 ;
RECT 16.795 10.625 169.810 10.795 ;
LAYER li1 ;
RECT 0.000 9.825 16.970 10.020 ;
RECT 0.000 8.415 16.645 10.625 ;
LAYER li1 ;
RECT 16.970 9.825 169.810 10.020 ;
RECT 16.645 8.415 169.810 10.625 ;
LAYER li1 ;
RECT 0.000 9.655 17.920 9.825 ;
RECT 0.000 8.245 16.795 8.415 ;
LAYER li1 ;
RECT 17.920 9.655 169.810 9.825 ;
LAYER li1 ;
RECT 0.000 9.000 16.840 9.655 ;
LAYER li1 ;
RECT 16.840 9.000 169.810 9.655 ;
LAYER li1 ;
RECT 0.000 8.670 16.905 9.000 ;
LAYER li1 ;
RECT 16.905 8.670 169.810 9.000 ;
LAYER li1 ;
RECT 0.000 8.245 16.795 8.670 ;
LAYER li1 ;
RECT 16.795 8.245 169.810 8.670 ;
RECT 16.795 8.245 169.810 8.415 ;
LAYER li1 ;
RECT 0.000 8.075 15.325 8.245 ;
LAYER li1 ;
@ -687,9 +663,25 @@ MACRO gpio_control_block
LAYER li1 ;
RECT 16.795 5.185 169.810 5.355 ;
LAYER li1 ;
RECT 0.000 2.975 6.525 5.185 ;
RECT 0.000 4.205 6.505 5.185 ;
LAYER li1 ;
RECT 6.525 2.975 169.810 5.185 ;
RECT 6.505 4.205 169.810 5.185 ;
LAYER li1 ;
RECT 0.000 4.045 6.585 4.205 ;
LAYER li1 ;
RECT 6.585 4.045 169.810 4.205 ;
LAYER li1 ;
RECT 0.000 3.795 6.085 4.045 ;
LAYER li1 ;
RECT 6.085 3.795 169.810 4.045 ;
LAYER li1 ;
RECT 0.000 3.605 6.585 3.795 ;
LAYER li1 ;
RECT 6.585 3.605 169.810 3.795 ;
LAYER li1 ;
RECT 0.000 2.975 6.505 3.605 ;
LAYER li1 ;
RECT 6.505 2.975 169.810 3.605 ;
LAYER li1 ;
RECT 0.000 2.805 16.795 2.975 ;
LAYER li1 ;
@ -703,7 +695,7 @@ MACRO gpio_control_block
LAYER li1 ;
RECT 16.795 0.000 169.810 2.635 ;
LAYER met1 ;
RECT 4.300 0.000 170.000 65.000 ;
RECT 4.600 0.000 170.000 65.000 ;
LAYER met2 ;
RECT 5.250 60.720 6.710 65.000 ;
RECT 7.550 60.720 9.010 65.000 ;
@ -718,68 +710,67 @@ MACRO gpio_control_block
RECT 28.250 60.720 29.710 65.000 ;
RECT 30.550 60.720 32.010 65.000 ;
RECT 32.850 60.720 170.000 65.000 ;
RECT 4.690 0.000 170.000 60.720 ;
RECT 4.970 0.000 170.000 60.720 ;
LAYER met3 ;
RECT 4.665 60.840 69.600 61.705 ;
RECT 4.665 60.200 70.000 60.840 ;
RECT 4.665 58.800 69.600 60.200 ;
RECT 4.665 58.160 70.000 58.800 ;
RECT 4.665 56.760 69.600 58.160 ;
RECT 4.665 56.120 70.000 56.760 ;
RECT 4.665 54.720 69.600 56.120 ;
RECT 4.665 54.080 70.000 54.720 ;
RECT 4.665 52.680 69.600 54.080 ;
RECT 4.665 52.040 70.000 52.680 ;
RECT 4.665 50.640 69.600 52.040 ;
RECT 4.665 50.000 70.000 50.640 ;
RECT 4.665 48.600 69.600 50.000 ;
RECT 4.665 47.960 70.000 48.600 ;
RECT 4.665 46.560 69.600 47.960 ;
RECT 4.665 45.920 70.000 46.560 ;
RECT 4.665 44.520 69.600 45.920 ;
RECT 4.665 43.880 70.000 44.520 ;
RECT 4.665 42.480 69.600 43.880 ;
RECT 4.665 41.840 70.000 42.480 ;
RECT 4.665 40.440 69.600 41.840 ;
RECT 4.665 39.800 70.000 40.440 ;
RECT 4.665 38.400 69.600 39.800 ;
RECT 4.665 37.760 70.000 38.400 ;
RECT 4.665 36.360 69.600 37.760 ;
RECT 4.665 35.720 70.000 36.360 ;
RECT 4.665 34.320 69.600 35.720 ;
RECT 4.665 33.680 70.000 34.320 ;
RECT 4.665 32.280 69.600 33.680 ;
RECT 4.665 31.640 70.000 32.280 ;
RECT 4.665 30.240 69.600 31.640 ;
RECT 4.665 29.600 70.000 30.240 ;
RECT 4.665 28.200 69.600 29.600 ;
RECT 4.665 27.560 70.000 28.200 ;
RECT 4.665 26.160 69.600 27.560 ;
RECT 4.665 25.520 70.000 26.160 ;
RECT 4.665 24.120 69.600 25.520 ;
RECT 4.665 23.480 70.000 24.120 ;
RECT 4.665 22.080 69.600 23.480 ;
RECT 4.665 21.440 70.000 22.080 ;
RECT 4.665 20.040 69.600 21.440 ;
RECT 4.665 19.400 70.000 20.040 ;
RECT 4.665 18.000 69.600 19.400 ;
RECT 4.665 17.360 70.000 18.000 ;
RECT 4.665 15.960 69.600 17.360 ;
RECT 4.665 15.320 70.000 15.960 ;
RECT 4.665 13.920 69.600 15.320 ;
RECT 4.665 13.280 70.000 13.920 ;
RECT 4.665 11.880 69.600 13.280 ;
RECT 4.665 11.240 70.000 11.880 ;
RECT 4.665 9.840 69.600 11.240 ;
RECT 4.665 9.200 70.000 9.840 ;
RECT 4.665 7.800 69.600 9.200 ;
RECT 4.665 7.160 70.000 7.800 ;
RECT 4.665 5.760 69.600 7.160 ;
RECT 4.665 5.120 70.000 5.760 ;
RECT 4.665 3.720 69.600 5.120 ;
RECT 4.665 3.080 70.000 3.720 ;
RECT 4.665 1.680 69.600 3.080 ;
RECT 4.665 0.175 70.000 1.680 ;
RECT 6.045 60.840 69.600 61.705 ;
RECT 6.045 60.200 70.000 60.840 ;
RECT 6.045 58.800 69.600 60.200 ;
RECT 6.045 58.160 70.000 58.800 ;
RECT 6.045 56.760 69.600 58.160 ;
RECT 6.045 56.120 70.000 56.760 ;
RECT 6.045 54.720 69.600 56.120 ;
RECT 6.045 54.080 70.000 54.720 ;
RECT 6.045 52.680 69.600 54.080 ;
RECT 6.045 52.040 70.000 52.680 ;
RECT 6.045 50.640 69.600 52.040 ;
RECT 6.045 50.000 70.000 50.640 ;
RECT 6.045 48.600 69.600 50.000 ;
RECT 6.045 47.960 70.000 48.600 ;
RECT 6.045 46.560 69.600 47.960 ;
RECT 6.045 45.920 70.000 46.560 ;
RECT 6.045 44.520 69.600 45.920 ;
RECT 6.045 43.880 70.000 44.520 ;
RECT 6.045 42.480 69.600 43.880 ;
RECT 6.045 41.840 70.000 42.480 ;
RECT 6.045 40.440 69.600 41.840 ;
RECT 6.045 39.800 70.000 40.440 ;
RECT 6.045 38.400 69.600 39.800 ;
RECT 6.045 37.760 70.000 38.400 ;
RECT 6.045 36.360 69.600 37.760 ;
RECT 6.045 35.720 70.000 36.360 ;
RECT 6.045 34.320 69.600 35.720 ;
RECT 6.045 33.680 70.000 34.320 ;
RECT 6.045 32.280 69.600 33.680 ;
RECT 6.045 31.640 70.000 32.280 ;
RECT 6.045 30.240 69.600 31.640 ;
RECT 6.045 29.600 70.000 30.240 ;
RECT 6.045 28.200 69.600 29.600 ;
RECT 6.045 27.560 70.000 28.200 ;
RECT 6.045 26.160 69.600 27.560 ;
RECT 6.045 25.520 70.000 26.160 ;
RECT 6.045 24.120 69.600 25.520 ;
RECT 6.045 23.480 70.000 24.120 ;
RECT 6.045 22.080 69.600 23.480 ;
RECT 6.045 21.440 70.000 22.080 ;
RECT 6.045 20.040 69.600 21.440 ;
RECT 6.045 19.400 70.000 20.040 ;
RECT 6.045 18.000 69.600 19.400 ;
RECT 6.045 17.360 70.000 18.000 ;
RECT 6.045 15.960 69.600 17.360 ;
RECT 6.045 15.320 70.000 15.960 ;
RECT 6.045 13.920 69.600 15.320 ;
RECT 6.045 13.280 70.000 13.920 ;
RECT 6.045 11.880 69.600 13.280 ;
RECT 6.045 11.240 70.000 11.880 ;
RECT 6.045 9.840 69.600 11.240 ;
RECT 6.045 9.200 70.000 9.840 ;
RECT 6.045 7.800 69.600 9.200 ;
RECT 6.045 7.160 70.000 7.800 ;
RECT 6.045 5.760 69.600 7.160 ;
RECT 6.045 5.120 70.000 5.760 ;
RECT 6.045 3.720 69.600 5.120 ;
RECT 6.045 3.080 70.000 3.720 ;
RECT 6.045 2.215 69.600 3.080 ;
LAYER met4 ;
RECT 6.280 60.480 170.000 65.000 ;
RECT 6.280 2.080 12.400 60.480 ;

10
mag/caravan.mag
View File

@ -59042,23 +59042,23 @@ use gpio_control_block gpio_control_in_2\[9\]
timestamp 1650900217
transform 1 0 7631 0 1 332200
box 882 416 34000 13000
use gpio_defaults_block_1803 gpio_defaults_block_0\[0\]
use gpio_defaults_block_1803 gpio_defaults_block_0
timestamp 1638587925
transform -1 0 709467 0 1 134000
box -38 0 6018 2224
use gpio_defaults_block_1803 gpio_defaults_block_0\[1\]
use gpio_defaults_block_1803 gpio_defaults_block_1
timestamp 1638587925
transform -1 0 709467 0 1 179200
box -38 0 6018 2224
use gpio_defaults_block_0403 gpio_defaults_block_2\[0\]
use gpio_defaults_block_0403 gpio_defaults_block_2
timestamp 1638587925
transform -1 0 709467 0 1 224200
box -38 0 6018 2224
use gpio_defaults_block_0403 gpio_defaults_block_2\[1\]
use gpio_defaults_block_0801 gpio_defaults_block_3
timestamp 1638587925
transform -1 0 709467 0 1 269400
box -38 0 6018 2224
use gpio_defaults_block_0403 gpio_defaults_block_2\[2\]
use gpio_defaults_block_0403 gpio_defaults_block_4
timestamp 1638587925
transform -1 0 709467 0 1 314400
box -38 0 6018 2224

10
mag/caravel.mag
View File

@ -73882,23 +73882,23 @@ use gpio_control_block gpio_control_in_2\[15\]
timestamp 1650900217
transform 1 0 7631 0 1 332200
box 882 416 34000 13000
use gpio_defaults_block_1803 gpio_defaults_block_0\[0\]
use gpio_defaults_block_1803 gpio_defaults_block_0
timestamp 1638587925
transform -1 0 709467 0 1 134000
box -38 0 6018 2224
use gpio_defaults_block_1803 gpio_defaults_block_0\[1\]
use gpio_defaults_block_1803 gpio_defaults_block_1
timestamp 1638587925
transform -1 0 709467 0 1 179200
box -38 0 6018 2224
use gpio_defaults_block_0403 gpio_defaults_block_2\[0\]
use gpio_defaults_block_0403 gpio_defaults_block_2
timestamp 1638587925
transform -1 0 709467 0 1 224200
box -38 0 6018 2224
use gpio_defaults_block_0403 gpio_defaults_block_2\[1\]
use gpio_defaults_block_0801 gpio_defaults_block_3
timestamp 1638587925
transform -1 0 709467 0 1 269400
box -38 0 6018 2224
use gpio_defaults_block_0403 gpio_defaults_block_2\[2\]
use gpio_defaults_block_0403 gpio_defaults_block_4
timestamp 1638587925
transform -1 0 709467 0 1 314400
box -38 0 6018 2224

14978
mag/gpio_control_block.mag
View File

File diff suppressed because it is too large Load Diff

131
maglef/gpio_control_block.mag
View File

@ -1,12 +1,12 @@
magic
tech sky130A
magscale 1 2
timestamp 1664976471
timestamp 1665142206
<< obsli1 >>
rect 0 13000 853 13014
rect 0 0 33962 13000
<< obsm1 >>
rect 860 0 34000 13000
rect 920 0 34000 13000
<< metal2 >>
rect 938 12200 994 13000
rect 1398 12200 1454 13000
@ -35,7 +35,7 @@ rect 5190 12144 5482 13000
rect 5650 12144 5942 13000
rect 6110 12144 6402 13000
rect 6570 12144 34000 13000
rect 938 0 34000 12144
rect 994 0 34000 12144
<< metal3 >>
rect 14000 12248 34000 12368
rect 14000 11840 34000 11960
@ -68,66 +68,65 @@ rect 14000 1232 34000 1352
rect 14000 824 34000 944
rect 14000 416 34000 536
<< obsm3 >>
rect 933 12168 13920 12341
rect 933 12040 14000 12168
rect 933 11760 13920 12040
rect 933 11632 14000 11760
rect 933 11352 13920 11632
rect 933 11224 14000 11352
rect 933 10944 13920 11224
rect 933 10816 14000 10944
rect 933 10536 13920 10816
rect 933 10408 14000 10536
rect 933 10128 13920 10408
rect 933 10000 14000 10128
rect 933 9720 13920 10000
rect 933 9592 14000 9720
rect 933 9312 13920 9592
rect 933 9184 14000 9312
rect 933 8904 13920 9184
rect 933 8776 14000 8904
rect 933 8496 13920 8776
rect 933 8368 14000 8496
rect 933 8088 13920 8368
rect 933 7960 14000 8088
rect 933 7680 13920 7960
rect 933 7552 14000 7680
rect 933 7272 13920 7552
rect 933 7144 14000 7272
rect 933 6864 13920 7144
rect 933 6736 14000 6864
rect 933 6456 13920 6736
rect 933 6328 14000 6456
rect 933 6048 13920 6328
rect 933 5920 14000 6048
rect 933 5640 13920 5920
rect 933 5512 14000 5640
rect 933 5232 13920 5512
rect 933 5104 14000 5232
rect 933 4824 13920 5104
rect 933 4696 14000 4824
rect 933 4416 13920 4696
rect 933 4288 14000 4416
rect 933 4008 13920 4288
rect 933 3880 14000 4008
rect 933 3600 13920 3880
rect 933 3472 14000 3600
rect 933 3192 13920 3472
rect 933 3064 14000 3192
rect 933 2784 13920 3064
rect 933 2656 14000 2784
rect 933 2376 13920 2656
rect 933 2248 14000 2376
rect 933 1968 13920 2248
rect 933 1840 14000 1968
rect 933 1560 13920 1840
rect 933 1432 14000 1560
rect 933 1152 13920 1432
rect 933 1024 14000 1152
rect 933 744 13920 1024
rect 933 616 14000 744
rect 933 336 13920 616
rect 933 35 14000 336
rect 1209 12168 13920 12341
rect 1209 12040 14000 12168
rect 1209 11760 13920 12040
rect 1209 11632 14000 11760
rect 1209 11352 13920 11632
rect 1209 11224 14000 11352
rect 1209 10944 13920 11224
rect 1209 10816 14000 10944
rect 1209 10536 13920 10816
rect 1209 10408 14000 10536
rect 1209 10128 13920 10408
rect 1209 10000 14000 10128
rect 1209 9720 13920 10000
rect 1209 9592 14000 9720
rect 1209 9312 13920 9592
rect 1209 9184 14000 9312
rect 1209 8904 13920 9184
rect 1209 8776 14000 8904
rect 1209 8496 13920 8776
rect 1209 8368 14000 8496
rect 1209 8088 13920 8368
rect 1209 7960 14000 8088
rect 1209 7680 13920 7960
rect 1209 7552 14000 7680
rect 1209 7272 13920 7552
rect 1209 7144 14000 7272
rect 1209 6864 13920 7144
rect 1209 6736 14000 6864
rect 1209 6456 13920 6736
rect 1209 6328 14000 6456
rect 1209 6048 13920 6328
rect 1209 5920 14000 6048
rect 1209 5640 13920 5920
rect 1209 5512 14000 5640
rect 1209 5232 13920 5512
rect 1209 5104 14000 5232
rect 1209 4824 13920 5104
rect 1209 4696 14000 4824
rect 1209 4416 13920 4696
rect 1209 4288 14000 4416
rect 1209 4008 13920 4288
rect 1209 3880 14000 4008
rect 1209 3600 13920 3880
rect 1209 3472 14000 3600
rect 1209 3192 13920 3472
rect 1209 3064 14000 3192
rect 1209 2784 13920 3064
rect 1209 2656 14000 2784
rect 1209 2376 13920 2656
rect 1209 2248 14000 2376
rect 1209 1968 13920 2248
rect 1209 1840 14000 1968
rect 1209 1560 13920 1840
rect 1209 1432 14000 1560
rect 1209 1152 13920 1432
rect 1209 1024 14000 1152
rect 1209 744 13920 1024
rect 1209 616 14000 744
rect 1209 443 13920 616
<< metal4 >>
rect 2560 496 2880 12016
rect 3560 496 3880 12016
@ -304,8 +303,8 @@ port 47 nsew signal output
string FIXED_BBOX 0 0 34000 13000
string LEFclass BLOCK
string LEFview TRUE
string GDS_END 572912
string GDS_FILE /home/kareem_farid/caravel/openlane/gpio_control_block/runs/22_10_05_06_26/results/signoff/gpio_control_block.magic.gds
string GDS_START 204218
string GDS_END 560298
string GDS_FILE /home/kareem_farid/caravel/openlane/gpio_control_block/runs/22_10_07_04_28/results/signoff/gpio_control_block.magic.gds
string GDS_START 184426
<< end >>

19
manifest
View File

@ -2,28 +2,29 @@
87735eb5981740ca4d4b48e6b0321c8bb0023800 verilog/rtl/__uprj_netlists.v
684085713662e37a26f9f981d35be7c6c7ff6e9a verilog/rtl/__user_analog_project_wrapper.v
b5ad3558a91e508fad154b91565c7d664b247020 verilog/rtl/__user_project_wrapper.v
0e2cda74281c33da2f4e23d0ff5af91adcbcf32a verilog/rtl/caravan.v
a855d65d6fc59352e4f8a994e451418d113586fc verilog/rtl/caravan_netlists.v
f93c57988b0044d2bff4470a84b5eddc158f2094 verilog/rtl/caravan.v
1b8dc7f0a4f2196b7c2de926af9c648ebf315f3d verilog/rtl/caravan_netlists.v
a3d12a2d2d3596800bec47d1266dce2399a2fcc6 verilog/rtl/caravan_openframe.v
cb320bf7e981979c4e823270d823395ea609c77e verilog/rtl/caravel.v
b4b8fecbdc56c5d8acca9b904415f30e3159d1d5 verilog/rtl/caravel.v
2fe34f043edbe87c626e5616ad54f82c9ba067c2 verilog/rtl/caravel_clocking.v
3b9185fd0dc2d0e8c49f1af3d14724e0948fe650 verilog/rtl/caravel_openframe.v
d0c5cf9260783b1a88c0b772c2e3cee3dcd0cf76 verilog/rtl/chip_io.v
54de41c59139783d39654e1f0a86e2880cb7b076 verilog/rtl/chip_io_alt.v
fdddad12354f0aaf93b9df98980e8a28fb59df65 verilog/rtl/chip_io.v
8a4f1bd4eb40367c3ca8df76df6e1423a8271461 verilog/rtl/chip_io_alt.v
126aff02aa229dc346301c552d785dec76a4d68e verilog/rtl/clock_div.v
941bd7636e7558b045faa3d8c6ba2d91b4c4b798 verilog/rtl/constant_block.v
36af0303a0e84ce4a40a854ef1481f8a56bc9989 verilog/rtl/digital_pll.v
ce49f9af199b5f16d2c39c417d58e5890bc7bab2 verilog/rtl/digital_pll_controller.v
60d2384a91301fec5721953d87931193681822c4 verilog/rtl/gpio_control_block.v
1f894f1c43d42017c157d8dd7d2e4674c1a43303 verilog/rtl/gpio_control_block.v
9c92ddf1391fa75ee906e452e168ca2cdd23bd18 verilog/rtl/gpio_defaults_block.v
32d395d5936632f3c92a0de4867d6dd7cd4af1bb verilog/rtl/gpio_logic_high.v
8dafb824eae7173e43f4e2f31c7470a6a1272c79 verilog/rtl/housekeeping.v
9b602cb0e7f0e6b7e21d87d3a2bd30cb631302c4 verilog/rtl/housekeeping.v
3030f955d5f110d24012bd1562c0e18c1a0d04e2 verilog/rtl/housekeeping_spi.v
ee3fbd794fcc6d221562147b09891e315873ac4c verilog/rtl/mgmt_protect.v
3b1ff20593bc386d13f5e2cf1571f08121889957 verilog/rtl/mgmt_protect_hv.v
9816acedf3dc3edd193861cc217ec46180ac1cdd verilog/rtl/mprj2_logic_high.v
9dd11188f3a6980537dd51d8dd1a827795ac70fc verilog/rtl/mprj_io.v
d71adbc70dbb0ed879d3b75419bd807c866a9680 verilog/rtl/mprj_io.v
3baffde4788f01e2ff0e5cd83020a76bd63ef7d7 verilog/rtl/mprj_logic_high.v
6f490c83d6064c380a3f475823ef97f325d7f6c1 verilog/rtl/pads.v
4edbfd0ad80b69a799a399ffc717b560fcae615b verilog/rtl/pads.v
669d16642d5dd5f6824812754db20db98c9fe17b verilog/rtl/ring_osc2x13.v
6f802b6ab7e6502160adfe41e313958b86d2c277 verilog/rtl/simple_por.v
1b1705d41992b318c791a5703e0d43d0bcda8f12 verilog/rtl/spare_logic_block.v

5
openlane/gpio_control_block/config.tcl
View File

@ -21,7 +21,7 @@ set ::env(VERILOG_FILES) "\
$::env(DESIGN_DIR)/../../verilog/rtl/gpio_control_block.v"
set ::env(PL_TARGET_DENSITY) 0.8
set ::env(PL_TARGET_DENSITY) 0.9
set ::env(CLOCK_PORT) "serial_clock"
set ::env(FP_DEF_TEMPLATE) "$::env(DESIGN_DIR)/template/gpio_control_block.def"
@ -43,13 +43,14 @@ set ::env(SYNTH_STRATEGY) "AREA 0"
set ::env(FP_SIZING) absolute
set ::env(DIE_AREA) "0 0 170 65"
set ::env(RIGHT_MARGIN_MULT) 257
set ::env(RIGHT_MARGIN_MULT) 256
set ::env(LEFT_MARGIN_MULT) 10
set ::env(TOP_MARGIN_MULT) 1
set ::env(BOTTOM_MARGIN_MULT) 1
set ::env(DPL_CELL_PADDING) 0
set ::env(GPL_CELL_PADDING) 0
set ::env(DIODE_PADDING) 0
## PDN
set ::env(FP_PDN_MACRO_HOOKS) "\

2
scripts/gen_gpio_defaults.py
View File

@ -172,7 +172,7 @@ if __name__ == '__main__':
kvpairs["`USER_CONFIG_GPIO_0_INIT"] = "13'h1803"
kvpairs["`USER_CONFIG_GPIO_1_INIT"] = "13'h1803"
kvpairs["`USER_CONFIG_GPIO_2_INIT"] = "13'h0403"
kvpairs["`USER_CONFIG_GPIO_3_INIT"] = "13'h0403"
kvpairs["`USER_CONFIG_GPIO_3_INIT"] = "13'h0801"
kvpairs["`USER_CONFIG_GPIO_4_INIT"] = "13'h0403"
# Generate zero and one coordinates for each via

1
scripts/run_caravan_lvs_full.sh
View File

@ -78,6 +78,7 @@ readnet verilog ../verilog/gl/digital_pll.v \$circuit2
readnet verilog ../verilog/gl/gpio_control_block.v \$circuit2
readnet verilog ../verilog/gl/gpio_defaults_block.v \$circuit2
readnet verilog ../verilog/gl/gpio_defaults_block_1803.v \$circuit2
readnet verilog ../verilog/gl/gpio_defaults_block_0801.v \$circuit2
readnet verilog ../verilog/gl/gpio_defaults_block_0403.v \$circuit2
readnet verilog ../verilog/gl/gpio_logic_high.v \$circuit2
readnet verilog ../verilog/gl/housekeeping.v \$circuit2

2
sdc/gpio_control_block.sdc
View File

@ -1,6 +1,6 @@
###############################################################################
# Created by write_sdc
# Wed Oct 5 13:27:20 2022
# Fri Oct 7 11:29:34 2022
###############################################################################
current_design gpio_control_block
###############################################################################

1754
sdf/gpio_control_block.sdf
View File

File diff suppressed because it is too large Load Diff

9732
spef/gpio_control_block.spef
View File

File diff suppressed because it is too large Load Diff

422
spi/lvs/gpio_control_block.spice
View File

@ -8,6 +8,10 @@
.subckt sky130_fd_sc_hd__fill_1 VGND VNB VPB VPWR
.ends
* Black-box entry subcircuit for sky130_fd_sc_hd__nand2b_2 abstract view
.subckt sky130_fd_sc_hd__nand2b_2 A_N B VGND VNB VPB VPWR Y
.ends
* Black-box entry subcircuit for sky130_fd_sc_hd__dfbbn_2 abstract view
.subckt sky130_fd_sc_hd__dfbbn_2 CLK_N D RESET_B SET_B VGND VNB VPB VPWR Q Q_N
.ends
@ -16,22 +20,30 @@
.subckt sky130_fd_sc_hd__buf_16 A VGND VNB VPB VPWR X
.ends
* Black-box entry subcircuit for sky130_fd_sc_hd__clkbuf_16 abstract view
.subckt sky130_fd_sc_hd__clkbuf_16 A VGND VNB VPB VPWR X
.ends
* Black-box entry subcircuit for sky130_fd_sc_hd__inv_2 abstract view
.subckt sky130_fd_sc_hd__inv_2 A VGND VNB VPB VPWR Y
.ends
* Black-box entry subcircuit for sky130_fd_sc_hd__diode_2 abstract view
.subckt sky130_fd_sc_hd__diode_2 DIODE VGND VNB VPB VPWR
* Black-box entry subcircuit for sky130_fd_sc_hd__mux2_4 abstract view
.subckt sky130_fd_sc_hd__mux2_4 A0 A1 S VGND VNB VPB VPWR X
.ends
* Black-box entry subcircuit for sky130_fd_sc_hd__clkbuf_16 abstract view
.subckt sky130_fd_sc_hd__clkbuf_16 A VGND VNB VPB VPWR X
.ends
* Black-box entry subcircuit for sky130_fd_sc_hd__and2_0 abstract view
.subckt sky130_fd_sc_hd__and2_0 A B VGND VNB VPB VPWR X
.ends
* Black-box entry subcircuit for sky130_fd_sc_hd__dlygate4sd3_1 abstract view
.subckt sky130_fd_sc_hd__dlygate4sd3_1 A VGND VNB VPB VPWR X
.ends
* Black-box entry subcircuit for sky130_fd_sc_hd__diode_2 abstract view
.subckt sky130_fd_sc_hd__diode_2 DIODE VGND VNB VPB VPWR
.ends
* Black-box entry subcircuit for sky130_fd_sc_hd__decap_3 abstract view
.subckt sky130_fd_sc_hd__decap_3 VGND VNB VPB VPWR
.ends
@ -40,40 +52,40 @@
.subckt sky130_fd_sc_hd__conb_1 VGND VNB VPB VPWR HI LO
.ends
* Black-box entry subcircuit for sky130_fd_sc_hd__nand2b_2 abstract view
.subckt sky130_fd_sc_hd__nand2b_2 A_N B VGND VNB VPB VPWR Y
.ends
* Black-box entry subcircuit for sky130_fd_sc_hd__or2_0 abstract view
.subckt sky130_fd_sc_hd__or2_0 A B VGND VNB VPB VPWR X
* Black-box entry subcircuit for sky130_fd_sc_hd__decap_4 abstract view
.subckt sky130_fd_sc_hd__decap_4 VGND VNB VPB VPWR
.ends
* Black-box entry subcircuit for sky130_fd_sc_hd__buf_2 abstract view
.subckt sky130_fd_sc_hd__buf_2 A VGND VNB VPB VPWR X
.ends
* Black-box entry subcircuit for sky130_fd_sc_hd__einvp_8 abstract view
.subckt sky130_fd_sc_hd__einvp_8 A TE VGND VNB VPB VPWR Z
* Black-box entry subcircuit for sky130_fd_sc_hd__or2_0 abstract view
.subckt sky130_fd_sc_hd__or2_0 A B VGND VNB VPB VPWR X
.ends
* Black-box entry subcircuit for sky130_fd_sc_hd__tapvpwrvgnd_1 abstract view
.subckt sky130_fd_sc_hd__tapvpwrvgnd_1 VGND VPWR
.ends
* Black-box entry subcircuit for sky130_fd_sc_hd__o21ai_4 abstract view
.subckt sky130_fd_sc_hd__o21ai_4 A1 A2 B1 VGND VNB VPB VPWR Y
.ends
* Black-box entry subcircuit for sky130_fd_sc_hd__decap_6 abstract view
.subckt sky130_fd_sc_hd__decap_6 VGND VNB VPB VPWR
* Black-box entry subcircuit for sky130_fd_sc_hd__decap_8 abstract view
.subckt sky130_fd_sc_hd__decap_8 VGND VNB VPB VPWR
.ends
* Black-box entry subcircuit for gpio_logic_high abstract view
.subckt gpio_logic_high gpio_logic1 vccd1 vssd1
.ends
* Black-box entry subcircuit for sky130_fd_sc_hd__ebufn_8 abstract view
.subckt sky130_fd_sc_hd__ebufn_8 A TE_B VGND VNB VPB VPWR Z
* Black-box entry subcircuit for sky130_fd_sc_hd__fill_2 abstract view
.subckt sky130_fd_sc_hd__fill_2 VGND VNB VPB VPWR
.ends
* Black-box entry subcircuit for sky130_fd_sc_hd__and2_2 abstract view
.subckt sky130_fd_sc_hd__and2_2 A B VGND VNB VPB VPWR X
.ends
* Black-box entry subcircuit for sky130_fd_sc_hd__o21ai_4 abstract view
.subckt sky130_fd_sc_hd__o21ai_4 A1 A2 B1 VGND VNB VPB VPWR Y
.ends
* Black-box entry subcircuit for sky130_fd_sc_hd__o21ai_2 abstract view
@ -84,20 +96,12 @@
.subckt sky130_fd_sc_hd__and2b_2 A_N B VGND VNB VPB VPWR X
.ends
* Black-box entry subcircuit for sky130_fd_sc_hd__and3b_2 abstract view
.subckt sky130_fd_sc_hd__and3b_2 A_N B C VGND VNB VPB VPWR X
.ends
* Black-box entry subcircuit for sky130_fd_sc_hd__dfrtp_2 abstract view
.subckt sky130_fd_sc_hd__dfrtp_2 CLK D RESET_B VGND VNB VPB VPWR Q
.ends
* Black-box entry subcircuit for sky130_fd_sc_hd__mux2_4 abstract view
.subckt sky130_fd_sc_hd__mux2_4 A0 A1 S VGND VNB VPB VPWR X
.ends
* Black-box entry subcircuit for sky130_fd_sc_hd__and2_0 abstract view
.subckt sky130_fd_sc_hd__and2_0 A B VGND VNB VPB VPWR X
* Black-box entry subcircuit for sky130_fd_sc_hd__and3b_2 abstract view
.subckt sky130_fd_sc_hd__and3b_2 A_N B C VGND VNB VPB VPWR X
.ends
.subckt gpio_control_block gpio_defaults[0] gpio_defaults[10] gpio_defaults[11] gpio_defaults[12]
@ -108,277 +112,283 @@
+ pad_gpio_in pad_gpio_inenb pad_gpio_out pad_gpio_outenb pad_gpio_slow_sel pad_gpio_vtrip_sel
+ resetn resetn_out serial_clock serial_clock_out serial_data_in serial_data_out serial_load
+ serial_load_out user_gpio_in user_gpio_oeb user_gpio_out vccd vccd1 vssd vssd1 zero
X_131_ _134_/CLK _131_/D _085_/A vssd vssd vccd vccd hold1/A sky130_fd_sc_hd__dfrtp_4
X_131_ _131_/CLK hold1/X _086_/A vssd vssd vccd vccd hold2/A sky130_fd_sc_hd__dfrtp_4
XFILLER_9_99 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
X_062_ _106_/Q user_gpio_out vssd vssd vccd vccd _062_/Y sky130_fd_sc_hd__nand2b_2
XFILLER_0_57 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
XFILLER_20_98 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
X_114_ _101__6/Y _127_/D _081_/X _082_/Y vssd vssd vccd vccd _114_/Q _114_/Q_N sky130_fd_sc_hd__dfbbn_2
Xoutput20 _135_/Q vssd vssd vccd vccd serial_data_out sky130_fd_sc_hd__buf_16
Xoutput7 _121_/Q vssd vssd vccd vccd pad_gpio_ana_pol sky130_fd_sc_hd__buf_16
X_130_ _130_/CLK hold8/X _095_/A vssd vssd vccd vccd _130_/Q sky130_fd_sc_hd__dfrtp_4
X_113_ _100__5/Y hold6/X _079_/X _080_/Y vssd vssd vccd vccd _113_/Q _113_/Q_N sky130_fd_sc_hd__dfbbn_2
Xclkbuf_1_0__f_serial_load clkbuf_0_serial_load/X vssd vssd vccd vccd _103__8/A sky130_fd_sc_hd__clkbuf_16
X_097__2 _104__9/A vssd vssd vccd vccd _097__2/Y sky130_fd_sc_hd__inv_2
Xoutput8 _120_/Q vssd vssd vccd vccd pad_gpio_ana_sel sky130_fd_sc_hd__buf_16
Xoutput10 _117_/Q vssd vssd vccd vccd pad_gpio_dm[1] sky130_fd_sc_hd__buf_16
X_060_ _139_/A vssd vssd vccd vccd _060_/Y sky130_fd_sc_hd__inv_2
X_112_ _099__4/Y hold1/X _077_/X _078_/Y vssd vssd vccd vccd _112_/Q _112_/Q_N sky130_fd_sc_hd__dfbbn_2
XANTENNA__065__A0 user_gpio_oeb vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
Xhold10 _132_/Q vssd vssd vccd vccd _133_/D sky130_fd_sc_hd__dlygate4sd3_1
Xoutput9 _116_/Q vssd vssd vccd vccd pad_gpio_dm[0] sky130_fd_sc_hd__buf_16
Xoutput11 _118_/Q vssd vssd vccd vccd pad_gpio_dm[2] sky130_fd_sc_hd__buf_16
XANTENNA__084__A_N _083_/A vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XFILLER_3_48 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
X_111_ _098__3/Y _131_/D _075_/X _076_/Y vssd vssd vccd vccd _111_/Q _111_/Q_N sky130_fd_sc_hd__dfbbn_2
Xhold11 _127_/Q vssd vssd vccd vccd _128_/D sky130_fd_sc_hd__dlygate4sd3_1
X_107__12 _103__8/A vssd vssd vccd vccd _107__12/Y sky130_fd_sc_hd__inv_2
Xoutput12 _110_/Q vssd vssd vccd vccd pad_gpio_holdover sky130_fd_sc_hd__buf_16
X_110_ _097__2/Y hold4/X _073_/X _074_/Y vssd vssd vccd vccd _110_/Q _110_/Q_N sky130_fd_sc_hd__dfbbn_2
Xhold12 _130_/Q vssd vssd vccd vccd _131_/D sky130_fd_sc_hd__dlygate4sd3_1
XANTENNA__072__B gpio_defaults[0] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XANTENNA__074__A_N _083_/A vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
Xoutput13 _114_/Q vssd vssd vccd vccd pad_gpio_ib_mode_sel sky130_fd_sc_hd__buf_16
XANTENNA__083__A _083_/A vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XANTENNA__080__B gpio_defaults[3] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XANTENNA__075__B gpio_defaults[8] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
Xhold13 _126_/Q vssd vssd vccd vccd _127_/D sky130_fd_sc_hd__dlygate4sd3_1
XANTENNA__083__B gpio_defaults[1] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
X_114_ _101__9/Y hold1/X _084_/X _085_/Y vssd vssd vccd vccd _114_/Q _114_/Q_N sky130_fd_sc_hd__dfbbn_2
Xoutput20 _134_/X vssd vssd vccd vccd resetn_out sky130_fd_sc_hd__buf_16
Xoutput7 _116_/Q vssd vssd vccd vccd pad_gpio_ana_en sky130_fd_sc_hd__buf_16
X_104__12 _100__8/A vssd vssd vccd vccd _104__12/Y sky130_fd_sc_hd__inv_2
X_130_ _131_/CLK hold9/X _086_/A vssd vssd vccd vccd hold1/A sky130_fd_sc_hd__dfrtp_4
X_094__2 _101__9/A vssd vssd vccd vccd _094__2/Y sky130_fd_sc_hd__inv_2
X_061_ user_gpio_oeb _060_/X _106_/Q vssd vssd vccd vccd _061_/X sky130_fd_sc_hd__mux2_4
X_113_ _100__8/Y hold9/X _082_/X _083_/Y vssd vssd vccd vccd _113_/Q _113_/Q_N sky130_fd_sc_hd__dfbbn_2
Xclkbuf_1_0__f_serial_load clkbuf_0_serial_load/X vssd vssd vccd vccd _100__8/A sky130_fd_sc_hd__clkbuf_16
X_059__14 _126_/CLK vssd vssd vccd vccd _132_/CLK sky130_fd_sc_hd__inv_2
Xoutput21 _132_/Q vssd vssd vccd vccd serial_data_out sky130_fd_sc_hd__buf_16
Xoutput8 _118_/Q vssd vssd vccd vccd pad_gpio_ana_pol sky130_fd_sc_hd__buf_16
Xoutput10 _113_/Q vssd vssd vccd vccd pad_gpio_dm[0] sky130_fd_sc_hd__buf_16
X_060_ _112_/Q _063_/C vssd vssd vccd vccd _060_/X sky130_fd_sc_hd__and2_0
X_112_ _099__7/Y hold3/X _080_/X _081_/Y vssd vssd vccd vccd _112_/Q _112_/Q_N sky130_fd_sc_hd__dfbbn_2
Xhold10 _123_/Q vssd vssd vccd vccd _124_/D sky130_fd_sc_hd__dlygate4sd3_1
Xoutput22 _067_/X vssd vssd vccd vccd user_gpio_in sky130_fd_sc_hd__buf_16
Xoutput11 _114_/Q vssd vssd vccd vccd pad_gpio_dm[1] sky130_fd_sc_hd__buf_16
Xoutput9 _117_/Q vssd vssd vccd vccd pad_gpio_ana_sel sky130_fd_sc_hd__buf_16
X_111_ _098__6/Y _124_/D _078_/X _079_/Y vssd vssd vccd vccd _111_/Q _111_/Q_N sky130_fd_sc_hd__dfbbn_2
XFILLER_0_27 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
Xhold11 _126_/Q vssd vssd vccd vccd _127_/D sky130_fd_sc_hd__dlygate4sd3_1
Xoutput12 _115_/Q vssd vssd vccd vccd pad_gpio_dm[2] sky130_fd_sc_hd__buf_16
XANTENNA__072__B gpio_defaults[8] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
X_110_ _097__5/Y hold6/X _076_/X _077_/Y vssd vssd vccd vccd _110_/Q _110_/Q_N sky130_fd_sc_hd__dfbbn_2
Xhold12 _125_/Q vssd vssd vccd vccd _126_/D sky130_fd_sc_hd__dlygate4sd3_1
X_097__5 _101__9/A vssd vssd vccd vccd _097__5/Y sky130_fd_sc_hd__inv_2
Xoutput13 _107_/Q vssd vssd vccd vccd pad_gpio_holdover sky130_fd_sc_hd__buf_16
XANTENNA__080__B gpio_defaults[1] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XANTENNA__075__B gpio_defaults[9] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
Xhold13 _124_/Q vssd vssd vccd vccd _125_/D sky130_fd_sc_hd__dlygate4sd3_1
XANTENNA__083__B gpio_defaults[10] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
Xoutput14 _111_/Q vssd vssd vccd vccd pad_gpio_ib_mode_sel sky130_fd_sc_hd__buf_16
XPHY_0 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
XANTENNA__078__B gpio_defaults[9] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
Xoutput14 _113_/Q vssd vssd vccd vccd pad_gpio_inenb sky130_fd_sc_hd__buf_16
XANTENNA__125__RESET_B _083_/A vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XANTENNA__091__B gpio_defaults[5] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XANTENNA__086__B gpio_defaults[10] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
Xoutput15 _070_/Y vssd vssd vccd vccd pad_gpio_out sky130_fd_sc_hd__buf_16
XANTENNA__078__B gpio_defaults[4] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XANTENNA__091__B gpio_defaults[6] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XANTENNA__086__B gpio_defaults[12] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XPHY_1 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
XANTENNA__094__B gpio_defaults[6] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XANTENNA__089__B gpio_defaults[12] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
X_100__5 _104__9/A vssd vssd vccd vccd _100__5/Y sky130_fd_sc_hd__inv_2
Xoutput15 _110_/Q vssd vssd vccd vccd pad_gpio_inenb sky130_fd_sc_hd__buf_16
XANTENNA__089__B gpio_defaults[5] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
Xconst_source vssd vssd vccd vccd one_buffer/A zero_buffer/A sky130_fd_sc_hd__conb_1
XFILLER_19_70 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
Xoutput16 _065_/X vssd vssd vccd vccd pad_gpio_outenb sky130_fd_sc_hd__buf_16
XFILLER_10_83 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
XFILLER_1_30 vssd vssd vccd vccd sky130_fd_sc_hd__decap_4
XANTENNA_fanout27_A _134_/A vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
Xoutput16 _066_/Y vssd vssd vccd vccd pad_gpio_out sky130_fd_sc_hd__buf_16
XPHY_2 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
Xoutput17 _111_/Q vssd vssd vccd vccd pad_gpio_slow_sel sky130_fd_sc_hd__buf_16
Xoutput17 _061_/X vssd vssd vccd vccd pad_gpio_outenb sky130_fd_sc_hd__buf_16
XPHY_3 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
XFILLER_10_85 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
X_096_ _095_/A gpio_defaults[7] vssd vssd vccd vccd _096_/Y sky130_fd_sc_hd__nand2b_2
XFILLER_1_32 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
XFILLER_1_98 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
X_079_ _083_/A gpio_defaults[3] vssd vssd vccd vccd _079_/X sky130_fd_sc_hd__or2_0
Xoutput18 _112_/Q vssd vssd vccd vccd pad_gpio_vtrip_sel sky130_fd_sc_hd__buf_16
Xfanout30 input4/X vssd vssd vccd vccd fanout30/X sky130_fd_sc_hd__buf_2
Xoutput18 _108_/Q vssd vssd vccd vccd pad_gpio_slow_sel sky130_fd_sc_hd__buf_16
X_079_ _088_/A gpio_defaults[4] vssd vssd vccd vccd _079_/Y sky130_fd_sc_hd__nand2b_2
XPHY_4 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
X_095_ _095_/A gpio_defaults[7] vssd vssd vccd vccd _095_/X sky130_fd_sc_hd__or2_0
XANTENNA_serial_load_out_buffer_A _101__9/A vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
X_100__8 _100__8/A vssd vssd vccd vccd _100__8/Y sky130_fd_sc_hd__inv_2
XANTENNA_input4_A resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
X_078_ _085_/A gpio_defaults[9] vssd vssd vccd vccd _078_/Y sky130_fd_sc_hd__nand2b_2
Xoutput19 _136_/X vssd vssd vccd vccd resetn_out sky130_fd_sc_hd__buf_16
XFILLER_7_98 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
X_103__8 _103__8/A vssd vssd vccd vccd _103__8/Y sky130_fd_sc_hd__inv_2
Xoutput19 _109_/Q vssd vssd vccd vccd pad_gpio_vtrip_sel sky130_fd_sc_hd__buf_16
XANTENNA__061__A0 user_gpio_oeb vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
X_103__11 _100__8/A vssd vssd vccd vccd _103__11/Y sky130_fd_sc_hd__inv_2
X_078_ _088_/A gpio_defaults[4] vssd vssd vccd vccd _078_/X sky130_fd_sc_hd__or2_0
XANTENNA__097__5_A _101__9/A vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XPHY_5 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
Xfanout21 _095_/A vssd vssd vccd vccd _091_/A sky130_fd_sc_hd__buf_2
XANTENNA__080__A_N _083_/A vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
X_094_ _091_/A gpio_defaults[6] vssd vssd vccd vccd _094_/Y sky130_fd_sc_hd__nand2b_2
X_077_ _089_/A gpio_defaults[9] vssd vssd vccd vccd _077_/X sky130_fd_sc_hd__or2_0
X_129_ _130_/CLK hold9/X _095_/A vssd vssd vccd vccd hold8/A sky130_fd_sc_hd__dfrtp_4
XANTENNA__058__1_A _101__9/A vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XFILLER_1_34 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
X_129_ _131_/CLK hold4/X _074_/A vssd vssd vccd vccd hold9/A sky130_fd_sc_hd__dfrtp_4
X_077_ _076_/A gpio_defaults[3] vssd vssd vccd vccd _077_/Y sky130_fd_sc_hd__nand2b_2
XPHY_6 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
Xfanout22 fanout28/X vssd vssd vccd vccd _095_/A sky130_fd_sc_hd__buf_2
X_093_ _095_/A gpio_defaults[6] vssd vssd vccd vccd _093_/X sky130_fd_sc_hd__or2_0
X_076_ _085_/A gpio_defaults[8] vssd vssd vccd vccd _076_/Y sky130_fd_sc_hd__nand2b_2
Xinput1 mgmt_gpio_oeb vssd vssd vccd vccd _067_/C sky130_fd_sc_hd__buf_2
X_128_ _130_/CLK _128_/D _095_/A vssd vssd vccd vccd hold9/A sky130_fd_sc_hd__dfrtp_4
X_093_ _092_/A gpio_defaults[7] vssd vssd vccd vccd _093_/Y sky130_fd_sc_hd__nand2b_2
X_076_ _076_/A gpio_defaults[3] vssd vssd vccd vccd _076_/X sky130_fd_sc_hd__or2_0
Xinput1 mgmt_gpio_oeb vssd vssd vccd vccd _063_/C sky130_fd_sc_hd__buf_2
X_128_ _131_/CLK hold7/X _074_/A vssd vssd vccd vccd hold4/A sky130_fd_sc_hd__dfrtp_4
XPHY_7 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
Xfanout23 _072_/A_N vssd vssd vccd vccd _083_/A sky130_fd_sc_hd__buf_2
X_092_ _091_/A gpio_defaults[5] vssd vssd vccd vccd _092_/Y sky130_fd_sc_hd__nand2b_2
Xgpio_in_buf _060_/Y gpio_in_buf/TE vssd vssd vccd vccd user_gpio_in sky130_fd_sc_hd__einvp_8
XANTENNA_input2_A mgmt_gpio_out vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
Xfanout23 _092_/A vssd vssd vccd vccd _088_/A sky130_fd_sc_hd__buf_2
X_092_ _092_/A gpio_defaults[7] vssd vssd vccd vccd _092_/X sky130_fd_sc_hd__or2_0
Xinput2 mgmt_gpio_out vssd vssd vccd vccd input2/X sky130_fd_sc_hd__buf_2
X_075_ _085_/A gpio_defaults[8] vssd vssd vccd vccd _075_/X sky130_fd_sc_hd__or2_0
X_127_ _130_/CLK _127_/D _091_/A vssd vssd vccd vccd _127_/Q sky130_fd_sc_hd__dfrtp_4
XANTENNA_input2_A mgmt_gpio_out vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
X_075_ _074_/A gpio_defaults[9] vssd vssd vccd vccd _075_/Y sky130_fd_sc_hd__nand2b_2
X_127_ _131_/CLK _127_/D _092_/A vssd vssd vccd vccd hold7/A sky130_fd_sc_hd__dfrtp_4
XANTENNA_clkbuf_0_serial_load_A serial_load vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XPHY_8 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
X_106__11 _103__8/A vssd vssd vccd vccd _106__11/Y sky130_fd_sc_hd__inv_2
Xfanout24 fanout28/X vssd vssd vccd vccd _072_/A_N sky130_fd_sc_hd__buf_2
XFILLER_19_55 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
X_095__3 _100__8/A vssd vssd vccd vccd _095__3/Y sky130_fd_sc_hd__inv_2
Xfanout24 fanout30/X vssd vssd vccd vccd _092_/A sky130_fd_sc_hd__buf_2
XANTENNA__102__10_A _101__9/A vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
X_074_ _074_/A gpio_defaults[9] vssd vssd vccd vccd _074_/X sky130_fd_sc_hd__or2_0
XTAP_70 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
Xinput3 pad_gpio_in vssd vssd vccd vccd _139_/A sky130_fd_sc_hd__buf_2
X_091_ _091_/A gpio_defaults[5] vssd vssd vccd vccd _091_/X sky130_fd_sc_hd__or2_0
X_074_ _083_/A gpio_defaults[2] vssd vssd vccd vccd _074_/Y sky130_fd_sc_hd__nand2b_2
X_126_ _130_/CLK hold6/X _091_/A vssd vssd vccd vccd _126_/Q sky130_fd_sc_hd__dfrtp_4
X_098__3 _103__8/A vssd vssd vccd vccd _098__3/Y sky130_fd_sc_hd__inv_2
Xinput3 pad_gpio_in vssd vssd vccd vccd _133_/A sky130_fd_sc_hd__buf_2
X_091_ _088_/A gpio_defaults[6] vssd vssd vccd vccd _091_/Y sky130_fd_sc_hd__nand2b_2
X_126_ _126_/CLK _126_/D _088_/A vssd vssd vccd vccd _126_/Q sky130_fd_sc_hd__dfrtp_4
XPHY_9 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
X_109_ _061__1/Y hold3/X _071_/X _072_/Y vssd vssd vccd vccd _109_/Q _109_/Q_N sky130_fd_sc_hd__dfbbn_2
Xfanout25 fanout28/X vssd vssd vccd vccd _089_/A sky130_fd_sc_hd__buf_2
X_109_ _096__4/Y hold4/X _074_/X _075_/Y vssd vssd vccd vccd _109_/Q _109_/Q_N sky130_fd_sc_hd__dfbbn_2
Xfanout25 _080_/A vssd vssd vccd vccd _076_/A sky130_fd_sc_hd__buf_2
XTAP_71 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
XTAP_60 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
X_090_ _092_/A gpio_defaults[6] vssd vssd vccd vccd _090_/X sky130_fd_sc_hd__or2_0
Xinput4 resetn vssd vssd vccd vccd input4/X sky130_fd_sc_hd__buf_2
X_090_ _136_/A gpio_defaults[12] vssd vssd vccd vccd _090_/Y sky130_fd_sc_hd__nand2b_2
X_073_ _083_/A gpio_defaults[2] vssd vssd vccd vccd _073_/X sky130_fd_sc_hd__or2_0
X_125_ _130_/CLK hold4/X _083_/A vssd vssd vccd vccd hold6/A sky130_fd_sc_hd__dfrtp_4
XANTENNA__073__A _083_/A vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
Xfanout26 fanout28/X vssd vssd vccd vccd _136_/A sky130_fd_sc_hd__buf_2
XFILLER_5_80 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
X_073_ _074_/A gpio_defaults[8] vssd vssd vccd vccd _073_/Y sky130_fd_sc_hd__nand2b_2
X_125_ _126_/CLK _125_/D _088_/A vssd vssd vccd vccd _125_/Q sky130_fd_sc_hd__dfrtp_4
XFILLER_7_26 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
XANTENNA__062__B user_gpio_out vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
X_108_ _095__3/Y hold7/X _072_/X _073_/Y vssd vssd vccd vccd _108_/Q _108_/Q_N sky130_fd_sc_hd__dfbbn_2
XANTENNA__070__B gpio_defaults[2] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XANTENNA__098__6_A _101__9/A vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
Xfanout26 fanout30/X vssd vssd vccd vccd _080_/A sky130_fd_sc_hd__buf_2
XTAP_72 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
X_072_ _074_/A gpio_defaults[8] vssd vssd vccd vccd _072_/X sky130_fd_sc_hd__or2_0
XTAP_61 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
X_072_ _072_/A_N gpio_defaults[0] vssd vssd vccd vccd _072_/Y sky130_fd_sc_hd__nand2b_2
Xinput5 serial_data_in vssd vssd vccd vccd _119_/D sky130_fd_sc_hd__buf_2
XTAP_50 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
Xinput5 serial_data_in vssd vssd vccd vccd _122_/D sky130_fd_sc_hd__buf_2
X_124_ _130_/CLK hold5/X _072_/A_N vssd vssd vccd vccd hold4/A sky130_fd_sc_hd__dfrtp_4
XANTENNA__073__B gpio_defaults[2] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
Xfanout27 fanout28/X vssd vssd vccd vccd _085_/A sky130_fd_sc_hd__buf_2
XANTENNA__079__A _083_/A vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XANTENNA__076__B gpio_defaults[8] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XANTENNA__081__B gpio_defaults[4] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XANTENNA__073__B gpio_defaults[8] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
X_124_ _126_/CLK _124_/D _092_/A vssd vssd vccd vccd _124_/Q sky130_fd_sc_hd__dfrtp_4
XANTENNA__101__9_A _101__9/A vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XANTENNA__068__B gpio_defaults[0] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
X_107_ _094__2/Y hold8/X _070_/X _071_/Y vssd vssd vccd vccd _107_/Q _107_/Q_N sky130_fd_sc_hd__dfbbn_2
Xfanout27 _134_/A vssd vssd vccd vccd _074_/A sky130_fd_sc_hd__buf_2
XANTENNA__081__B gpio_defaults[1] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XANTENNA__076__B gpio_defaults[3] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XTAP_73 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
X_071_ _089_/A gpio_defaults[0] vssd vssd vccd vccd _071_/X sky130_fd_sc_hd__or2_0
X_071_ _076_/A gpio_defaults[2] vssd vssd vccd vccd _071_/Y sky130_fd_sc_hd__nand2b_2
XTAP_62 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
XTAP_51 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
X_123_ _130_/CLK hold3/X _072_/A_N vssd vssd vccd vccd hold5/A sky130_fd_sc_hd__dfrtp_4
XANTENNA__084__B gpio_defaults[1] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
Xfanout28 input4/X vssd vssd vccd vccd fanout28/X sky130_fd_sc_hd__buf_2
XANTENNA__079__B gpio_defaults[3] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
X_106_ _058__1/Y hold5/X _068_/X _069_/Y vssd vssd vccd vccd _106_/Q _106_/Q_N sky130_fd_sc_hd__dfbbn_2
X_123_ _126_/CLK hold6/X _092_/A vssd vssd vccd vccd _123_/Q sky130_fd_sc_hd__dfrtp_4
X_098__6 _101__9/A vssd vssd vccd vccd _098__6/Y sky130_fd_sc_hd__inv_2
XANTENNA__084__B gpio_defaults[11] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XANTENNA__079__B gpio_defaults[4] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
Xfanout28 _134_/A vssd vssd vccd vccd _086_/A sky130_fd_sc_hd__buf_2
XTAP_63 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
X_070_ _068_/X _069_/Y _066_/Y vssd vssd vccd vccd _070_/Y sky130_fd_sc_hd__o21ai_4
XTAP_52 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
XANTENNA__092__B gpio_defaults[5] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XANTENNA__087__B gpio_defaults[11] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
X_122_ _134_/CLK _122_/D _072_/A_N vssd vssd vccd vccd hold3/A sky130_fd_sc_hd__dfrtp_4
XANTENNA__095__B gpio_defaults[7] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
Xserial_clock_out_buffer _134_/CLK vssd vssd vccd vccd serial_clock_out sky130_fd_sc_hd__clkbuf_16
X_070_ _076_/A gpio_defaults[2] vssd vssd vccd vccd _070_/X sky130_fd_sc_hd__or2_0
XANTENNA__092__B gpio_defaults[7] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XANTENNA__087__B gpio_defaults[12] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
X_122_ _126_/CLK hold8/X _076_/A vssd vssd vccd vccd hold6/A sky130_fd_sc_hd__dfrtp_4
Xserial_clock_out_buffer _126_/CLK vssd vssd vccd vccd serial_clock_out sky130_fd_sc_hd__clkbuf_16
Xfanout29 fanout30/X vssd vssd vccd vccd _134_/A sky130_fd_sc_hd__buf_2
XTAP_64 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
XTAP_53 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
XTAP_42 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
XFILLER_2_52 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
X_121_ _108__13/Y hold8/X _095_/X _096_/Y vssd vssd vccd vccd _121_/Q _121_/Q_N sky130_fd_sc_hd__dfbbn_2
XFILLER_2_41 vssd vssd vccd vccd sky130_fd_sc_hd__decap_8
X_121_ _126_/CLK hold3/X _080_/A vssd vssd vccd vccd hold8/A sky130_fd_sc_hd__dfrtp_4
XTAP_65 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
XTAP_54 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
X_101__6 _103__8/A vssd vssd vccd vccd _101__6/Y sky130_fd_sc_hd__inv_2
XTAP_43 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
X_120_ _107__12/Y hold9/X _093_/X _094_/Y vssd vssd vccd vccd _120_/Q _120_/Q_N sky130_fd_sc_hd__dfbbn_2
XFILLER_2_42 vssd vssd vccd vccd sky130_fd_sc_hd__decap_6
XFILLER_8_52 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
X_120_ _126_/CLK hold5/X _076_/A vssd vssd vccd vccd hold3/A sky130_fd_sc_hd__dfrtp_4
X_102__10 _101__9/A vssd vssd vccd vccd _102__10/Y sky130_fd_sc_hd__inv_2
X_058__1 _101__9/A vssd vssd vccd vccd _058__1/Y sky130_fd_sc_hd__inv_2
Xhold1 hold1/A vssd vssd vccd vccd hold1/X sky130_fd_sc_hd__dlygate4sd3_1
XANTENNA__099__7_A _101__9/A vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XTAP_66 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
XTAP_55 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
XFILLER_2_32 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
XTAP_44 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
Xhold2 hold2/A vssd vssd vccd vccd hold2/X sky130_fd_sc_hd__dlygate4sd3_1
Xclkbuf_0_serial_load serial_load vssd vssd vccd vccd clkbuf_0_serial_load/X sky130_fd_sc_hd__clkbuf_16
Xclkbuf_1_0__f_serial_clock clkbuf_0_serial_clock/X vssd vssd vccd vccd _130_/CLK
Xclkbuf_1_0__f_serial_clock clkbuf_0_serial_clock/X vssd vssd vccd vccd _126_/CLK
+ sky130_fd_sc_hd__clkbuf_16
XTAP_67 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
XTAP_56 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
Xgpio_logic_high gpio_in_buf/TE vccd1 vssd1 gpio_logic_high
Xgpio_logic_high _067_/A vccd1 vssd1 gpio_logic_high
XTAP_45 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
XFILLER_5_98 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
XPHY_40 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
Xone_buffer one_buffer/A vssd vssd vccd vccd one sky130_fd_sc_hd__buf_16
XFILLER_8_98 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
XFILLER_8_65 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
Xhold3 hold3/A vssd vssd vccd vccd hold3/X sky130_fd_sc_hd__dlygate4sd3_1
XPHY_41 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
X_101__9 _101__9/A vssd vssd vccd vccd _101__9/Y sky130_fd_sc_hd__inv_2
XTAP_68 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
XPHY_30 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
XTAP_57 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
XTAP_46 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
X_105__10 _104__9/A vssd vssd vccd vccd _105__10/Y sky130_fd_sc_hd__inv_2
XANTENNA_fanout28_A _134_/A vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
Xhold4 hold4/A vssd vssd vccd vccd hold4/X sky130_fd_sc_hd__dlygate4sd3_1
X_104__9 _104__9/A vssd vssd vccd vccd _104__9/Y sky130_fd_sc_hd__inv_2
XFILLER_8_99 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
XTAP_69 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
XFILLER_14_98 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
XTAP_58 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
XFILLER_5_56 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
XFILLER_5_34 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
XTAP_47 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
XPHY_31 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
XPHY_20 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
XFILLER_0_3 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
XFILLER_17_98 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
XANTENNA__134__A _134_/A vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
Xhold5 hold5/A vssd vssd vccd vccd hold5/X sky130_fd_sc_hd__dlygate4sd3_1
XPHY_32 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
XTAP_59 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
XPHY_21 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
XPHY_10 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
XTAP_48 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
X_089_ _089_/A gpio_defaults[12] vssd vssd vccd vccd _089_/X sky130_fd_sc_hd__or2_0
XFILLER_17_99 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
Xhold6 hold6/A vssd vssd vccd vccd hold6/X sky130_fd_sc_hd__dlygate4sd3_1
X_089_ _088_/A gpio_defaults[5] vssd vssd vccd vccd _089_/Y sky130_fd_sc_hd__nand2b_2
Xzero_buffer zero_buffer/A vssd vssd vccd vccd zero sky130_fd_sc_hd__buf_16
XTAP_49 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
XFILLER_0_91 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
XPHY_33 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
Xclkbuf_0_serial_clock serial_clock vssd vssd vccd vccd clkbuf_0_serial_clock/X sky130_fd_sc_hd__clkbuf_16
XPHY_22 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
XANTENNA_input5_A serial_data_in vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XFILLER_2_48 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
XPHY_11 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
XFILLER_3_80 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
X_088_ _089_/A gpio_defaults[11] vssd vssd vccd vccd _088_/Y sky130_fd_sc_hd__nand2b_2
XANTENNA_input5_A serial_data_in vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
X_105__13 _100__8/A vssd vssd vccd vccd _105__13/Y sky130_fd_sc_hd__inv_2
X_088_ _088_/A gpio_defaults[5] vssd vssd vccd vccd _088_/X sky130_fd_sc_hd__or2_0
Xhold7 hold7/A vssd vssd vccd vccd hold7/X sky130_fd_sc_hd__dlygate4sd3_1
XFILLER_5_26 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
X_096__4 _100__8/A vssd vssd vccd vccd _096__4/Y sky130_fd_sc_hd__inv_2
XPHY_12 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
XPHY_34 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
XPHY_23 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
X_087_ _089_/A gpio_defaults[11] vssd vssd vccd vccd _087_/X sky130_fd_sc_hd__or2_0
X_099__4 _104__9/A vssd vssd vccd vccd _099__4/Y sky130_fd_sc_hd__inv_2
XFILLER_2_49 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
Xhold8 hold8/A vssd vssd vccd vccd hold8/X sky130_fd_sc_hd__dlygate4sd3_1
Xclkbuf_1_1__f_serial_load clkbuf_0_serial_load/X vssd vssd vccd vccd _104__9/A sky130_fd_sc_hd__clkbuf_16
XANTENNA__071__B gpio_defaults[0] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
X_139_ _139_/A _063_/Y vssd vssd vccd vccd mgmt_gpio_in sky130_fd_sc_hd__ebufn_8
XANTENNA__066__B user_gpio_out vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XFILLER_17_57 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
X_087_ _086_/A gpio_defaults[12] vssd vssd vccd vccd _087_/Y sky130_fd_sc_hd__nand2b_2
Xclkbuf_1_1__f_serial_load clkbuf_0_serial_load/X vssd vssd vccd vccd _101__9/A sky130_fd_sc_hd__clkbuf_16
XANTENNA__082__A _134_/A vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XANTENNA__071__B gpio_defaults[2] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XPHY_35 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
XPHY_24 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
XPHY_13 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
X_086_ _085_/A gpio_defaults[10] vssd vssd vccd vccd _086_/Y sky130_fd_sc_hd__nand2b_2
Xclkbuf_1_1__f_serial_clock clkbuf_0_serial_clock/X vssd vssd vccd vccd _134_/CLK
Xclkbuf_1_1__f_serial_clock clkbuf_0_serial_clock/X vssd vssd vccd vccd _131_/CLK
+ sky130_fd_sc_hd__clkbuf_16
XANTENNA__074__B gpio_defaults[2] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
X_086_ _086_/A gpio_defaults[12] vssd vssd vccd vccd _086_/X sky130_fd_sc_hd__or2_0
XANTENNA__074__B gpio_defaults[9] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
X_069_ _080_/A gpio_defaults[0] vssd vssd vccd vccd _069_/Y sky130_fd_sc_hd__nand2b_2
Xhold9 hold9/A vssd vssd vccd vccd hold9/X sky130_fd_sc_hd__dlygate4sd3_1
X_069_ input2/X _068_/B _109_/Q vssd vssd vccd vccd _069_/Y sky130_fd_sc_hd__o21ai_2
X_108__13 _103__8/A vssd vssd vccd vccd _108__13/Y sky130_fd_sc_hd__inv_2
XANTENNA__082__B gpio_defaults[4] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XANTENNA__069__B gpio_defaults[0] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XANTENNA__082__B gpio_defaults[10] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XPHY_36 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
XANTENNA__077__B gpio_defaults[9] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XPHY_25 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
XANTENNA__077__B gpio_defaults[3] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XPHY_14 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
XANTENNA__132__RESET_B _134_/A vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XANTENNA_input3_A pad_gpio_in vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XANTENNA__090__B gpio_defaults[12] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XANTENNA__085__B gpio_defaults[10] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
X_085_ _085_/A gpio_defaults[10] vssd vssd vccd vccd _085_/X sky130_fd_sc_hd__or2_0
X_068_ _116_/Q_N _068_/B vssd vssd vccd vccd _068_/X sky130_fd_sc_hd__and2b_2
X_085_ _086_/A gpio_defaults[11] vssd vssd vccd vccd _085_/Y sky130_fd_sc_hd__nand2b_2
XANTENNA__090__B gpio_defaults[6] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XANTENNA__085__B gpio_defaults[11] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
X_068_ _086_/A gpio_defaults[0] vssd vssd vccd vccd _068_/X sky130_fd_sc_hd__or2_0
XPHY_37 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
XANTENNA__093__B gpio_defaults[6] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XPHY_26 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
XPHY_15 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
XANTENNA__088__B gpio_defaults[11] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
X_067_ _118_/Q _117_/Q _067_/C vssd vssd vccd vccd _068_/B sky130_fd_sc_hd__and3b_2
X_136_ _136_/A vssd vssd vccd vccd _136_/X sky130_fd_sc_hd__buf_2
X_084_ _083_/A gpio_defaults[1] vssd vssd vccd vccd _084_/Y sky130_fd_sc_hd__nand2b_2
XANTENNA__096__B gpio_defaults[7] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
X_119_ _106__11/Y _128_/D _091_/X _092_/Y vssd vssd vccd vccd _119_/Q _119_/Q_N sky130_fd_sc_hd__dfbbn_2
X_062__14 _130_/CLK vssd vssd vccd vccd _135_/CLK sky130_fd_sc_hd__inv_2
XANTENNA__093__B gpio_defaults[7] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XANTENNA__088__B gpio_defaults[5] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XANTENNA__094__2_A _101__9/A vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XFILLER_3_84 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
X_084_ _086_/A gpio_defaults[11] vssd vssd vccd vccd _084_/X sky130_fd_sc_hd__or2_0
X_099__7 _101__9/A vssd vssd vccd vccd _099__7/Y sky130_fd_sc_hd__inv_2
X_067_ _067_/A _133_/A vssd vssd vccd vccd _067_/X sky130_fd_sc_hd__and2_2
X_119_ _126_/CLK _119_/D _080_/A vssd vssd vccd vccd hold5/A sky130_fd_sc_hd__dfrtp_4
XPHY_38 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
XPHY_27 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
XPHY_16 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
X_083_ _083_/A gpio_defaults[1] vssd vssd vccd vccd _083_/X sky130_fd_sc_hd__or2_0
X_118_ _105__10/Y hold7/X _089_/X _090_/Y vssd vssd vccd vccd _118_/Q _118_/Q_N sky130_fd_sc_hd__dfbbn_2
X_135_ _135_/CLK hold7/A _136_/A vssd vssd vccd vccd _135_/Q sky130_fd_sc_hd__dfrtp_2
X_061__1 _104__9/A vssd vssd vccd vccd _061__1/Y sky130_fd_sc_hd__inv_2
X_066_ _109_/Q user_gpio_out vssd vssd vccd vccd _066_/Y sky130_fd_sc_hd__nand2b_2
XFILLER_0_31 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
X_083_ _074_/A gpio_defaults[10] vssd vssd vccd vccd _083_/Y sky130_fd_sc_hd__nand2b_2
XFILLER_3_52 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
X_066_ _064_/X _065_/Y _062_/Y vssd vssd vccd vccd _066_/Y sky130_fd_sc_hd__o21ai_4
X_118_ _105__13/Y _127_/D _092_/X _093_/Y vssd vssd vccd vccd _118_/Q _118_/Q_N sky130_fd_sc_hd__dfbbn_2
XPHY_39 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
XFILLER_15_50 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
XPHY_28 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
XPHY_17 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
X_134_ _134_/CLK hold2/X _089_/A vssd vssd vccd vccd hold7/A sky130_fd_sc_hd__dfrtp_4
X_065_ user_gpio_oeb _064_/X _109_/Q vssd vssd vccd vccd _065_/X sky130_fd_sc_hd__mux2_4
X_082_ _091_/A gpio_defaults[4] vssd vssd vccd vccd _082_/Y sky130_fd_sc_hd__nand2b_2
Xserial_load_out_buffer _104__9/A vssd vssd vccd vccd serial_load_out sky130_fd_sc_hd__clkbuf_16
X_065_ input2/X _064_/B _106_/Q vssd vssd vccd vccd _065_/Y sky130_fd_sc_hd__o21ai_2
X_082_ _134_/A gpio_defaults[10] vssd vssd vccd vccd _082_/X sky130_fd_sc_hd__or2_0
X_134_ _134_/A vssd vssd vccd vccd _134_/X sky130_fd_sc_hd__buf_2
Xserial_load_out_buffer _101__9/A vssd vssd vccd vccd serial_load_out sky130_fd_sc_hd__clkbuf_16
XANTENNA_input1_A mgmt_gpio_oeb vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
X_117_ _104__9/Y hold2/X _087_/X _088_/Y vssd vssd vccd vccd _117_/Q _117_/Q_N sky130_fd_sc_hd__dfbbn_2
X_117_ _104__12/Y _126_/D _090_/X _091_/Y vssd vssd vccd vccd _117_/Q _117_/Q_N sky130_fd_sc_hd__dfbbn_2
XPHY_29 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
X_102__7 _104__9/A vssd vssd vccd vccd _102__7/Y sky130_fd_sc_hd__inv_2
XPHY_18 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
X_081_ _091_/A gpio_defaults[4] vssd vssd vccd vccd _081_/X sky130_fd_sc_hd__or2_0
X_133_ _134_/CLK _133_/D _089_/A vssd vssd vccd vccd hold2/A sky130_fd_sc_hd__dfrtp_4
X_064_ _115_/Q _067_/C vssd vssd vccd vccd _064_/X sky130_fd_sc_hd__and2_0
X_081_ _076_/A gpio_defaults[1] vssd vssd vccd vccd _081_/Y sky130_fd_sc_hd__nand2b_2
XFILLER_3_43 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
X_064_ _113_/Q_N _064_/B vssd vssd vccd vccd _064_/X sky130_fd_sc_hd__and2b_2
XFILLER_0_33 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
X_133_ _133_/A vssd vssd vccd vccd _133_/X sky130_fd_sc_hd__buf_2
X_116_ _103__11/Y _125_/D _088_/X _089_/Y vssd vssd vccd vccd _116_/Q _116_/Q_N sky130_fd_sc_hd__dfbbn_2
XPHY_19 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
X_116_ _103__8/Y _133_/D _085_/X _086_/Y vssd vssd vccd vccd _116_/Q _116_/Q_N sky130_fd_sc_hd__dfbbn_2
XANTENNA_clkbuf_0_serial_clock_A serial_clock vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
X_063_ _113_/Q _115_/Q vssd vssd vccd vccd _063_/Y sky130_fd_sc_hd__nand2b_2
X_132_ _134_/CLK hold1/X _085_/A vssd vssd vccd vccd _132_/Q sky130_fd_sc_hd__dfrtp_4
X_080_ _083_/A gpio_defaults[3] vssd vssd vccd vccd _080_/Y sky130_fd_sc_hd__nand2b_2
X_115_ _102__7/Y hold5/X _083_/X _084_/Y vssd vssd vccd vccd _115_/Q _115_/Q_N sky130_fd_sc_hd__dfbbn_2
Xoutput6 _119_/Q vssd vssd vccd vccd pad_gpio_ana_en sky130_fd_sc_hd__buf_16
X_132_ _132_/CLK hold2/A _134_/A vssd vssd vccd vccd _132_/Q sky130_fd_sc_hd__dfrtp_2
X_063_ _115_/Q _114_/Q _063_/C vssd vssd vccd vccd _064_/B sky130_fd_sc_hd__and3b_2
X_080_ _080_/A gpio_defaults[1] vssd vssd vccd vccd _080_/X sky130_fd_sc_hd__or2_0
X_115_ _102__10/Y hold2/X _086_/X _087_/Y vssd vssd vccd vccd _115_/Q _115_/Q_N sky130_fd_sc_hd__dfbbn_2
Xoutput6 _133_/X vssd vssd vccd vccd mgmt_gpio_in sky130_fd_sc_hd__buf_16
.ends

8
verilog/dv/caravel/defs.h
View File

@ -216,15 +216,15 @@ extern uint32_t flashio_worker_end;
// Useful GPIO mode values
#define GPIO_MODE_MGMT_STD_INPUT_NOPULL 0x0403
#define GPIO_MODE_MGMT_STD_INPUT_PULLDOWN 0x0801
#define GPIO_MODE_MGMT_STD_INPUT_PULLUP 0x0c01
#define GPIO_MODE_MGMT_STD_INPUT_PULLDOWN 0x0c01
#define GPIO_MODE_MGMT_STD_INPUT_PULLUP 0x0801
#define GPIO_MODE_MGMT_STD_OUTPUT 0x1809
#define GPIO_MODE_MGMT_STD_BIDIRECTIONAL 0x1801
#define GPIO_MODE_MGMT_STD_ANALOG 0x000b
#define GPIO_MODE_USER_STD_INPUT_NOPULL 0x0402
#define GPIO_MODE_USER_STD_INPUT_PULLDOWN 0x0800
#define GPIO_MODE_USER_STD_INPUT_PULLUP 0x0c00
#define GPIO_MODE_USER_STD_INPUT_PULLDOWN 0x0c00
#define GPIO_MODE_USER_STD_INPUT_PULLUP 0x0800
#define GPIO_MODE_USER_STD_OUTPUT 0x1808
#define GPIO_MODE_USER_STD_BIDIRECTIONAL 0x1800
#define GPIO_MODE_USER_STD_OUT_MONITORED 0x1802

10
verilog/gl/caravan.v
View File

@ -3802,12 +3802,12 @@ module caravan(vddio, vddio_2, vssio, vssio_2, vdda, vssa, vccd, vssd, vdda1, vd
.vssd1(vssd1_core),
.zero()
);
gpio_defaults_block_1803 \gpio_defaults_block_0[0] (
gpio_defaults_block_1803 gpio_defaults_block_0 (
.VGND(vssd_core),
.VPWR(vccd_core),
.gpio_defaults({ \gpio_defaults[12] , \gpio_defaults[11] , \gpio_defaults[10] , \gpio_defaults[9] , \gpio_defaults[8] , \gpio_defaults[7] , \gpio_defaults[6] , \gpio_defaults[5] , \gpio_defaults[4] , \gpio_defaults[3] , \gpio_defaults[2] , \gpio_defaults[1] , \gpio_defaults[0] })
);
gpio_defaults_block_1803 \gpio_defaults_block_0[1] (
gpio_defaults_block_1803 gpio_defaults_block_1 (
.VGND(vssd_core),
.VPWR(vccd_core),
.gpio_defaults({ \gpio_defaults[25] , \gpio_defaults[24] , \gpio_defaults[23] , \gpio_defaults[22] , \gpio_defaults[21] , \gpio_defaults[20] , \gpio_defaults[19] , \gpio_defaults[18] , \gpio_defaults[17] , \gpio_defaults[16] , \gpio_defaults[15] , \gpio_defaults[14] , \gpio_defaults[13] })
@ -3857,17 +3857,17 @@ module caravan(vddio, vddio_2, vssio, vssio_2, vdda, vssa, vccd, vssd, vdda1, vd
.VPWR(vccd_core),
.gpio_defaults({ \gpio_defaults[246] , \gpio_defaults[245] , \gpio_defaults[244] , \gpio_defaults[243] , \gpio_defaults[242] , \gpio_defaults[241] , \gpio_defaults[240] , \gpio_defaults[239] , \gpio_defaults[238] , \gpio_defaults[237] , \gpio_defaults[236] , \gpio_defaults[235] , \gpio_defaults[234] })
);
gpio_defaults_block_0403 \gpio_defaults_block_2[0] (
gpio_defaults_block_0403 gpio_defaults_block_2 (
.VGND(vssd_core),
.VPWR(vccd_core),
.gpio_defaults({ \gpio_defaults[38] , \gpio_defaults[37] , \gpio_defaults[36] , \gpio_defaults[35] , \gpio_defaults[34] , \gpio_defaults[33] , \gpio_defaults[32] , \gpio_defaults[31] , \gpio_defaults[30] , \gpio_defaults[29] , \gpio_defaults[28] , \gpio_defaults[27] , \gpio_defaults[26] })
);
gpio_defaults_block_0403 \gpio_defaults_block_2[1] (
gpio_defaults_block_0801 gpio_defaults_block_3 (
.VGND(vssd_core),
.VPWR(vccd_core),
.gpio_defaults({ \gpio_defaults[51] , \gpio_defaults[50] , \gpio_defaults[49] , \gpio_defaults[48] , \gpio_defaults[47] , \gpio_defaults[46] , \gpio_defaults[45] , \gpio_defaults[44] , \gpio_defaults[43] , \gpio_defaults[42] , \gpio_defaults[41] , \gpio_defaults[40] , \gpio_defaults[39] })
);
gpio_defaults_block_0403 \gpio_defaults_block_2[2] (
gpio_defaults_block_0403 gpio_defaults_block_4 (
.VGND(vssd_core),
.VPWR(vccd_core),
.gpio_defaults({ \gpio_defaults[64] , \gpio_defaults[63] , \gpio_defaults[62] , \gpio_defaults[61] , \gpio_defaults[60] , \gpio_defaults[59] , \gpio_defaults[58] , \gpio_defaults[57] , \gpio_defaults[56] , \gpio_defaults[55] , \gpio_defaults[54] , \gpio_defaults[53] , \gpio_defaults[52] })

10
verilog/gl/caravel.v
View File

@ -4493,12 +4493,12 @@ module caravel(vddio, vddio_2, vssio, vssio_2, vdda, vssa, vccd, vssd, vdda1, vd
.vssd1(vssd1_core),
.zero()
);
gpio_defaults_block_1803 \gpio_defaults_block_0[0] (
gpio_defaults_block_1803 gpio_defaults_block_0 (
.VGND(vssd_core),
.VPWR(vccd_core),
.gpio_defaults({ \gpio_defaults[12] , \gpio_defaults[11] , \gpio_defaults[10] , \gpio_defaults[9] , \gpio_defaults[8] , \gpio_defaults[7] , \gpio_defaults[6] , \gpio_defaults[5] , \gpio_defaults[4] , \gpio_defaults[3] , \gpio_defaults[2] , \gpio_defaults[1] , \gpio_defaults[0] })
);
gpio_defaults_block_1803 \gpio_defaults_block_0[1] (
gpio_defaults_block_1803 gpio_defaults_block_1 (
.VGND(vssd_core),
.VPWR(vccd_core),
.gpio_defaults({ \gpio_defaults[25] , \gpio_defaults[24] , \gpio_defaults[23] , \gpio_defaults[22] , \gpio_defaults[21] , \gpio_defaults[20] , \gpio_defaults[19] , \gpio_defaults[18] , \gpio_defaults[17] , \gpio_defaults[16] , \gpio_defaults[15] , \gpio_defaults[14] , \gpio_defaults[13] })
@ -4603,17 +4603,17 @@ module caravel(vddio, vddio_2, vssio, vssio_2, vdda, vssa, vccd, vssd, vdda1, vd
.VPWR(vccd_core),
.gpio_defaults({ \gpio_defaults[389] , \gpio_defaults[388] , \gpio_defaults[387] , \gpio_defaults[386] , \gpio_defaults[385] , \gpio_defaults[384] , \gpio_defaults[383] , \gpio_defaults[382] , \gpio_defaults[381] , \gpio_defaults[380] , \gpio_defaults[379] , \gpio_defaults[378] , \gpio_defaults[377] })
);
gpio_defaults_block_0403 \gpio_defaults_block_2[0] (
gpio_defaults_block_0403 gpio_defaults_block_2 (
.VGND(vssd_core),
.VPWR(vccd_core),
.gpio_defaults({ \gpio_defaults[38] , \gpio_defaults[37] , \gpio_defaults[36] , \gpio_defaults[35] , \gpio_defaults[34] , \gpio_defaults[33] , \gpio_defaults[32] , \gpio_defaults[31] , \gpio_defaults[30] , \gpio_defaults[29] , \gpio_defaults[28] , \gpio_defaults[27] , \gpio_defaults[26] })
);
gpio_defaults_block_0403 \gpio_defaults_block_2[1] (
gpio_defaults_block_0801 gpio_defaults_block_3 (
.VGND(vssd_core),
.VPWR(vccd_core),
.gpio_defaults({ \gpio_defaults[51] , \gpio_defaults[50] , \gpio_defaults[49] , \gpio_defaults[48] , \gpio_defaults[47] , \gpio_defaults[46] , \gpio_defaults[45] , \gpio_defaults[44] , \gpio_defaults[43] , \gpio_defaults[42] , \gpio_defaults[41] , \gpio_defaults[40] , \gpio_defaults[39] })
);
gpio_defaults_block_0403 \gpio_defaults_block_2[2] (
gpio_defaults_block_0403 gpio_defaults_block_4 (
.VGND(vssd_core),
.VPWR(vccd_core),
.gpio_defaults({ \gpio_defaults[64] , \gpio_defaults[63] , \gpio_defaults[62] , \gpio_defaults[61] , \gpio_defaults[60] , \gpio_defaults[59] , \gpio_defaults[58] , \gpio_defaults[57] , \gpio_defaults[56] , \gpio_defaults[55] , \gpio_defaults[54] , \gpio_defaults[53] , \gpio_defaults[52] })

1128
verilog/gl/gpio_control_block.v
View File

File diff suppressed because it is too large Load Diff

260
verilog/gl/gpio_defaults_block_0801.v Normal file
View File

@ -0,0 +1,260 @@
module gpio_defaults_block_0801 (VGND,
VPWR,
gpio_defaults);
input VGND;
input VPWR;
output [12:0] gpio_defaults;
wire \gpio_defaults_low[0] ;
wire \gpio_defaults_high[10] ;
wire \gpio_defaults_low[11] ;
wire \gpio_defaults_low[12] ;
wire \gpio_defaults_high[1] ;
wire \gpio_defaults_low[2] ;
wire \gpio_defaults_low[3] ;
wire \gpio_defaults_low[4] ;
wire \gpio_defaults_low[5] ;
wire \gpio_defaults_low[6] ;
wire \gpio_defaults_low[7] ;
wire \gpio_defaults_low[8] ;
wire \gpio_defaults_low[9] ;
wire \gpio_defaults_high[0] ;
wire \gpio_defaults_high[11] ;
wire \gpio_defaults_high[12] ;
wire \gpio_defaults_high[2] ;
wire \gpio_defaults_high[3] ;
wire \gpio_defaults_high[4] ;
wire \gpio_defaults_high[5] ;
wire \gpio_defaults_high[6] ;
wire \gpio_defaults_high[7] ;
wire \gpio_defaults_high[8] ;
wire \gpio_defaults_high[9] ;
wire \gpio_defaults_low[10] ;
wire \gpio_defaults_low[1] ;
sky130_fd_sc_hd__fill_1 FILLER_0_29 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_6 FILLER_0_3 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__fill_2 FILLER_0_33 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__fill_2 FILLER_0_38 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__fill_2 FILLER_0_43 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__fill_1 FILLER_0_48 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__fill_1 FILLER_0_55 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__fill_2 FILLER_0_60 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__fill_1 FILLER_0_9 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_12 FILLER_1_15 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_12 FILLER_1_27 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_12 FILLER_1_3 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_12 FILLER_1_39 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_4 FILLER_1_51 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__fill_1 FILLER_1_55 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_4 FILLER_1_57 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__fill_1 FILLER_1_61 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_12 FILLER_2_15 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__fill_1 FILLER_2_27 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_12 FILLER_2_29 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_12 FILLER_2_3 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_12 FILLER_2_41 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 FILLER_2_53 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_4 FILLER_2_57 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__fill_1 FILLER_2_61 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_0 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_1 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_2 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_3 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_4 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_5 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_10 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_6 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_7 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_8 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_9 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__conb_1 \gpio_default_value[0] (.HI(\gpio_defaults_high[0] ),
.LO(\gpio_defaults_low[0] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__conb_1 \gpio_default_value[10] (.HI(\gpio_defaults_high[10] ),
.LO(\gpio_defaults_low[10] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__conb_1 \gpio_default_value[11] (.HI(\gpio_defaults_high[11] ),
.LO(\gpio_defaults_low[11] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__conb_1 \gpio_default_value[12] (.HI(\gpio_defaults_high[12] ),
.LO(\gpio_defaults_low[12] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__conb_1 \gpio_default_value[1] (.HI(\gpio_defaults_high[1] ),
.LO(\gpio_defaults_low[1] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__conb_1 \gpio_default_value[2] (.HI(\gpio_defaults_high[2] ),
.LO(\gpio_defaults_low[2] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__conb_1 \gpio_default_value[3] (.HI(\gpio_defaults_high[3] ),
.LO(\gpio_defaults_low[3] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__conb_1 \gpio_default_value[4] (.HI(\gpio_defaults_high[4] ),
.LO(\gpio_defaults_low[4] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__conb_1 \gpio_default_value[5] (.HI(\gpio_defaults_high[5] ),
.LO(\gpio_defaults_low[5] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__conb_1 \gpio_default_value[6] (.HI(\gpio_defaults_high[6] ),
.LO(\gpio_defaults_low[6] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__conb_1 \gpio_default_value[7] (.HI(\gpio_defaults_high[7] ),
.LO(\gpio_defaults_low[7] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__conb_1 \gpio_default_value[8] (.HI(\gpio_defaults_high[8] ),
.LO(\gpio_defaults_low[8] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__conb_1 \gpio_default_value[9] (.HI(\gpio_defaults_high[9] ),
.LO(\gpio_defaults_low[9] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
assign gpio_defaults[0] = \gpio_defaults_high[0] ;
assign gpio_defaults[1] = \gpio_defaults_low[1] ;
assign gpio_defaults[2] = \gpio_defaults_low[2] ;
assign gpio_defaults[3] = \gpio_defaults_low[3] ;
assign gpio_defaults[4] = \gpio_defaults_low[4] ;
assign gpio_defaults[5] = \gpio_defaults_low[5] ;
assign gpio_defaults[6] = \gpio_defaults_low[6] ;
assign gpio_defaults[7] = \gpio_defaults_low[7] ;
assign gpio_defaults[8] = \gpio_defaults_low[8] ;
assign gpio_defaults[9] = \gpio_defaults_low[9] ;
assign gpio_defaults[10] = \gpio_defaults_low[10] ;
assign gpio_defaults[11] = \gpio_defaults_high[11] ;
assign gpio_defaults[12] = \gpio_defaults_low[12] ;
endmodule

132
verilog/rtl/caravan.v
View File

@ -165,6 +165,7 @@ module caravan (
wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] mprj_io_in;
wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] mprj_io_in_3v3;
wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] mprj_io_out;
wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] mprj_io_one;
// User Project Control (user-facing)
// 27 GPIO bidirectional with in/out/oeb and a 3.3V copy of the input
@ -208,10 +209,10 @@ module caravan (
// ser_tx = mprj_io[6] (output)
// irq = mprj_io[7] (input)
wire [`MPRJ_IO_PADS-1:0] mgmt_io_in; /* one- and three-pin data */
wire [`MPRJ_IO_PADS-1:0] mgmt_io_nc; /* no-connects */
wire [4:0] mgmt_io_out; /* three-pin interface out */
wire [4:0] mgmt_io_oeb; /* three-pin output enable */
wire [`MPRJ_IO_PADS-1:0] mgmt_io_in; /* one- and three-pin data in */
wire [`MPRJ_IO_PADS-1:0] mgmt_io_out; /* one- and three-pin data out */
wire [`MPRJ_IO_PADS-1:0] mgmt_io_oeb; /* output enable, used only by */
/* three-pin interfaces */
wire [`MPRJ_PWR_PADS-1:0] pwr_ctrl_nc; /* no-connects */
wire clock_core;
@ -291,7 +292,6 @@ module caravan (
.vccd2 (vccd2_core),
.vssd1 (vssd1_core),
.vssd2 (vssd2_core),
.gpio(gpio),
.mprj_io(mprj_io),
.clock(clock),
@ -325,6 +325,7 @@ module caravan (
.flash_io1_do_core(flash_io1_do),
.flash_io0_di_core(flash_io0_di),
.flash_io1_di_core(flash_io1_di),
.mprj_io_one(mprj_io_one),
.mprj_io_in(mprj_io_in),
.mprj_io_in_3v3(mprj_io_in_3v3),
.mprj_io_out(mprj_io_out),
@ -405,15 +406,21 @@ module caravan (
wire mprj_vdd_pwrgood;
wire mprj2_vdd_pwrgood;
`ifdef USE_SRAM_RO_INTERFACE
// SRAM read-noly access from housekeeping
wire hkspi_sram_clk;
wire hkspi_sram_csb;
wire [7:0] hkspi_sram_addr;
wire [31:0] hkspi_sram_data;
`endif
// Management processor (wrapper). Any management core
// implementation must match this pinout.
// Pass thru clock and reset
wire clk_passthru;
wire resetn_passthru;
mgmt_core_wrapper soc (
`ifdef USE_POWER_PINS
.VPWR(vccd_core),
@ -424,6 +431,12 @@ module caravan (
.core_clk(caravel_clk),
.core_rstn(caravel_rstn),
// Pass thru Clock and reset
.clk_in(caravel_clk),
.resetn_in(caravel_rstn),
.clk_out(clk_passthru),
.resetn_out(resetn_passthru),
// GPIO (1 pin)
.gpio_out_pad(gpio_out_core),
.gpio_in_pad(gpio_in_core),
@ -494,11 +507,13 @@ module caravan (
.la_oenb(la_oenb_mprj),
.la_iena(la_iena_mprj),
`ifdef USE_SRAM_RO_INTERFACE
// SRAM Read-only access from housekeeping
.sram_ro_clk(hkspi_sram_clk),
.sram_ro_csb(hkspi_sram_csb),
.sram_ro_addr(hkspi_sram_addr),
.sram_ro_data(hkspi_sram_data),
`endif
// Trap status
.trap(trap)
@ -522,9 +537,9 @@ module caravan (
.vdda2(vdda2_core),
.vssa2(vssa2_core),
`endif
.caravel_clk(caravel_clk),
.caravel_clk(clk_passthru),
.caravel_clk2(caravel_clk2),
.caravel_rstn(caravel_rstn),
.caravel_rstn(resetn_passthru),
.mprj_iena_wb(mprj_iena_wb),
.mprj_cyc_o_core(mprj_cyc_o_core),
.mprj_stb_o_core(mprj_stb_o_core),
@ -761,10 +776,8 @@ module caravan (
.serial_data_2(mprj_io_loader_data_2),
.mgmt_gpio_in(mgmt_io_in),
.mgmt_gpio_out({mgmt_io_out[4:2], mgmt_io_in[`MPRJ_IO_PADS-4:2],
mgmt_io_out[1:0]}),
.mgmt_gpio_oeb({mgmt_io_oeb[4:2], mgmt_io_nc[`MPRJ_IO_PADS-6:0],
mgmt_io_oeb[1:0]}),
.mgmt_gpio_out(mgmt_io_out),
.mgmt_gpio_oeb(mgmt_io_oeb),
.pwr_ctrl_out(pwr_ctrl_nc), /* Not used in this version */
@ -802,10 +815,12 @@ module caravan (
.pad_flash_io0_di(flash_io0_di),
.pad_flash_io1_di(flash_io1_di),
`ifdef USE_SRAM_RO_INTERFACE
.sram_ro_clk(hkspi_sram_clk),
.sram_ro_csb(hkspi_sram_csb),
.sram_ro_addr(hkspi_sram_addr),
.sram_ro_data(hkspi_sram_data),
`endif
.usr1_vcc_pwrgood(mprj_vcc_pwrgood),
.usr2_vcc_pwrgood(mprj2_vcc_pwrgood),
@ -820,22 +835,53 @@ module caravan (
gpio_defaults_block #(
.GPIO_CONFIG_INIT(13'h1803)
) gpio_defaults_block_0 [1:0] (
) gpio_defaults_block_0 (
`ifdef USE_POWER_PINS
.VPWR(vccd_core),
.VGND(vssd_core),
`endif
.gpio_defaults(gpio_defaults[25:0])
.gpio_defaults(gpio_defaults[12:0])
);
gpio_defaults_block #(
.GPIO_CONFIG_INIT(13'h1803)
) gpio_defaults_block_1 (
`ifdef USE_POWER_PINS
.VPWR(vccd_core),
.VGND(vssd_core),
`endif
.gpio_defaults(gpio_defaults[25:13])
);
gpio_defaults_block #(
.GPIO_CONFIG_INIT(13'h0403)
) gpio_defaults_block_2 [2:0] (
) gpio_defaults_block_2 (
`ifdef USE_POWER_PINS
.VPWR(vccd_core),
.VGND(vssd_core),
`endif
.gpio_defaults(gpio_defaults[64:26])
.gpio_defaults(gpio_defaults[38:26])
);
// CSB is configured to be a weak pull-up
gpio_defaults_block #(
.GPIO_CONFIG_INIT(13'h0801)
) gpio_defaults_block_3 (
`ifdef USE_POWER_PINS
.VPWR(vccd_core),
.VGND(vssd_core),
`endif
.gpio_defaults(gpio_defaults[51:39])
);
gpio_defaults_block #(
.GPIO_CONFIG_INIT(13'h0403)
) gpio_defaults_block_4 (
`ifdef USE_POWER_PINS
.VPWR(vccd_core),
.VGND(vssd_core),
`endif
.gpio_defaults(gpio_defaults[64:52])
);
/* Via-programmable defaults for the rest of the GPIO pins */
@ -1099,7 +1145,7 @@ module caravan (
.mgmt_gpio_out(mgmt_io_out[1:0]),
.mgmt_gpio_oeb(mgmt_io_oeb[1:0]),
.one(),
.one(mprj_io_one[1:0]),
.zero(),
// Serial data chain for pad configuration
@ -1127,7 +1173,6 @@ module caravan (
);
/* Section 1 GPIOs (GPIO 0 to 18) */
wire [`MPRJ_IO_PADS_1-`ANALOG_PADS_1-3:0] one_loop1;
/* Section 1 GPIOs (GPIO 2 to 7) that start up under management control */
@ -1152,10 +1197,11 @@ module caravan (
.serial_load_out(gpio_load_1[7:2]),
.mgmt_gpio_in(mgmt_io_in[7:2]),
.mgmt_gpio_out(mgmt_io_in[7:2]),
.mgmt_gpio_oeb(one_loop1[5:0]),
.mgmt_gpio_out(mgmt_io_out[7:2]),
.mgmt_gpio_oeb(mprj_io_one[7:2]),
.one(one_loop1[5:0]),
.one(mprj_io_one[7:2]),
.zero(),
// Serial data chain for pad configuration
@ -1204,10 +1250,10 @@ module caravan (
.serial_load_out(gpio_load_1[(`MPRJ_IO_PADS_1-`ANALOG_PADS_1-1):8]),
.mgmt_gpio_in(mgmt_io_in[`DIG1_TOP:8]),
.mgmt_gpio_out(mgmt_io_in[`DIG1_TOP:8]),
.mgmt_gpio_oeb(one_loop1[`MPRJ_IO_PADS_1-`ANALOG_PADS_1-3:6]),
.one(one_loop1[`MPRJ_IO_PADS_1-`ANALOG_PADS_1-3:6]),
.mgmt_gpio_out(mgmt_io_out[`DIG1_TOP:8]),
.mgmt_gpio_oeb(mprj_io_one[(`MPRJ_IO_PADS_1-`ANALOG_PADS_1-1):8]),
.one(mprj_io_one[(`MPRJ_IO_PADS_1-`ANALOG_PADS_1-1):8]),
.zero(),
// Serial data chain for pad configuration
@ -1257,10 +1303,10 @@ module caravan (
.serial_load_out(gpio_load_2[(`MPRJ_IO_PADS_2-`ANALOG_PADS_2-1):(`MPRJ_IO_PADS_2-`ANALOG_PADS_2-3)]),
.mgmt_gpio_in(mgmt_io_in[(`DIG2_TOP):(`DIG2_TOP-2)]),
.mgmt_gpio_out(mgmt_io_out[4:2]),
.mgmt_gpio_oeb(mgmt_io_oeb[4:2]),
.mgmt_gpio_out(mgmt_io_out[(`DIG2_TOP):(`DIG2_TOP-2)]),
.mgmt_gpio_oeb(mgmt_io_oeb[(`DIG2_TOP):(`DIG2_TOP-2)]),
.one(),
.one(mprj_io_one[(`MPRJ_DIG_PADS-1):(`MPRJ_DIG_PADS-3)]),
.zero(),
// Serial data chain for pad configuration
@ -1288,7 +1334,6 @@ module caravan (
);
/* Section 2 GPIOs (GPIO 19 to 37) */
wire [`MPRJ_IO_PADS_2-`ANALOG_PADS_2-4:0] one_loop2;
gpio_control_block gpio_control_in_2 [`MPRJ_IO_PADS_2-`ANALOG_PADS_2-4:0] (
`ifdef USE_POWER_PINS
@ -1311,10 +1356,10 @@ module caravan (
.serial_load_out(gpio_load_2[(`MPRJ_IO_PADS_2-`ANALOG_PADS_2-4):0]),
.mgmt_gpio_in(mgmt_io_in[(`DIG2_TOP-3):`DIG2_BOT]),
.mgmt_gpio_out(mgmt_io_in[(`DIG2_TOP-3):`DIG2_BOT]),
.mgmt_gpio_oeb(one_loop2),
.mgmt_gpio_out(mgmt_io_out[(`DIG2_TOP-3):`DIG2_BOT]),
.mgmt_gpio_oeb(mprj_io_one[(`MPRJ_IO_PADS_2-`ANALOG_PADS_2-4):0]),
.one(one_loop2),
.one(mprj_io_one[(`MPRJ_IO_PADS_2-`ANALOG_PADS_2-4):0]),
.zero(),
// Serial data chain for pad configuration
@ -1376,17 +1421,22 @@ module caravan (
.X(rstb_l)
);
// Spare logic for metal mask fixes
wire [107:0] spare_xz_nc;
wire [15:0] spare_xi_nc;
wire [3:0] spare_xib_nc;
wire [7:0] spare_xna_nc;
wire [7:0] spare_xno_nc;
wire [7:0] spare_xmx_nc;
wire [7:0] spare_xfq_nc;
wire [7:0] spare_xfqn_nc;
/* Spare logic for metal mask fixes */
// `define NUM_SPARE_BLOCKS (`MPRJ_DIG_PADS+4)
`define NUM_SPARE_BLOCKS 4
spare_logic_block spare_logic [3:0] (
wire [(27*`NUM_SPARE_BLOCKS)-1:0] spare_xz_nc;
wire [(4*`NUM_SPARE_BLOCKS)-1:0] spare_xi_nc;
wire [(1*`NUM_SPARE_BLOCKS)-1:0] spare_xib_nc;
wire [(2*`NUM_SPARE_BLOCKS)-1:0] spare_xna_nc;
wire [(2*`NUM_SPARE_BLOCKS)-1:0] spare_xno_nc;
wire [(2*`NUM_SPARE_BLOCKS)-1:0] spare_xmx_nc;
wire [(2*`NUM_SPARE_BLOCKS)-1:0] spare_xfq_nc;
wire [(2*`NUM_SPARE_BLOCKS)-1:0] spare_xfqn_nc;
// Four spare logic blocks above the processor and one per GPIO
// control block.
spare_logic_block spare_logic [`NUM_SPARE_BLOCKS-1:0] (
`ifdef USE_POWER_PINS
.vccd(vccd_core),
.vssd(vssd_core),

3
verilog/rtl/caravan_netlists.v
View File

@ -58,10 +58,12 @@
`include "gl/mprj2_logic_high.v"
`include "gl/mgmt_protect.v"
`include "gl/mgmt_protect_hv.v"
`include "gl/constant_block.v"
`include "gl/gpio_control_block.v"
`include "gl/gpio_defaults_block.v"
`include "gl/gpio_defaults_block_0403.v"
`include "gl/gpio_defaults_block_1803.v"
`include "gl/gpio_defaults_block_0801.v"
`include "gl/gpio_logic_high.v"
`include "gl/xres_buf.v"
`include "gl/spare_logic_block.v"
@ -83,6 +85,7 @@
`include "mprj2_logic_high.v"
`include "mgmt_protect.v"
`include "mgmt_protect_hv.v"
`include "constant_block.v"
`include "gpio_control_block.v"
`include "gpio_defaults_block.v"
`include "gpio_logic_high.v"

134
verilog/rtl/caravel.v
View File

@ -142,6 +142,7 @@ module caravel (
wire [`MPRJ_IO_PADS*3-1:0] mprj_io_dm;
wire [`MPRJ_IO_PADS-1:0] mprj_io_in;
wire [`MPRJ_IO_PADS-1:0] mprj_io_out;
wire [`MPRJ_IO_PADS-1:0] mprj_io_one;
// User Project Control (user-facing)
wire [`MPRJ_IO_PADS-1:0] user_io_oeb;
@ -173,10 +174,10 @@ module caravel (
// ser_tx = mprj_io[6] (output)
// irq = mprj_io[7] (input)
wire [`MPRJ_IO_PADS-1:0] mgmt_io_in; /* one- and three-pin data */
wire [`MPRJ_IO_PADS-5:0] mgmt_io_nc; /* no-connects */
wire [4:0] mgmt_io_out; /* three-pin interface out */
wire [4:0] mgmt_io_oeb; /* three-pin output enable */
wire [`MPRJ_IO_PADS-1:0] mgmt_io_in; /* one- and three-pin data in */
wire [`MPRJ_IO_PADS-1:0] mgmt_io_out; /* one- and three-pin data out */
wire [`MPRJ_IO_PADS-1:0] mgmt_io_oeb; /* output enable, used only by */
/* the three-pin interfaces */
wire [`MPRJ_PWR_PADS-1:0] pwr_ctrl_nc; /* no-connects */
wire clock_core;
@ -252,7 +253,6 @@ module caravel (
.vccd2 (vccd2_core),
.vssd1 (vssd1_core),
.vssd2 (vssd2_core),
.gpio(gpio),
.mprj_io(mprj_io),
.clock(clock),
@ -286,6 +286,7 @@ module caravel (
.flash_io1_do_core(flash_io1_do),
.flash_io0_di_core(flash_io0_di),
.flash_io1_di_core(flash_io1_di),
.mprj_io_one(mprj_io_one),
.mprj_io_in(mprj_io_in),
.mprj_io_out(mprj_io_out),
.mprj_io_oeb(mprj_io_oeb),
@ -359,15 +360,21 @@ module caravel (
wire mprj_vdd_pwrgood;
wire mprj2_vdd_pwrgood;
`ifdef USE_SRAM_RO_INTERFACE
// SRAM read-only access from houskeeping
wire hkspi_sram_clk;
wire hkspi_sram_csb;
wire [7:0] hkspi_sram_addr;
wire [31:0] hkspi_sram_data;
`endif
// Management processor (wrapper). Any management core
// implementation must match this pinout.
// Pass thru clock and reset
wire clk_passthru;
wire resetn_passthru;
mgmt_core_wrapper soc (
`ifdef USE_POWER_PINS
.VPWR(vccd_core),
@ -378,6 +385,12 @@ module caravel (
.core_clk(caravel_clk),
.core_rstn(caravel_rstn),
// Pass thru Clock and reset
.clk_in(caravel_clk),
.resetn_in(caravel_rstn),
.clk_out(clk_passthru),
.resetn_out(resetn_passthru),
// GPIO (1 pin)
.gpio_out_pad(gpio_out_core),
.gpio_in_pad(gpio_in_core),
@ -448,11 +461,13 @@ module caravel (
.la_oenb(la_oenb_mprj),
.la_iena(la_iena_mprj),
`ifdef USE_SRAM_RO_INTERFACE
// SRAM Read-only access from housekeeping
.sram_ro_clk(hkspi_sram_clk),
.sram_ro_csb(hkspi_sram_csb),
.sram_ro_addr(hkspi_sram_addr),
.sram_ro_data(hkspi_sram_data),
`endif
// Trap status
.trap(trap)
@ -476,9 +491,9 @@ module caravel (
.vdda2(vdda2_core),
.vssa2(vssa2_core),
`endif
.caravel_clk(caravel_clk),
.caravel_clk(clk_passthru),
.caravel_clk2(caravel_clk2),
.caravel_rstn(caravel_rstn),
.caravel_rstn(resetn_passthru),
.mprj_iena_wb(mprj_iena_wb),
.mprj_cyc_o_core(mprj_cyc_o_core),
.mprj_stb_o_core(mprj_stb_o_core),
@ -703,10 +718,8 @@ module caravel (
.serial_data_2(mprj_io_loader_data_2),
.mgmt_gpio_in(mgmt_io_in),
.mgmt_gpio_out({mgmt_io_out[4:2], mgmt_io_in[`MPRJ_IO_PADS-4:2],
mgmt_io_out[1:0]}),
.mgmt_gpio_oeb({mgmt_io_oeb[4:2], mgmt_io_nc[`MPRJ_IO_PADS-6:0],
mgmt_io_oeb[1:0]}),
.mgmt_gpio_out(mgmt_io_out),
.mgmt_gpio_oeb(mgmt_io_oeb),
.pwr_ctrl_out(pwr_ctrl_nc), /* Not used in this version */
@ -744,10 +757,12 @@ module caravel (
.pad_flash_io0_di(flash_io0_di),
.pad_flash_io1_di(flash_io1_di),
`ifdef USE_SRAM_RO_INTERFACE
.sram_ro_clk(hkspi_sram_clk),
.sram_ro_csb(hkspi_sram_csb),
.sram_ro_addr(hkspi_sram_addr),
.sram_ro_data(hkspi_sram_data),
`endif
.usr1_vcc_pwrgood(mprj_vcc_pwrgood),
.usr2_vcc_pwrgood(mprj2_vcc_pwrgood),
@ -762,22 +777,53 @@ module caravel (
gpio_defaults_block #(
.GPIO_CONFIG_INIT(13'h1803)
) gpio_defaults_block_0 [1:0] (
) gpio_defaults_block_0 (
`ifdef USE_POWER_PINS
.VPWR(vccd_core),
.VGND(vssd_core),
`endif
.gpio_defaults(gpio_defaults[25:0])
.gpio_defaults(gpio_defaults[12:0])
);
gpio_defaults_block #(
.GPIO_CONFIG_INIT(13'h1803)
) gpio_defaults_block_1 (
`ifdef USE_POWER_PINS
.VPWR(vccd_core),
.VGND(vssd_core),
`endif
.gpio_defaults(gpio_defaults[25:13])
);
gpio_defaults_block #(
.GPIO_CONFIG_INIT(13'h0403)
) gpio_defaults_block_2 [2:0] (
) gpio_defaults_block_2 (
`ifdef USE_POWER_PINS
.VPWR(vccd_core),
.VGND(vssd_core),
`endif
.gpio_defaults(gpio_defaults[64:26])
.gpio_defaults(gpio_defaults[38:26])
);
// CSB pin is set as an internal pull-up
gpio_defaults_block #(
.GPIO_CONFIG_INIT(13'h0801)
) gpio_defaults_block_3 (
`ifdef USE_POWER_PINS
.VPWR(vccd_core),
.VGND(vssd_core),
`endif
.gpio_defaults(gpio_defaults[51:39])
);
gpio_defaults_block #(
.GPIO_CONFIG_INIT(13'h0403)
) gpio_defaults_block_4 (
`ifdef USE_POWER_PINS
.VPWR(vccd_core),
.VGND(vssd_core),
`endif
.gpio_defaults(gpio_defaults[64:52])
);
/* Via-programmable defaults for the rest of the GPIO pins */
@ -1152,7 +1198,7 @@ module caravel (
.mgmt_gpio_out(mgmt_io_out[1:0]),
.mgmt_gpio_oeb(mgmt_io_oeb[1:0]),
.one(),
.one(mprj_io_one[1:0]),
.zero(),
// Serial data chain for pad configuration
@ -1179,9 +1225,6 @@ module caravel (
.pad_gpio_in(mprj_io_in[1:0])
);
/* Section 1 GPIOs (GPIO 0 to 18) */
wire [`MPRJ_IO_PADS_1-1:2] one_loop1;
/* Section 1 GPIOs (GPIO 2 to 7) that start up under management control */
gpio_control_block gpio_control_in_1a [5:0] (
@ -1205,10 +1248,10 @@ module caravel (
.serial_load_out(gpio_load_1[7:2]),
.mgmt_gpio_in(mgmt_io_in[7:2]),
.mgmt_gpio_out(mgmt_io_in[7:2]),
.mgmt_gpio_oeb(one_loop1[7:2]),
.mgmt_gpio_out(mgmt_io_out[7:2]),
.mgmt_gpio_oeb(mprj_io_one[7:2]),
.one(one_loop1[7:2]),
.one(mprj_io_one[7:2]),
.zero(),
// Serial data chain for pad configuration
@ -1258,10 +1301,10 @@ module caravel (
.serial_load_out(gpio_load_1[(`MPRJ_IO_PADS_1-1):8]),
.mgmt_gpio_in(mgmt_io_in[(`MPRJ_IO_PADS_1-1):8]),
.mgmt_gpio_out(mgmt_io_in[(`MPRJ_IO_PADS_1-1):8]),
.mgmt_gpio_oeb(one_loop1[(`MPRJ_IO_PADS_1-1):8]),
.one(one_loop1[(`MPRJ_IO_PADS_1-1):8]),
.mgmt_gpio_out(mgmt_io_out[(`MPRJ_IO_PADS_1-1):8]),
.mgmt_gpio_oeb(mprj_io_one[(`MPRJ_IO_PADS_1-1):8]),
.one(mprj_io_one[(`MPRJ_IO_PADS_1-1):8]),
.zero(),
// Serial data chain for pad configuration
@ -1311,10 +1354,10 @@ module caravel (
.serial_load_out(gpio_load_2[(`MPRJ_IO_PADS_2-1):(`MPRJ_IO_PADS_2-3)]),
.mgmt_gpio_in(mgmt_io_in[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
.mgmt_gpio_out(mgmt_io_out[4:2]),
.mgmt_gpio_oeb(mgmt_io_oeb[4:2]),
.mgmt_gpio_out(mgmt_io_out[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
.mgmt_gpio_oeb(mgmt_io_oeb[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
.one(),
.one(mprj_io_one[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
.zero(),
// Serial data chain for pad configuration
@ -1342,7 +1385,6 @@ module caravel (
);
/* Section 2 GPIOs (GPIO 19 to 34) */
wire [`MPRJ_IO_PADS_2-4:0] one_loop2;
gpio_control_block gpio_control_in_2 [`MPRJ_IO_PADS_2-4:0] (
`ifdef USE_POWER_PINS
@ -1365,10 +1407,11 @@ module caravel (
.serial_load_out(gpio_load_2[(`MPRJ_IO_PADS_2-4):0]),
.mgmt_gpio_in(mgmt_io_in[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
.mgmt_gpio_out(mgmt_io_in[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
.mgmt_gpio_oeb(one_loop2),
.mgmt_gpio_out(mgmt_io_out[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
.mgmt_gpio_oeb(mprj_io_one[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
.one(one_loop2),
.one(mprj_io_one[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
.zero(),
// Serial data chain for pad configuration
@ -1430,17 +1473,22 @@ module caravel (
.X(rstb_l)
);
// Spare logic for metal mask fixes
wire [107:0] spare_xz_nc;
wire [15:0] spare_xi_nc;
wire [3:0] spare_xib_nc;
wire [7:0] spare_xna_nc;
wire [7:0] spare_xno_nc;
wire [7:0] spare_xmx_nc;
wire [7:0] spare_xfq_nc;
wire [7:0] spare_xfqn_nc;
/* Spare logic for metal mask fixes */
// `define NUM_SPARE_BLOCKS (`MPRJ_IO_PADS+4)
`define NUM_SPARE_BLOCKS 4
spare_logic_block spare_logic [3:0] (
wire [(27*`NUM_SPARE_BLOCKS)-1:0] spare_xz_nc;
wire [(4*`NUM_SPARE_BLOCKS)-1:0] spare_xi_nc;
wire [(1*`NUM_SPARE_BLOCKS)-1:0] spare_xib_nc;
wire [(2*`NUM_SPARE_BLOCKS)-1:0] spare_xna_nc;
wire [(2*`NUM_SPARE_BLOCKS)-1:0] spare_xno_nc;
wire [(2*`NUM_SPARE_BLOCKS)-1:0] spare_xmx_nc;
wire [(2*`NUM_SPARE_BLOCKS)-1:0] spare_xfq_nc;
wire [(2*`NUM_SPARE_BLOCKS)-1:0] spare_xfqn_nc;
// Four spare logic blocks above the processor and one per GPIO
// control block.
spare_logic_block spare_logic [`NUM_SPARE_BLOCKS-1:0] (
`ifdef USE_POWER_PINS
.vccd(vccd_core),
.vssd(vssd_core),

3
verilog/rtl/caravel_netlists.v
View File

@ -56,10 +56,12 @@
`include "gl/mprj2_logic_high.v"
`include "gl/mgmt_protect.v"
`include "gl/mgmt_protect_hv.v"
`include "gl/constant_block.v"
`include "gl/gpio_control_block.v"
`include "gl/gpio_defaults_block.v"
`include "gl/gpio_defaults_block_0403.v"
`include "gl/gpio_defaults_block_1803.v"
`include "gl/gpio_defaults_block_0801.v"
`include "gl/gpio_logic_high.v"
`include "gl/xres_buf.v"
`include "gl/spare_logic_block.v"
@ -81,6 +83,7 @@
`include "mprj2_logic_high.v"
`include "mgmt_protect.v"
`include "mgmt_protect_hv.v"
`include "constant_block.v"
`include "gpio_control_block.v"
`include "gpio_defaults_block.v"
`include "gpio_logic_high.v"

42
verilog/rtl/chip_io.v
View File

@ -97,6 +97,8 @@ module chip_io(
input [`MPRJ_IO_PADS-1:0] mprj_io_analog_pol,
input [`MPRJ_IO_PADS*3-1:0] mprj_io_dm,
output [`MPRJ_IO_PADS-1:0] mprj_io_in,
// Loopbacks to constant value 1 in the 1.8V domain
input [`MPRJ_IO_PADS-1:0] mprj_io_one,
// User project direct access to gpio pad connections for analog
// (all but the lowest-numbered 7 pads)
inout [`MPRJ_IO_PADS-10:0] mprj_analog_io
@ -273,19 +275,29 @@ module chip_io(
wire[2:0] flash_io1_mode =
{flash_io1_ieb_core, flash_io1_ieb_core, flash_io1_oeb_core};
wire [6:0] vccd_const_one; // Constant value for management pins
wire [6:0] vssd_const_zero; // Constant value for management pins
constant_block constant_value_inst [6:0] (
.vccd(vccd),
.vssd(vssd),
.one(vccd_const_one),
.zero(vssd_const_zero)
);
// Management clock input pad
`INPUT_PAD(clock, clock_core);
`INPUT_PAD(clock, clock_core, vccd_const_one[0], vssd_const_zero[0]);
// Management GPIO pad
`INOUT_PAD(gpio, gpio_in_core, gpio_out_core, gpio_inenb_core, gpio_outenb_core, dm_all);
`INOUT_PAD(gpio, gpio_in_core, vccd_const_one[1], vssd_const_zero[1], gpio_out_core, gpio_inenb_core, gpio_outenb_core, dm_all);
// Management Flash SPI pads
`INOUT_PAD(flash_io0, flash_io0_di_core, flash_io0_do_core, flash_io0_ieb_core, flash_io0_oeb_core, flash_io0_mode);
`INOUT_PAD(flash_io0, flash_io0_di_core, vccd_const_one[2], vssd_const_zero[2], flash_io0_do_core, flash_io0_ieb_core, flash_io0_oeb_core, flash_io0_mode);
`INOUT_PAD(flash_io1, flash_io1_di_core, flash_io1_do_core, flash_io1_ieb_core, flash_io1_oeb_core, flash_io1_mode);
`INOUT_PAD(flash_io1, flash_io1_di_core, vccd_const_one[3], vssd_const_zero[3], flash_io1_do_core, flash_io1_ieb_core, flash_io1_oeb_core, flash_io1_mode);
`OUTPUT_NO_INP_DIS_PAD(flash_csb, flash_csb_core, flash_csb_oeb_core);
`OUTPUT_NO_INP_DIS_PAD(flash_clk, flash_clk_core, flash_clk_oeb_core);
`OUTPUT_NO_INP_DIS_PAD(flash_csb, flash_csb_core, vccd_const_one[4], vssd_const_zero[4], flash_csb_oeb_core);
`OUTPUT_NO_INP_DIS_PAD(flash_clk, flash_clk_core, vccd_const_one[5], vssd_const_zero[5], flash_clk_oeb_core);
// NOTE: The analog_out pad from the raven chip has been replaced by
// the digital reset input resetb on caravel due to the lack of an on-board
@ -293,6 +305,7 @@ module chip_io(
// free reset.
wire xresloop;
wire xres_vss_loop;
sky130_fd_io__top_xres4v2 resetb_pad (
`MGMT_ABUTMENT_PINS
`ifndef TOP_ROUTING
@ -300,16 +313,16 @@ module chip_io(
`endif
.TIE_WEAK_HI_H(xresloop), // Loop-back connection to pad through pad_a_esd_h
.TIE_HI_ESD(),
.TIE_LO_ESD(),
.TIE_LO_ESD(xres_vss_loop),
.PAD_A_ESD_H(xresloop),
.XRES_H_N(resetb_core_h),
.DISABLE_PULLUP_H(vssio), // 0 = enable pull-up on reset pad
.ENABLE_H(porb_h), // Power-on-reset
.EN_VDDIO_SIG_H(vssio), // No idea.
.INP_SEL_H(vssio), // 1 = use filt_in_h else filter the pad input
.FILT_IN_H(vssio), // Alternate input for glitch filter
.PULLUP_H(vssio), // Pullup connection for alternate filter input
.ENABLE_VDDIO(vccd)
.DISABLE_PULLUP_H(xres_vss_loop), // 0 = enable pull-up on reset pad
.ENABLE_H(porb_h), // Power-on-reset
.EN_VDDIO_SIG_H(xres_vss_loop), // No idea.
.INP_SEL_H(xres_vss_loop), // 1 = use filt_in_h else filter the pad input
.FILT_IN_H(xres_vss_loop), // Alternate input for glitch filter
.PULLUP_H(xres_vss_loop), // Pullup connection for alternate filter input
.ENABLE_VDDIO(vccd_const_one[6])
);
// Corner cells (These are overlay cells; it is not clear what is normally
@ -378,6 +391,7 @@ module chip_io(
.analog_a(analog_a),
.analog_b(analog_b),
.porb_h(porb_h),
.vccd_conb(mprj_io_one),
.io(mprj_io),
.io_out(mprj_io_out),
.oeb(mprj_io_oeb),

41
verilog/rtl/chip_io_alt.v
View File

@ -116,6 +116,7 @@ module chip_io_alt #(
input [(`MPRJ_IO_PADS-ANALOG_PADS_1-ANALOG_PADS_2)*3-1:0] mprj_io_dm,
output [`MPRJ_IO_PADS-ANALOG_PADS_1-ANALOG_PADS_2-1:0] mprj_io_in,
output [`MPRJ_IO_PADS-ANALOG_PADS_1-ANALOG_PADS_2-1:0] mprj_io_in_3v3,
input [`MPRJ_IO_PADS-ANALOG_PADS_1-ANALOG_PADS_2-1:0] mprj_io_one,
// User project direct access to gpio pad connections for analog
// "analog" connects to the "esd_0" pin of the GPIO pad, and
@ -343,18 +344,28 @@ module chip_io_alt #(
wire[2:0] flash_io1_mode =
{flash_io1_ieb_core, flash_io1_ieb_core, flash_io1_oeb_core};
wire [6:0] vccd_const_one; // Constant value for management pins
wire [6:0] vssd_const_zero; // Constant value for management pins
constant_block constant_value_inst [6:0] (
.vccd(vccd),
.vssd(vssd),
.one(vccd_const_one),
.zero(vssd_const_zero)
);
// Management clock input pad
`INPUT_PAD(clock, clock_core);
`INPUT_PAD(clock, clock_core, vccd_const_one[0], vssd_const_zero[0]);
// Management GPIO pad
`INOUT_PAD(gpio, gpio_in_core, gpio_out_core, gpio_inenb_core, gpio_outenb_core, dm_all);
`INOUT_PAD(gpio, gpio_in_core, vccd_const_one[1], vssd_const_zero[1], gpio_out_core, gpio_inenb_core, gpio_outenb_core, dm_all);
// Management Flash SPI pads
`INOUT_PAD(flash_io0, flash_io0_di_core, flash_io0_do_core, flash_io0_ieb_core, flash_io0_oeb_core, flash_io0_mode);
`INOUT_PAD(flash_io1, flash_io1_di_core, flash_io1_do_core, flash_io1_ieb_core, flash_io1_oeb_core, flash_io1_mode);
`INOUT_PAD(flash_io0, flash_io0_di_core, vccd_const_one[2], vssd_const_zero[2], flash_io0_do_core, flash_io0_ieb_core, flash_io0_oeb_core, flash_io0_mode);
`INOUT_PAD(flash_io1, flash_io1_di_core, vccd_const_one[3], vssd_const_zero[3], flash_io1_do_core, flash_io1_ieb_core, flash_io1_oeb_core, flash_io1_mode);
`OUTPUT_NO_INP_DIS_PAD(flash_csb, flash_csb_core, flash_csb_oeb_core);
`OUTPUT_NO_INP_DIS_PAD(flash_clk, flash_clk_core, flash_clk_oeb_core);
`OUTPUT_NO_INP_DIS_PAD(flash_csb, flash_csb_core, vccd_const_one[4], vssd_const_zero[4], flash_csb_oeb_core);
`OUTPUT_NO_INP_DIS_PAD(flash_clk, flash_clk_core, vccd_const_one[5], vssd_const_zero[5], flash_clk_oeb_core);
// NOTE: The analog_out pad from the raven chip has been replaced by
// the digital reset input resetb on caravel due to the lack of an on-board
@ -362,6 +373,7 @@ module chip_io_alt #(
// free reset.
wire xresloop;
wire xres_zero_loop
sky130_fd_io__top_xres4v2 resetb_pad (
`MGMT_ABUTMENT_PINS
`ifndef TOP_ROUTING
@ -369,16 +381,16 @@ module chip_io_alt #(
`endif
.TIE_WEAK_HI_H(xresloop), // Loop-back connection to pad through pad_a_esd_h
.TIE_HI_ESD(),
.TIE_LO_ESD(),
.TIE_LO_ESD(xres_zero_loop),
.PAD_A_ESD_H(xresloop),
.XRES_H_N(resetb_core_h),
.DISABLE_PULLUP_H(vssio), // 0 = enable pull-up on reset pad
.ENABLE_H(porb_h), // Power-on-reset
.EN_VDDIO_SIG_H(vssio), // No idea.
.INP_SEL_H(vssio), // 1 = use filt_in_h else filter the pad input
.FILT_IN_H(vssio), // Alternate input for glitch filter
.PULLUP_H(vssio), // Pullup connection for alternate filter input
.ENABLE_VDDIO(vccd)
.DISABLE_PULLUP_H(xres_zero_loop), // 0 = enable pull-up on reset pad
.ENABLE_H(porb_h), // Power-on-reset
.EN_VDDIO_SIG_H(xres_zero_loop), // No idea.
.INP_SEL_H(xres_zero_loop), // 1 = use filt_in_h else filter the pad input
.FILT_IN_H(xres_zero_loop), // Alternate input for glitch filter
.PULLUP_H(xres_zero_loop), // Pullup connection for alternate filter input
.ENABLE_VDDIO(vccd_const_one[6])
);
// Corner cells (These are overlay cells; it is not clear what is normally
@ -451,6 +463,7 @@ module chip_io_alt #(
.analog_a(analog_a),
.analog_b(analog_b),
.porb_h(porb_h),
.vccd_conb(mprj_io_one),
.io({mprj_io[`MPRJ_IO_PADS-1:`MPRJ_IO_PADS_1+ANALOG_PADS_2],
mprj_io[`MPRJ_IO_PADS_1-ANALOG_PADS_1-1:0]}),

77
verilog/rtl/constant_block.v Normal file
View File

@ -0,0 +1,77 @@
// SPDX-FileCopyrightText: 2020 Efabless Corporation
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
// SPDX-License-Identifier: Apache-2.0
`default_nettype none
/*
*---------------------------------------------------------------------
* A simple module that generates buffered high and low outputs
* in the 1.8V domain.
*---------------------------------------------------------------------
*/
module constant_block (
`ifdef USE_POWER_PINS
inout vccd,
inout vssd,
`endif
output one,
output zero
);
wire one_unbuf;
wire zero_unbuf;
sky130_fd_sc_hd__conb_1 const_source (
`ifdef USE_POWER_PINS
.VPWR(vccd),
.VGND(vssd),
.VPB(vccd),
.VNB(vssd),
`endif
.HI(one_unbuf),
.LO(zero_unbuf)
);
/* Buffer the constant outputs (could be synthesized) */
/* NOTE: Constant cell HI, LO outputs are connected to power */
/* rails through an approximately 120 ohm resistor, which is not */
/* enough to drive inputs in the I/O cells while ensuring ESD */
/* requirements, without buffering. */
sky130_fd_sc_hd__buf_16 const_one_buf (
`ifdef USE_POWER_PINS
.VPWR(vccd),
.VGND(vssd),
.VPB(vccd),
.VNB(vssd),
`endif
.A(one_unbuf),
.X(one)
);
sky130_fd_sc_hd__buf_16 const_zero_buf (
`ifdef USE_POWER_PINS
.VPWR(vccd),
.VGND(vssd),
.VPB(vccd),
.VNB(vssd),
`endif
.A(zero_unbuf),
.X(zero)
);
endmodule
`default_nettype wire

43
verilog/rtl/gpio_control_block.v
View File

@ -44,6 +44,9 @@
* so that the serial data bit out from the module only changes on
* the clock half cycle. This avoids the need to fine-tune the clock
* skew between GPIO blocks.
*
* Modified 10/05/2022 by Tim Edwards
*
*---------------------------------------------------------------------
*/
@ -140,11 +143,12 @@ module gpio_control_block #(
wire pad_gpio_outenb;
wire pad_gpio_out;
wire pad_gpio_in;
wire one_unbuf;
wire zero_unbuf;
wire one;
wire zero;
wire user_gpio_in;
wire gpio_in_unbuf;
wire gpio_logic1;
reg serial_data_out;
@ -223,11 +227,21 @@ module gpio_control_block #(
/* Implement pad control behavior depending on state of mgmt_ena */
assign gpio_in_unbuf = pad_gpio_in;
assign mgmt_gpio_in = (gpio_inenb == 1'b0 && gpio_outenb == 1'b1) ?
pad_gpio_in : 1'bz;
/* The pad value always goes back to the housekeeping module */
assign mgmt_gpio_in = pad_gpio_in;
/* For 2-wire interfaces, the mgmt_gpio_oeb line is tied high at */
/* the control block. In this case, the output enable state is */
/* determined by the OEB configuration bit. */
assign pad_gpio_outenb = (mgmt_ena) ? ((mgmt_gpio_oeb == 1'b1) ?
gpio_outenb : 1'b0) : user_gpio_oeb;
/* For 2-wire interfaces, if the pad is configured for pull-up or */
/* pull-down, drive the output value locally to achieve the */
/* expected pull. */
assign pad_gpio_out = (mgmt_ena) ? ((mgmt_gpio_oeb == 1'b1) ?
((gpio_dm[2:1] == 2'b01) ? ~gpio_dm[0] : mgmt_gpio_out) :
mgmt_gpio_out) : user_gpio_out;
@ -242,17 +256,9 @@ module gpio_control_block #(
.gpio_logic1(gpio_logic1)
);
sky130_fd_sc_hd__einvp_8 gpio_in_buf (
`ifdef USE_POWER_PINS
.VPWR(vccd),
.VGND(vssd),
.VPB(vccd),
.VNB(vssd),
`endif
.Z(user_gpio_in),
.A(~gpio_in_unbuf),
.TE(gpio_logic1)
);
/* If user project area is powered down, zero the pad input value */
/* going to the user project. */
assign user_gpio_in = pad_gpio_in & gpio_logic1;
sky130_fd_sc_hd__conb_1 const_source (
`ifdef USE_POWER_PINS
@ -261,9 +267,12 @@ module gpio_control_block #(
.VPB(vccd),
.VNB(vssd),
`endif
.HI(one),
.LO(zero)
.HI(one_unbuf),
.LO(zero_unbuf)
);
assign zero = zero_unbuf;
assign one = one_unbuf;
endmodule
`default_nettype wire

91
verilog/rtl/housekeeping.v
View File

@ -170,10 +170,12 @@ module housekeeping #(
input pad_flash_io0_di,
input pad_flash_io1_di,
`ifdef USE_SRAM_RO_INTERFACE
output sram_ro_clk,
output sram_ro_csb,
output [7:0] sram_ro_addr,
input [31:0] sram_ro_data,
`endif
// System signal monitoring
input usr1_vcc_pwrgood,
@ -203,9 +205,11 @@ module housekeeping #(
reg serial_xfer;
reg hkspi_disable;
`ifdef USE_SRAM_RO_INTERFACE
reg sram_ro_clk;
reg sram_ro_csb;
reg [7:0] sram_ro_addr;
`endif
reg clk1_output_dest;
reg clk2_output_dest;
@ -250,10 +254,12 @@ module housekeeping #(
wire cwstb; // Combination of SPI write strobe and back door write strobe
wire csclk; // Combination of SPI SCK and back door access trigger
`ifdef USE_SRAM_RO_INTERFACE
wire [31:0] sram_ro_data;
`endif
// Housekeeping side 3-wire interface to GPIOs (see below)
wire [`MPRJ_IO_PADS-1:0] mgmt_gpio_out_pre;
wire [`MPRJ_IO_PADS-1:0] mgmt_gpio_out;
// Pass-through mode handling. Signals may only be applied when the
// core processor is in reset.
@ -264,26 +270,6 @@ module housekeeping #(
wire wb_rst_i;
assign wb_rst_i = ~wb_rstn_i;
// Handle the management-side control of the GPIO pins. All but the
// first and last three GPIOs (0, 1 and 35 to 37) are one-pin interfaces with
// a single I/O pin whose direction is determined by the local OEB signal.
// The other five are straight-through connections of the 3-wire interface.
assign mgmt_gpio_out[`MPRJ_IO_PADS-1:`MPRJ_IO_PADS-3] =
mgmt_gpio_out_pre[`MPRJ_IO_PADS-1:`MPRJ_IO_PADS-3];
assign mgmt_gpio_out[1:0] = mgmt_gpio_out_pre[1:0];
genvar i;
// This implements high-impedence buffers on the GPIO outputs other than
// the first and last two GPIOs so that these pins can be tied together
// at the top level to create the single-wire interface on those GPIOs.
generate
for (i = 2; i < `MPRJ_IO_PADS-3; i = i + 1) begin
assign mgmt_gpio_out[i] = mgmt_gpio_oeb[i] ? 1'bz : mgmt_gpio_out_pre[i];
end
endgenerate
// Pass-through mode. Housekeeping SPI signals get inserted
// between the management SoC and the flash SPI I/O.
@ -384,13 +370,15 @@ module housekeeping #(
serial_bb_load, serial_bb_resetn, serial_bb_enable,
serial_busy};
/* To be added: SRAM read-only port (registers 14 to 19) */
`ifdef USE_SRAM_RO_INTERFACE
/* Optional: SRAM read-only port (registers 14 to 19) */
8'h14 : fdata = {6'b000000, sram_ro_clk, sram_ro_csb};
8'h15 : fdata = sram_ro_addr;
8'h16 : fdata = sram_ro_data[31:24];
8'h17 : fdata = sram_ro_data[23:16];
8'h18 : fdata = sram_ro_data[15:8];
8'h19 : fdata = sram_ro_data[7:0];
`endif
/* System monitoring */
8'h1a : fdata = {4'b0000, usr1_vcc_pwrgood, usr2_vcc_pwrgood,
@ -537,8 +525,6 @@ module housekeeping #(
gpio_adr | 12'h000 : spiaddr = 8'h13; // GPIO control
/* To be added: SRAM read-only interface */
sys_adr | 12'h000 : spiaddr = 8'h1a; // Power monitor
sys_adr | 12'h004 : spiaddr = 8'h1b; // Output redirect
sys_adr | 12'h00c : spiaddr = 8'h1c; // Input redirect
@ -750,7 +736,7 @@ module housekeeping #(
.reset(~porb),
.SCK(mgmt_gpio_in[4]),
.SDI(mgmt_gpio_in[2]),
.CSB((spi_is_active) ? mgmt_gpio_in[3] : 1'b1),
.CSB((spi_is_enabled) ? mgmt_gpio_in[3] : 1'b1),
.SDO(sdo),
.sdoenb(sdo_enb),
.idata(odata),
@ -777,9 +763,9 @@ module housekeeping #(
// GPIO data handling to and from the management SoC
assign mgmt_gpio_out_pre[37] = (qspi_enabled) ? spimemio_flash_io3_do :
assign mgmt_gpio_out[37] = (qspi_enabled) ? spimemio_flash_io3_do :
mgmt_gpio_data[37];
assign mgmt_gpio_out_pre[36] = (qspi_enabled) ? spimemio_flash_io2_do :
assign mgmt_gpio_out[36] = (qspi_enabled) ? spimemio_flash_io2_do :
mgmt_gpio_data[36];
assign mgmt_gpio_oeb[37] = (qspi_enabled) ? spimemio_flash_io3_oeb :
@ -795,40 +781,42 @@ module housekeeping #(
assign spimemio_flash_io2_di = mgmt_gpio_in[36];
// SPI master is assigned to the other 4 bits of the data high word.
assign mgmt_gpio_out_pre[32] = (spi_enabled) ? spi_sck : mgmt_gpio_data[32];
assign mgmt_gpio_out_pre[33] = (spi_enabled) ? spi_csb : mgmt_gpio_data[33];
assign mgmt_gpio_out_pre[34] = mgmt_gpio_data[34];
assign mgmt_gpio_out_pre[35] = (spi_enabled) ? spi_sdo : mgmt_gpio_data[35];
assign mgmt_gpio_out[32] = (spi_enabled) ? spi_sck : mgmt_gpio_data[32];
assign mgmt_gpio_out[33] = (spi_enabled) ? spi_csb : mgmt_gpio_data[33];
assign mgmt_gpio_out[34] = mgmt_gpio_data[34];
assign mgmt_gpio_out[35] = (spi_enabled) ? spi_sdo : mgmt_gpio_data[35];
assign mgmt_gpio_out_pre[31:16] = mgmt_gpio_data[31:16];
assign mgmt_gpio_out_pre[12:11] = mgmt_gpio_data[12:11];
assign mgmt_gpio_out[31:16] = mgmt_gpio_data[31:16];
assign mgmt_gpio_out[12:11] = mgmt_gpio_data[12:11];
assign mgmt_gpio_out_pre[10] = (pass_thru_user_delay) ? mgmt_gpio_in[2]
assign mgmt_gpio_out[10] = (pass_thru_user_delay) ? mgmt_gpio_in[2]
: mgmt_gpio_data[10];
assign mgmt_gpio_out_pre[9] = (pass_thru_user) ? mgmt_gpio_in[4]
assign mgmt_gpio_out[9] = (pass_thru_user) ? mgmt_gpio_in[4]
: mgmt_gpio_data[9];
assign mgmt_gpio_out_pre[8] = (pass_thru_user_delay) ? mgmt_gpio_in[3]
assign mgmt_gpio_out[8] = (pass_thru_user_delay) ? mgmt_gpio_in[3]
: mgmt_gpio_data[8];
assign mgmt_gpio_out_pre[7] = mgmt_gpio_data[7];
assign mgmt_gpio_out_pre[6] = (uart_enabled) ? ser_tx : mgmt_gpio_data[6];
assign mgmt_gpio_out_pre[5:2] = mgmt_gpio_data[5:2];
assign mgmt_gpio_out[7] = mgmt_gpio_data[7];
assign mgmt_gpio_out[6] = (uart_enabled) ? ser_tx : mgmt_gpio_data[6];
assign mgmt_gpio_out[5:2] = mgmt_gpio_data[5:2];
// In pass-through modes, route SDO from the respective flash (user or
// management SoC) to the dedicated SDO pin (GPIO[1])
assign mgmt_gpio_out_pre[1] = (pass_thru_mgmt) ? pad_flash_io1_di :
assign mgmt_gpio_out[1] = (pass_thru_mgmt) ? pad_flash_io1_di :
(pass_thru_user) ? mgmt_gpio_in[11] :
(spi_is_active) ? sdo : mgmt_gpio_data[1];
assign mgmt_gpio_out_pre[0] = (debug_mode) ? debug_out : mgmt_gpio_data[0];
assign mgmt_gpio_out[0] = (debug_mode) ? debug_out : mgmt_gpio_data[0];
assign mgmt_gpio_oeb[1] = (spi_is_active) ? sdo_enb : ~gpio_configure[0][INP_DIS];
assign mgmt_gpio_oeb[1] = (spi_is_active) ? sdo_enb : ~gpio_configure[1][INP_DIS];
assign mgmt_gpio_oeb[0] = (debug_mode) ? debug_oeb : ~gpio_configure[0][INP_DIS];
assign ser_rx = (uart_enabled) ? mgmt_gpio_in[5] : 1'b0;
assign spi_sdi = (spi_enabled) ? mgmt_gpio_in[34] : 1'b0;
assign debug_in = (debug_mode) ? mgmt_gpio_in[0] : 1'b0;
genvar i;
/* These are disconnected, but apply a meaningful signal anyway */
generate
for (i = 2; i < `MPRJ_IO_PADS-3; i = i + 1) begin
@ -843,11 +831,11 @@ module housekeeping #(
// so the pad being under control of the user area takes precedence
// over the system monitoring function.
assign mgmt_gpio_out_pre[15] = (clk2_output_dest == 1'b1) ? user_clock
assign mgmt_gpio_out[15] = (clk2_output_dest == 1'b1) ? user_clock
: mgmt_gpio_data[15];
assign mgmt_gpio_out_pre[14] = (clk1_output_dest == 1'b1) ? wb_clk_i
assign mgmt_gpio_out[14] = (clk1_output_dest == 1'b1) ? wb_clk_i
: mgmt_gpio_data[14];
assign mgmt_gpio_out_pre[13] = (trap_output_dest == 1'b1) ? trap
assign mgmt_gpio_out[13] = (trap_output_dest == 1'b1) ? trap
: mgmt_gpio_data[13];
assign irq[0] = irq_spi;
@ -1039,7 +1027,12 @@ module housekeeping #(
if ((j < 2) || (j >= `MPRJ_IO_PADS - 2)) begin
gpio_configure[j] <= 'h1803;
end else begin
gpio_configure[j] <= 'h0403;
if (j == 3) begin
// j == 3 corresponds to CSB, which is a weak pull-up
gpio_configure[j] <= 'h0801;
end else begin
gpio_configure[j] <= 'h0403;
end
end
end
@ -1055,9 +1048,11 @@ module housekeeping #(
hkspi_disable <= 1'b0;
pwr_ctrl_out <= 'd0;
`ifdef USE_SRAM_RO_INTERFACE
sram_ro_clk <= 1'b0;
sram_ro_csb <= 1'b1;
sram_ro_addr <= 8'h00;
`endif
end else begin
if (cwstb == 1'b1) begin
@ -1109,7 +1104,8 @@ module housekeeping #(
serial_xfer <= cdata[0];
end
/* To be done: Add SRAM read-only interface */
`ifdef USE_SRAM_RO_INTERFACE
/* Optional: Add SRAM read-only interface */
8'h14: begin
sram_ro_clk <= cdata[1];
sram_ro_csb <= cdata[0];
@ -1117,6 +1113,7 @@ module housekeeping #(
8'h15: begin
sram_ro_addr <= cdata;
end
`endif
/* Registers 16 to 19 (SRAM data) are read-only */

9
verilog/rtl/mprj_io.v
View File

@ -44,6 +44,7 @@ module mprj_io #(
input analog_a,
input analog_b,
input porb_h,
input [TOTAL_PADS-1:0] vccd_conb,
inout [TOTAL_PADS-1:0] io,
input [TOTAL_PADS-1:0] io_out,
input [TOTAL_PADS-1:0] oeb,
@ -79,8 +80,8 @@ module mprj_io #(
.ENABLE_H(enh[AREA1PADS - 1:0]),
.ENABLE_INP_H(loop1_io[AREA1PADS - 1:0]),
.ENABLE_VDDA_H(porb_h),
.ENABLE_VSWITCH_H(vssio),
.ENABLE_VDDIO(vccd),
.ENABLE_VSWITCH_H(loop1_io[AREA1PADS - 1:0]),
.ENABLE_VDDIO(vccd_conb[AREA1PADS - 1:0]),
.INP_DIS(inp_dis[AREA1PADS - 1:0]),
.IB_MODE_SEL(ib_mode_sel[AREA1PADS - 1:0]),
.VTRIP_SEL(vtrip_sel[AREA1PADS - 1:0]),
@ -110,8 +111,8 @@ module mprj_io #(
.ENABLE_H(enh[TOTAL_PADS - 1:AREA1PADS]),
.ENABLE_INP_H(loop1_io[TOTAL_PADS - 1:AREA1PADS]),
.ENABLE_VDDA_H(porb_h),
.ENABLE_VSWITCH_H(vssio),
.ENABLE_VDDIO(vccd),
.ENABLE_VSWITCH_H(loop1_io[TOTAL_PADS - 1:AREA1PADS]),
.ENABLE_VDDIO(vccd_conb[TOTAL_PADS - 1:AREA1PADS]),
.INP_DIS(inp_dis[TOTAL_PADS - 1:AREA1PADS]),
.IB_MODE_SEL(ib_mode_sel[TOTAL_PADS - 1:AREA1PADS]),
.VTRIP_SEL(vtrip_sel[TOTAL_PADS - 1:AREA1PADS]),

136
verilog/rtl/pads.v
View File

@ -73,40 +73,42 @@
.SRC_BDY_LVC1(L1), \
.SRC_BDY_LVC2(L2)
`define INPUT_PAD(X,Y) \
wire loop_``X; \
`define INPUT_PAD(X,Y,CONB_ONE,CONB_ZERO) \
wire loop_zero_``X; \
wire loop_one_``X; \
sky130_ef_io__gpiov2_pad_wrapped X``_pad ( \
`MGMT_ABUTMENT_PINS \
`ifndef TOP_ROUTING \
.PAD(X), \
`endif \
.OUT(vssd), \
.OE_N(vccd), \
.HLD_H_N(vddio), \
.OUT(CONB_ZERO), \
.OE_N(CONB_ONE), \
.HLD_H_N(loop_one_``X), \
.ENABLE_H(porb_h), \
.ENABLE_INP_H(loop_``X), \
.ENABLE_INP_H(loop_zero_``X), \
.ENABLE_VDDA_H(porb_h), \
.ENABLE_VSWITCH_H(vssa), \
.ENABLE_VDDIO(vccd), \
.ENABLE_VSWITCH_H(loop_zero_``X), \
.ENABLE_VDDIO(CONB_ONE), \
.INP_DIS(por), \
.IB_MODE_SEL(vssd), \
.VTRIP_SEL(vssd), \
.SLOW(vssd), \
.HLD_OVR(vssd), \
.ANALOG_EN(vssd), \
.ANALOG_SEL(vssd), \
.ANALOG_POL(vssd), \
.DM({vssd, vssd, vccd}), \
.IB_MODE_SEL(CONB_ZERO), \
.VTRIP_SEL(CONB_ZERO), \
.SLOW(CONB_ZERO), \
.HLD_OVR(CONB_ZERO), \
.ANALOG_EN(CONB_ZERO), \
.ANALOG_SEL(CONB_ZERO), \
.ANALOG_POL(CONB_ZERO), \
.DM({CONB_ZERO, CONB_ZERO, CONB_ONE}), \
.PAD_A_NOESD_H(), \
.PAD_A_ESD_0_H(), \
.PAD_A_ESD_1_H(), \
.IN(Y), \
.IN_H(), \
.TIE_HI_ESD(), \
.TIE_LO_ESD(loop_``X) )
.TIE_HI_ESD(loop_one_``X), \
.TIE_LO_ESD(loop_zero_``X) )
`define OUTPUT_PAD(X,Y,INPUT_DIS,OUT_EN_N) \
wire loop_``X; \
`define OUTPUT_PAD(X,Y,CONB_ONE,CONB_ZERO,INPUT_DIS,OUT_EN_N) \
wire loop_zero_``X; \
wire loop_one_``X; \
sky130_ef_io__gpiov2_pad_wrapped X``_pad ( \
`MGMT_ABUTMENT_PINS \
`ifndef TOP_ROUTING \
@ -114,31 +116,32 @@
`endif \
.OUT(Y), \
.OE_N(OUT_EN_N), \
.HLD_H_N(vddio), \
.HLD_H_N(loop_one_``X), \
.ENABLE_H(porb_h), \
.ENABLE_INP_H(loop_``X), \
.ENABLE_INP_H(loop_zero_``X), \
.ENABLE_VDDA_H(porb_h), \
.ENABLE_VSWITCH_H(vssa), \
.ENABLE_VDDIO(vccd), \
.ENABLE_VSWITCH_H(loop_zero_``X), \
.ENABLE_VDDIO(CONB_ONE), \
.INP_DIS(INPUT_DIS), \
.IB_MODE_SEL(vssd), \
.VTRIP_SEL(vssd), \
.SLOW(vssd), \
.HLD_OVR(vssd), \
.ANALOG_EN(vssd), \
.ANALOG_SEL(vssd), \
.ANALOG_POL(vssd), \
.DM({vccd, vccd, vssd}), \
.IB_MODE_SEL(CONB_ZERO), \
.VTRIP_SEL(CONB_ZERO), \
.SLOW(CONB_ZERO), \
.HLD_OVR(CONB_ZERO), \
.ANALOG_EN(CONB_ZERO), \
.ANALOG_SEL(CONB_ZERO), \
.ANALOG_POL(CONB_ZERO), \
.DM({CONB_ONE, CONB_ONE, CONB_ZERO}), \
.PAD_A_NOESD_H(), \
.PAD_A_ESD_0_H(), \
.PAD_A_ESD_1_H(), \
.IN(), \
.IN_H(), \
.TIE_HI_ESD(), \
.TIE_LO_ESD(loop_``X))
.TIE_HI_ESD(loop_one_``X), \
.TIE_LO_ESD(loop_zero_``X))
`define OUTPUT_NO_INP_DIS_PAD(X,Y,OUT_EN_N) \
wire loop_``X; \
`define OUTPUT_NO_INP_DIS_PAD(X,Y,CONB_ONE,CONB_ZERO,OUT_EN_N) \
wire loop_zero_``X; \
wire loop_one_``X; \
sky130_ef_io__gpiov2_pad_wrapped X``_pad ( \
`MGMT_ABUTMENT_PINS \
`ifndef TOP_ROUTING \
@ -146,31 +149,32 @@
`endif \
.OUT(Y), \
.OE_N(OUT_EN_N), \
.HLD_H_N(vddio), \
.HLD_H_N(loop_one_``X), \
.ENABLE_H(porb_h), \
.ENABLE_INP_H(loop_``X), \
.ENABLE_INP_H(loop_zero_``X), \
.ENABLE_VDDA_H(porb_h), \
.ENABLE_VSWITCH_H(vssa), \
.ENABLE_VDDIO(vccd), \
.INP_DIS(loop_``X), \
.IB_MODE_SEL(vssd), \
.VTRIP_SEL(vssd), \
.SLOW(vssd), \
.HLD_OVR(vssd), \
.ANALOG_EN(vssd), \
.ANALOG_SEL(vssd), \
.ANALOG_POL(vssd), \
.DM({vccd, vccd, vssd}), \
.ENABLE_VSWITCH_H(loop_zero_``X), \
.ENABLE_VDDIO(CONB_ONE), \
.INP_DIS(CONB_ZERO), \
.IB_MODE_SEL(CONB_ZERO), \
.VTRIP_SEL(CONB_ZERO), \
.SLOW(CONB_ZERO), \
.HLD_OVR(CONB_ZERO), \
.ANALOG_EN(CONB_ZERO), \
.ANALOG_SEL(CONB_ZERO), \
.ANALOG_POL(CONB_ZERO), \
.DM({CONB_ONE, CONB_ONE, CONB_ZERO}), \
.PAD_A_NOESD_H(), \
.PAD_A_ESD_0_H(), \
.PAD_A_ESD_1_H(), \
.IN(), \
.IN_H(), \
.TIE_HI_ESD(), \
.TIE_LO_ESD(loop_``X))
.TIE_HI_ESD(loop_one_``X), \
.TIE_LO_ESD(loop_zero_``X))
`define INOUT_PAD(X,Y,Y_OUT,INPUT_DIS,OUT_EN_N,MODE) \
wire loop_``X; \
`define INOUT_PAD(X,Y,CONB_ONE,CONB_ZERO,Y_OUT,INPUT_DIS,OUT_EN_N,MODE) \
wire loop_zero_``X; \
wire loop_one_``X; \
sky130_ef_io__gpiov2_pad_wrapped X``_pad ( \
`MGMT_ABUTMENT_PINS \
`ifndef TOP_ROUTING \
@ -178,27 +182,27 @@
`endif \
.OUT(Y_OUT), \
.OE_N(OUT_EN_N), \
.HLD_H_N(vddio), \
.HLD_H_N(loop_one_``X), \
.ENABLE_H(porb_h), \
.ENABLE_INP_H(loop_``X), \
.ENABLE_INP_H(loop_zero_``X), \
.ENABLE_VDDA_H(porb_h), \
.ENABLE_VSWITCH_H(vssa), \
.ENABLE_VDDIO(vccd), \
.ENABLE_VSWITCH_H(loop_zero_``X), \
.ENABLE_VDDIO(CONB_ONE), \
.INP_DIS(INPUT_DIS), \
.IB_MODE_SEL(vssd), \
.VTRIP_SEL(vssd), \
.SLOW(vssd), \
.HLD_OVR(vssd), \
.ANALOG_EN(vssd), \
.ANALOG_SEL(vssd), \
.ANALOG_POL(vssd), \
.IB_MODE_SEL(CONB_ZERO), \
.VTRIP_SEL(CONB_ZERO), \
.SLOW(CONB_ZERO), \
.HLD_OVR(CONB_ZERO), \
.ANALOG_EN(CONB_ZERO), \
.ANALOG_SEL(CONB_ZERO), \
.ANALOG_POL(CONB_ZERO), \
.DM(MODE), \
.PAD_A_NOESD_H(), \
.PAD_A_ESD_0_H(), \
.PAD_A_ESD_1_H(), \
.IN(Y), \
.IN_H(), \
.TIE_HI_ESD(), \
.TIE_LO_ESD(loop_``X) )
.TIE_HI_ESD(loop_one_``X), \
.TIE_LO_ESD(loop_zero_``X) )
// `default_nettype wire