mirror of https://github.com/efabless/caravel.git
[DATA] Update digital_pll pin placement to have it align with the HK
This commit is contained in:
manarabdelaty
parent
64bdd6230d
commit
37a07e291b
10980
def/digital_pll.def
10980
def/digital_pll.def
File diff suppressed because it is too large
Load Diff
Binary file not shown.
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@ -44,7 +44,7 @@ MACRO digital_pll
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 0.000 18.400 4.000 19.000 ;
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RECT 0.000 2.080 4.000 2.680 ;
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END
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END clockp[0]
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PIN clockp[1]
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@ -52,7 +52,7 @@ MACRO digital_pll
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 0.000 55.800 4.000 56.400 ;
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RECT 0.000 6.160 4.000 6.760 ;
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END
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END clockp[1]
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PIN dco
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@ -60,7 +60,7 @@ MACRO digital_pll
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 71.000 72.120 75.000 72.720 ;
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RECT 0.000 39.480 4.000 40.080 ;
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END
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END dco
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PIN div[0]
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@ -68,7 +68,7 @@ MACRO digital_pll
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 71.000 50.360 75.000 50.960 ;
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RECT 0.000 10.920 4.000 11.520 ;
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END
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END div[0]
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PIN div[1]
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@ -76,7 +76,7 @@ MACRO digital_pll
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 71.000 54.440 75.000 55.040 ;
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RECT 0.000 15.680 4.000 16.280 ;
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END
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END div[1]
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PIN div[2]
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@ -84,7 +84,7 @@ MACRO digital_pll
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 71.000 59.200 75.000 59.800 ;
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RECT 0.000 20.440 4.000 21.040 ;
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END
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END div[2]
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PIN div[3]
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@ -92,7 +92,7 @@ MACRO digital_pll
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 71.000 63.280 75.000 63.880 ;
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RECT 0.000 25.200 4.000 25.800 ;
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END
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END div[3]
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PIN div[4]
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@ -100,7 +100,7 @@ MACRO digital_pll
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 71.000 68.040 75.000 68.640 ;
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RECT 0.000 29.960 4.000 30.560 ;
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END
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END div[4]
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PIN enable
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@ -108,191 +108,191 @@ MACRO digital_pll
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 71.000 45.600 75.000 46.200 ;
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RECT 0.000 34.720 4.000 35.320 ;
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END
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END enable
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PIN ext_trim[0]
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met2 ;
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RECT 3.770 71.000 4.050 75.000 ;
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LAYER met3 ;
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RECT 0.000 43.560 4.000 44.160 ;
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END
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END ext_trim[0]
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PIN ext_trim[10]
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 71.000 2.080 75.000 2.680 ;
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LAYER met2 ;
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RECT 19.870 71.000 20.150 75.000 ;
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END
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END ext_trim[10]
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PIN ext_trim[11]
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 71.000 6.160 75.000 6.760 ;
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LAYER met2 ;
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RECT 25.850 71.000 26.130 75.000 ;
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END
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END ext_trim[11]
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PIN ext_trim[12]
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 71.000 10.240 75.000 10.840 ;
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LAYER met2 ;
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RECT 31.370 71.000 31.650 75.000 ;
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END
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END ext_trim[12]
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PIN ext_trim[13]
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 71.000 15.000 75.000 15.600 ;
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LAYER met2 ;
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RECT 37.350 71.000 37.630 75.000 ;
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END
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END ext_trim[13]
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PIN ext_trim[14]
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 71.000 19.080 75.000 19.680 ;
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LAYER met2 ;
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RECT 42.870 71.000 43.150 75.000 ;
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END
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END ext_trim[14]
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PIN ext_trim[15]
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 71.000 23.840 75.000 24.440 ;
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LAYER met2 ;
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RECT 48.850 71.000 49.130 75.000 ;
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END
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END ext_trim[15]
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PIN ext_trim[16]
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 71.000 27.920 75.000 28.520 ;
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LAYER met2 ;
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RECT 54.370 71.000 54.650 75.000 ;
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END
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END ext_trim[16]
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PIN ext_trim[17]
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 71.000 32.680 75.000 33.280 ;
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LAYER met2 ;
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RECT 60.350 71.000 60.630 75.000 ;
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END
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END ext_trim[17]
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PIN ext_trim[18]
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 71.000 36.760 75.000 37.360 ;
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LAYER met2 ;
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RECT 65.870 71.000 66.150 75.000 ;
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END
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END ext_trim[18]
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PIN ext_trim[19]
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 71.000 41.520 75.000 42.120 ;
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LAYER met2 ;
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RECT 71.850 71.000 72.130 75.000 ;
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END
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END ext_trim[19]
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PIN ext_trim[1]
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met2 ;
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RECT 11.130 71.000 11.410 75.000 ;
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LAYER met3 ;
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RECT 0.000 48.320 4.000 48.920 ;
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END
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END ext_trim[1]
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PIN ext_trim[20]
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met2 ;
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RECT 23.090 0.000 23.370 4.000 ;
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LAYER met3 ;
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RECT 71.000 68.040 75.000 68.640 ;
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END
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END ext_trim[20]
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PIN ext_trim[21]
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met2 ;
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RECT 32.750 0.000 33.030 4.000 ;
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LAYER met3 ;
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RECT 71.000 55.800 75.000 56.400 ;
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END
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END ext_trim[21]
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PIN ext_trim[22]
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met2 ;
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RECT 41.950 0.000 42.230 4.000 ;
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LAYER met3 ;
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RECT 71.000 43.560 75.000 44.160 ;
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END
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END ext_trim[22]
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PIN ext_trim[23]
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met2 ;
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RECT 51.150 0.000 51.430 4.000 ;
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LAYER met3 ;
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RECT 71.000 30.640 75.000 31.240 ;
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END
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END ext_trim[23]
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PIN ext_trim[24]
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met2 ;
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RECT 60.810 0.000 61.090 4.000 ;
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LAYER met3 ;
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RECT 71.000 18.400 75.000 19.000 ;
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END
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END ext_trim[24]
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PIN ext_trim[25]
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met2 ;
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RECT 70.010 0.000 70.290 4.000 ;
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LAYER met3 ;
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RECT 71.000 6.160 75.000 6.760 ;
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END
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END ext_trim[25]
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PIN ext_trim[2]
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met2 ;
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RECT 18.490 71.000 18.770 75.000 ;
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LAYER met3 ;
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RECT 0.000 53.080 4.000 53.680 ;
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END
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END ext_trim[2]
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PIN ext_trim[3]
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met2 ;
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RECT 25.850 71.000 26.130 75.000 ;
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LAYER met3 ;
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RECT 0.000 57.840 4.000 58.440 ;
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END
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END ext_trim[3]
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PIN ext_trim[4]
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met2 ;
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RECT 33.670 71.000 33.950 75.000 ;
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LAYER met3 ;
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RECT 0.000 62.600 4.000 63.200 ;
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END
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END ext_trim[4]
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PIN ext_trim[5]
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met2 ;
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RECT 41.030 71.000 41.310 75.000 ;
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LAYER met3 ;
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RECT 0.000 67.360 4.000 67.960 ;
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END
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END ext_trim[5]
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PIN ext_trim[6]
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met2 ;
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RECT 48.390 71.000 48.670 75.000 ;
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LAYER met3 ;
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RECT 0.000 72.120 4.000 72.720 ;
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END
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END ext_trim[6]
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PIN ext_trim[7]
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@ -300,7 +300,7 @@ MACRO digital_pll
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USE SIGNAL ;
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PORT
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LAYER met2 ;
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RECT 56.210 71.000 56.490 75.000 ;
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RECT 2.850 71.000 3.130 75.000 ;
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END
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END ext_trim[7]
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PIN ext_trim[8]
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@ -308,7 +308,7 @@ MACRO digital_pll
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USE SIGNAL ;
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PORT
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LAYER met2 ;
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RECT 63.570 71.000 63.850 75.000 ;
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RECT 8.370 71.000 8.650 75.000 ;
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END
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END ext_trim[8]
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PIN ext_trim[9]
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@ -316,7 +316,7 @@ MACRO digital_pll
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USE SIGNAL ;
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PORT
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LAYER met2 ;
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RECT 70.930 71.000 71.210 75.000 ;
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RECT 14.350 71.000 14.630 75.000 ;
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END
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END ext_trim[9]
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PIN osc
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@ -324,7 +324,7 @@ MACRO digital_pll
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USE SIGNAL ;
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PORT
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LAYER met2 ;
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RECT 13.890 0.000 14.170 4.000 ;
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RECT 55.750 0.000 56.030 4.000 ;
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END
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END osc
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PIN resetb
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@ -332,74 +332,71 @@ MACRO digital_pll
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USE SIGNAL ;
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PORT
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LAYER met2 ;
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RECT 4.690 0.000 4.970 4.000 ;
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RECT 18.490 0.000 18.770 4.000 ;
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END
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END resetb
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OBS
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LAYER li1 ;
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RECT 5.520 2.465 70.695 68.085 ;
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RECT 5.520 5.355 69.460 68.085 ;
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LAYER met1 ;
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RECT 3.750 2.420 71.230 68.240 ;
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RECT 2.830 5.200 72.150 68.980 ;
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LAYER met2 ;
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RECT 4.330 70.720 10.850 72.605 ;
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RECT 11.690 70.720 18.210 72.605 ;
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RECT 19.050 70.720 25.570 72.605 ;
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RECT 26.410 70.720 33.390 72.605 ;
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RECT 34.230 70.720 40.750 72.605 ;
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RECT 41.590 70.720 48.110 72.605 ;
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RECT 48.950 70.720 55.930 72.605 ;
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RECT 56.770 70.720 63.290 72.605 ;
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RECT 64.130 70.720 70.650 72.605 ;
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RECT 3.780 4.280 71.200 70.720 ;
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RECT 3.780 2.195 4.410 4.280 ;
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RECT 5.250 2.195 13.610 4.280 ;
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RECT 14.450 2.195 22.810 4.280 ;
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RECT 23.650 2.195 32.470 4.280 ;
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RECT 33.310 2.195 41.670 4.280 ;
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RECT 42.510 2.195 50.870 4.280 ;
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RECT 51.710 2.195 60.530 4.280 ;
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RECT 61.370 2.195 69.730 4.280 ;
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RECT 70.570 2.195 71.200 4.280 ;
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RECT 3.410 70.720 8.090 72.605 ;
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RECT 8.930 70.720 14.070 72.605 ;
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RECT 14.910 70.720 19.590 72.605 ;
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RECT 20.430 70.720 25.570 72.605 ;
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RECT 26.410 70.720 31.090 72.605 ;
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RECT 31.930 70.720 37.070 72.605 ;
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RECT 37.910 70.720 42.590 72.605 ;
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RECT 43.430 70.720 48.570 72.605 ;
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RECT 49.410 70.720 54.090 72.605 ;
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RECT 54.930 70.720 60.070 72.605 ;
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RECT 60.910 70.720 65.590 72.605 ;
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RECT 66.430 70.720 71.570 72.605 ;
|
||||
RECT 2.860 4.280 72.120 70.720 ;
|
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RECT 2.860 2.195 18.210 4.280 ;
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RECT 19.050 2.195 55.470 4.280 ;
|
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RECT 56.310 2.195 72.120 4.280 ;
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LAYER met3 ;
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RECT 4.000 71.720 70.600 72.585 ;
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RECT 4.400 71.720 71.000 72.585 ;
|
||||
RECT 4.000 69.040 71.000 71.720 ;
|
||||
RECT 4.000 67.640 70.600 69.040 ;
|
||||
RECT 4.000 64.280 71.000 67.640 ;
|
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RECT 4.000 62.880 70.600 64.280 ;
|
||||
RECT 4.000 60.200 71.000 62.880 ;
|
||||
RECT 4.000 58.800 70.600 60.200 ;
|
||||
RECT 4.000 56.800 71.000 58.800 ;
|
||||
RECT 4.400 55.440 71.000 56.800 ;
|
||||
RECT 4.400 55.400 70.600 55.440 ;
|
||||
RECT 4.000 54.040 70.600 55.400 ;
|
||||
RECT 4.000 51.360 71.000 54.040 ;
|
||||
RECT 4.000 49.960 70.600 51.360 ;
|
||||
RECT 4.000 46.600 71.000 49.960 ;
|
||||
RECT 4.000 45.200 70.600 46.600 ;
|
||||
RECT 4.000 42.520 71.000 45.200 ;
|
||||
RECT 4.000 41.120 70.600 42.520 ;
|
||||
RECT 4.000 37.760 71.000 41.120 ;
|
||||
RECT 4.000 36.360 70.600 37.760 ;
|
||||
RECT 4.000 33.680 71.000 36.360 ;
|
||||
RECT 4.000 32.280 70.600 33.680 ;
|
||||
RECT 4.000 28.920 71.000 32.280 ;
|
||||
RECT 4.000 27.520 70.600 28.920 ;
|
||||
RECT 4.000 24.840 71.000 27.520 ;
|
||||
RECT 4.000 23.440 70.600 24.840 ;
|
||||
RECT 4.000 20.080 71.000 23.440 ;
|
||||
RECT 4.000 19.400 70.600 20.080 ;
|
||||
RECT 4.400 18.680 70.600 19.400 ;
|
||||
RECT 4.400 18.000 71.000 18.680 ;
|
||||
RECT 4.000 16.000 71.000 18.000 ;
|
||||
RECT 4.000 14.600 70.600 16.000 ;
|
||||
RECT 4.000 11.240 71.000 14.600 ;
|
||||
RECT 4.000 9.840 70.600 11.240 ;
|
||||
RECT 4.000 7.160 71.000 9.840 ;
|
||||
RECT 4.000 5.760 70.600 7.160 ;
|
||||
RECT 4.000 68.360 70.600 69.040 ;
|
||||
RECT 4.400 67.640 70.600 68.360 ;
|
||||
RECT 4.400 66.960 71.000 67.640 ;
|
||||
RECT 4.000 63.600 71.000 66.960 ;
|
||||
RECT 4.400 62.200 71.000 63.600 ;
|
||||
RECT 4.000 58.840 71.000 62.200 ;
|
||||
RECT 4.400 57.440 71.000 58.840 ;
|
||||
RECT 4.000 56.800 71.000 57.440 ;
|
||||
RECT 4.000 55.400 70.600 56.800 ;
|
||||
RECT 4.000 54.080 71.000 55.400 ;
|
||||
RECT 4.400 52.680 71.000 54.080 ;
|
||||
RECT 4.000 49.320 71.000 52.680 ;
|
||||
RECT 4.400 47.920 71.000 49.320 ;
|
||||
RECT 4.000 44.560 71.000 47.920 ;
|
||||
RECT 4.400 43.160 70.600 44.560 ;
|
||||
RECT 4.000 40.480 71.000 43.160 ;
|
||||
RECT 4.400 39.080 71.000 40.480 ;
|
||||
RECT 4.000 35.720 71.000 39.080 ;
|
||||
RECT 4.400 34.320 71.000 35.720 ;
|
||||
RECT 4.000 31.640 71.000 34.320 ;
|
||||
RECT 4.000 30.960 70.600 31.640 ;
|
||||
RECT 4.400 30.240 70.600 30.960 ;
|
||||
RECT 4.400 29.560 71.000 30.240 ;
|
||||
RECT 4.000 26.200 71.000 29.560 ;
|
||||
RECT 4.400 24.800 71.000 26.200 ;
|
||||
RECT 4.000 21.440 71.000 24.800 ;
|
||||
RECT 4.400 20.040 71.000 21.440 ;
|
||||
RECT 4.000 19.400 71.000 20.040 ;
|
||||
RECT 4.000 18.000 70.600 19.400 ;
|
||||
RECT 4.000 16.680 71.000 18.000 ;
|
||||
RECT 4.400 15.280 71.000 16.680 ;
|
||||
RECT 4.000 11.920 71.000 15.280 ;
|
||||
RECT 4.400 10.520 71.000 11.920 ;
|
||||
RECT 4.000 7.160 71.000 10.520 ;
|
||||
RECT 4.400 5.760 70.600 7.160 ;
|
||||
RECT 4.000 3.080 71.000 5.760 ;
|
||||
RECT 4.000 2.215 70.600 3.080 ;
|
||||
LAYER met4 ;
|
||||
RECT 46.295 15.815 46.625 29.745 ;
|
||||
RECT 4.400 2.215 71.000 3.080 ;
|
||||
END
|
||||
END digital_pll
|
||||
END LIBRARY
|
||||
|
|
|
|||
33859
mag/digital_pll.mag
33859
mag/digital_pll.mag
File diff suppressed because it is too large
Load Diff
|
|
@ -1,114 +1,111 @@
|
|||
magic
|
||||
tech sky130A
|
||||
magscale 1 2
|
||||
timestamp 1636983913
|
||||
timestamp 1637256969
|
||||
<< obsli1 >>
|
||||
rect 1104 493 14139 13617
|
||||
rect 1104 1071 13892 13617
|
||||
<< obsm1 >>
|
||||
rect 750 484 14246 13648
|
||||
rect 566 1040 14430 13796
|
||||
<< metal2 >>
|
||||
rect 754 14200 810 15000
|
||||
rect 2226 14200 2282 15000
|
||||
rect 3698 14200 3754 15000
|
||||
rect 570 14200 626 15000
|
||||
rect 1674 14200 1730 15000
|
||||
rect 2870 14200 2926 15000
|
||||
rect 3974 14200 4030 15000
|
||||
rect 5170 14200 5226 15000
|
||||
rect 6734 14200 6790 15000
|
||||
rect 8206 14200 8262 15000
|
||||
rect 9678 14200 9734 15000
|
||||
rect 11242 14200 11298 15000
|
||||
rect 12714 14200 12770 15000
|
||||
rect 14186 14200 14242 15000
|
||||
rect 938 0 994 800
|
||||
rect 2778 0 2834 800
|
||||
rect 4618 0 4674 800
|
||||
rect 6550 0 6606 800
|
||||
rect 8390 0 8446 800
|
||||
rect 10230 0 10286 800
|
||||
rect 12162 0 12218 800
|
||||
rect 14002 0 14058 800
|
||||
rect 6274 14200 6330 15000
|
||||
rect 7470 14200 7526 15000
|
||||
rect 8574 14200 8630 15000
|
||||
rect 9770 14200 9826 15000
|
||||
rect 10874 14200 10930 15000
|
||||
rect 12070 14200 12126 15000
|
||||
rect 13174 14200 13230 15000
|
||||
rect 14370 14200 14426 15000
|
||||
rect 3698 0 3754 800
|
||||
rect 11150 0 11206 800
|
||||
<< obsm2 >>
|
||||
rect 866 14144 2170 14521
|
||||
rect 2338 14144 3642 14521
|
||||
rect 3810 14144 5114 14521
|
||||
rect 5282 14144 6678 14521
|
||||
rect 6846 14144 8150 14521
|
||||
rect 8318 14144 9622 14521
|
||||
rect 9790 14144 11186 14521
|
||||
rect 11354 14144 12658 14521
|
||||
rect 12826 14144 14130 14521
|
||||
rect 756 856 14240 14144
|
||||
rect 756 439 882 856
|
||||
rect 1050 439 2722 856
|
||||
rect 2890 439 4562 856
|
||||
rect 4730 439 6494 856
|
||||
rect 6662 439 8334 856
|
||||
rect 8502 439 10174 856
|
||||
rect 10342 439 12106 856
|
||||
rect 12274 439 13946 856
|
||||
rect 14114 439 14240 856
|
||||
rect 682 14144 1618 14521
|
||||
rect 1786 14144 2814 14521
|
||||
rect 2982 14144 3918 14521
|
||||
rect 4086 14144 5114 14521
|
||||
rect 5282 14144 6218 14521
|
||||
rect 6386 14144 7414 14521
|
||||
rect 7582 14144 8518 14521
|
||||
rect 8686 14144 9714 14521
|
||||
rect 9882 14144 10818 14521
|
||||
rect 10986 14144 12014 14521
|
||||
rect 12182 14144 13118 14521
|
||||
rect 13286 14144 14314 14521
|
||||
rect 572 856 14424 14144
|
||||
rect 572 439 3642 856
|
||||
rect 3810 439 11094 856
|
||||
rect 11262 439 14424 856
|
||||
<< metal3 >>
|
||||
rect 14200 14424 15000 14544
|
||||
rect 0 14424 800 14544
|
||||
rect 0 13472 800 13592
|
||||
rect 14200 13608 15000 13728
|
||||
rect 14200 12656 15000 12776
|
||||
rect 14200 11840 15000 11960
|
||||
rect 0 11160 800 11280
|
||||
rect 14200 10888 15000 11008
|
||||
rect 14200 10072 15000 10192
|
||||
rect 14200 9120 15000 9240
|
||||
rect 14200 8304 15000 8424
|
||||
rect 14200 7352 15000 7472
|
||||
rect 14200 6536 15000 6656
|
||||
rect 14200 5584 15000 5704
|
||||
rect 14200 4768 15000 4888
|
||||
rect 0 3680 800 3800
|
||||
rect 14200 3816 15000 3936
|
||||
rect 14200 3000 15000 3120
|
||||
rect 14200 2048 15000 2168
|
||||
rect 0 12520 800 12640
|
||||
rect 0 11568 800 11688
|
||||
rect 14200 11160 15000 11280
|
||||
rect 0 10616 800 10736
|
||||
rect 0 9664 800 9784
|
||||
rect 0 8712 800 8832
|
||||
rect 14200 8712 15000 8832
|
||||
rect 0 7896 800 8016
|
||||
rect 0 6944 800 7064
|
||||
rect 0 5992 800 6112
|
||||
rect 14200 6128 15000 6248
|
||||
rect 0 5040 800 5160
|
||||
rect 0 4088 800 4208
|
||||
rect 14200 3680 15000 3800
|
||||
rect 0 3136 800 3256
|
||||
rect 0 2184 800 2304
|
||||
rect 0 1232 800 1352
|
||||
rect 14200 1232 15000 1352
|
||||
rect 14200 416 15000 536
|
||||
rect 0 416 800 536
|
||||
<< obsm3 >>
|
||||
rect 800 14344 14120 14517
|
||||
rect 880 14344 14200 14517
|
||||
rect 800 13808 14200 14344
|
||||
rect 800 13528 14120 13808
|
||||
rect 800 12856 14200 13528
|
||||
rect 800 12576 14120 12856
|
||||
rect 800 12040 14200 12576
|
||||
rect 800 11760 14120 12040
|
||||
rect 800 11360 14200 11760
|
||||
rect 880 11088 14200 11360
|
||||
rect 880 11080 14120 11088
|
||||
rect 800 10808 14120 11080
|
||||
rect 800 10272 14200 10808
|
||||
rect 800 9992 14120 10272
|
||||
rect 800 9320 14200 9992
|
||||
rect 800 9040 14120 9320
|
||||
rect 800 8504 14200 9040
|
||||
rect 800 8224 14120 8504
|
||||
rect 800 7552 14200 8224
|
||||
rect 800 7272 14120 7552
|
||||
rect 800 6736 14200 7272
|
||||
rect 800 6456 14120 6736
|
||||
rect 800 5784 14200 6456
|
||||
rect 800 5504 14120 5784
|
||||
rect 800 4968 14200 5504
|
||||
rect 800 4688 14120 4968
|
||||
rect 800 4016 14200 4688
|
||||
rect 800 3880 14120 4016
|
||||
rect 880 3736 14120 3880
|
||||
rect 880 3600 14200 3736
|
||||
rect 800 3200 14200 3600
|
||||
rect 800 2920 14120 3200
|
||||
rect 800 2248 14200 2920
|
||||
rect 800 1968 14120 2248
|
||||
rect 800 1432 14200 1968
|
||||
rect 800 1152 14120 1432
|
||||
rect 800 13672 14120 13808
|
||||
rect 880 13528 14120 13672
|
||||
rect 880 13392 14200 13528
|
||||
rect 800 12720 14200 13392
|
||||
rect 880 12440 14200 12720
|
||||
rect 800 11768 14200 12440
|
||||
rect 880 11488 14200 11768
|
||||
rect 800 11360 14200 11488
|
||||
rect 800 11080 14120 11360
|
||||
rect 800 10816 14200 11080
|
||||
rect 880 10536 14200 10816
|
||||
rect 800 9864 14200 10536
|
||||
rect 880 9584 14200 9864
|
||||
rect 800 8912 14200 9584
|
||||
rect 880 8632 14120 8912
|
||||
rect 800 8096 14200 8632
|
||||
rect 880 7816 14200 8096
|
||||
rect 800 7144 14200 7816
|
||||
rect 880 6864 14200 7144
|
||||
rect 800 6328 14200 6864
|
||||
rect 800 6192 14120 6328
|
||||
rect 880 6048 14120 6192
|
||||
rect 880 5912 14200 6048
|
||||
rect 800 5240 14200 5912
|
||||
rect 880 4960 14200 5240
|
||||
rect 800 4288 14200 4960
|
||||
rect 880 4008 14200 4288
|
||||
rect 800 3880 14200 4008
|
||||
rect 800 3600 14120 3880
|
||||
rect 800 3336 14200 3600
|
||||
rect 880 3056 14200 3336
|
||||
rect 800 2384 14200 3056
|
||||
rect 880 2104 14200 2384
|
||||
rect 800 1432 14200 2104
|
||||
rect 880 1152 14120 1432
|
||||
rect 800 616 14200 1152
|
||||
rect 800 443 14120 616
|
||||
rect 880 443 14200 616
|
||||
<< metal4 >>
|
||||
rect 4208 1040 4528 13648
|
||||
rect 8208 1040 8528 13648
|
||||
rect 12208 1040 12528 13648
|
||||
<< obsm4 >>
|
||||
rect 9259 3163 9325 5949
|
||||
<< metal5 >>
|
||||
rect 1104 12210 13892 12530
|
||||
rect 1104 8210 13892 8530
|
||||
|
|
@ -126,86 +123,86 @@ rlabel metal4 s 4208 1040 4528 13648 6 VPWR
|
|||
port 2 nsew power input
|
||||
rlabel metal4 s 12208 1040 12528 13648 6 VPWR
|
||||
port 2 nsew power input
|
||||
rlabel metal3 s 0 3680 800 3800 6 clockp[0]
|
||||
rlabel metal3 s 0 416 800 536 6 clockp[0]
|
||||
port 3 nsew signal output
|
||||
rlabel metal3 s 0 11160 800 11280 6 clockp[1]
|
||||
rlabel metal3 s 0 1232 800 1352 6 clockp[1]
|
||||
port 4 nsew signal output
|
||||
rlabel metal3 s 14200 14424 15000 14544 6 dco
|
||||
rlabel metal3 s 0 7896 800 8016 6 dco
|
||||
port 5 nsew signal input
|
||||
rlabel metal3 s 14200 10072 15000 10192 6 div[0]
|
||||
rlabel metal3 s 0 2184 800 2304 6 div[0]
|
||||
port 6 nsew signal input
|
||||
rlabel metal3 s 14200 10888 15000 11008 6 div[1]
|
||||
rlabel metal3 s 0 3136 800 3256 6 div[1]
|
||||
port 7 nsew signal input
|
||||
rlabel metal3 s 14200 11840 15000 11960 6 div[2]
|
||||
rlabel metal3 s 0 4088 800 4208 6 div[2]
|
||||
port 8 nsew signal input
|
||||
rlabel metal3 s 14200 12656 15000 12776 6 div[3]
|
||||
rlabel metal3 s 0 5040 800 5160 6 div[3]
|
||||
port 9 nsew signal input
|
||||
rlabel metal3 s 14200 13608 15000 13728 6 div[4]
|
||||
rlabel metal3 s 0 5992 800 6112 6 div[4]
|
||||
port 10 nsew signal input
|
||||
rlabel metal3 s 14200 9120 15000 9240 6 enable
|
||||
rlabel metal3 s 0 6944 800 7064 6 enable
|
||||
port 11 nsew signal input
|
||||
rlabel metal2 s 754 14200 810 15000 6 ext_trim[0]
|
||||
rlabel metal3 s 0 8712 800 8832 6 ext_trim[0]
|
||||
port 12 nsew signal input
|
||||
rlabel metal3 s 14200 416 15000 536 6 ext_trim[10]
|
||||
rlabel metal2 s 3974 14200 4030 15000 6 ext_trim[10]
|
||||
port 13 nsew signal input
|
||||
rlabel metal3 s 14200 1232 15000 1352 6 ext_trim[11]
|
||||
rlabel metal2 s 5170 14200 5226 15000 6 ext_trim[11]
|
||||
port 14 nsew signal input
|
||||
rlabel metal3 s 14200 2048 15000 2168 6 ext_trim[12]
|
||||
rlabel metal2 s 6274 14200 6330 15000 6 ext_trim[12]
|
||||
port 15 nsew signal input
|
||||
rlabel metal3 s 14200 3000 15000 3120 6 ext_trim[13]
|
||||
rlabel metal2 s 7470 14200 7526 15000 6 ext_trim[13]
|
||||
port 16 nsew signal input
|
||||
rlabel metal3 s 14200 3816 15000 3936 6 ext_trim[14]
|
||||
rlabel metal2 s 8574 14200 8630 15000 6 ext_trim[14]
|
||||
port 17 nsew signal input
|
||||
rlabel metal3 s 14200 4768 15000 4888 6 ext_trim[15]
|
||||
rlabel metal2 s 9770 14200 9826 15000 6 ext_trim[15]
|
||||
port 18 nsew signal input
|
||||
rlabel metal3 s 14200 5584 15000 5704 6 ext_trim[16]
|
||||
rlabel metal2 s 10874 14200 10930 15000 6 ext_trim[16]
|
||||
port 19 nsew signal input
|
||||
rlabel metal3 s 14200 6536 15000 6656 6 ext_trim[17]
|
||||
rlabel metal2 s 12070 14200 12126 15000 6 ext_trim[17]
|
||||
port 20 nsew signal input
|
||||
rlabel metal3 s 14200 7352 15000 7472 6 ext_trim[18]
|
||||
rlabel metal2 s 13174 14200 13230 15000 6 ext_trim[18]
|
||||
port 21 nsew signal input
|
||||
rlabel metal3 s 14200 8304 15000 8424 6 ext_trim[19]
|
||||
rlabel metal2 s 14370 14200 14426 15000 6 ext_trim[19]
|
||||
port 22 nsew signal input
|
||||
rlabel metal2 s 2226 14200 2282 15000 6 ext_trim[1]
|
||||
rlabel metal3 s 0 9664 800 9784 6 ext_trim[1]
|
||||
port 23 nsew signal input
|
||||
rlabel metal2 s 4618 0 4674 800 6 ext_trim[20]
|
||||
rlabel metal3 s 14200 13608 15000 13728 6 ext_trim[20]
|
||||
port 24 nsew signal input
|
||||
rlabel metal2 s 6550 0 6606 800 6 ext_trim[21]
|
||||
rlabel metal3 s 14200 11160 15000 11280 6 ext_trim[21]
|
||||
port 25 nsew signal input
|
||||
rlabel metal2 s 8390 0 8446 800 6 ext_trim[22]
|
||||
rlabel metal3 s 14200 8712 15000 8832 6 ext_trim[22]
|
||||
port 26 nsew signal input
|
||||
rlabel metal2 s 10230 0 10286 800 6 ext_trim[23]
|
||||
rlabel metal3 s 14200 6128 15000 6248 6 ext_trim[23]
|
||||
port 27 nsew signal input
|
||||
rlabel metal2 s 12162 0 12218 800 6 ext_trim[24]
|
||||
rlabel metal3 s 14200 3680 15000 3800 6 ext_trim[24]
|
||||
port 28 nsew signal input
|
||||
rlabel metal2 s 14002 0 14058 800 6 ext_trim[25]
|
||||
rlabel metal3 s 14200 1232 15000 1352 6 ext_trim[25]
|
||||
port 29 nsew signal input
|
||||
rlabel metal2 s 3698 14200 3754 15000 6 ext_trim[2]
|
||||
rlabel metal3 s 0 10616 800 10736 6 ext_trim[2]
|
||||
port 30 nsew signal input
|
||||
rlabel metal2 s 5170 14200 5226 15000 6 ext_trim[3]
|
||||
rlabel metal3 s 0 11568 800 11688 6 ext_trim[3]
|
||||
port 31 nsew signal input
|
||||
rlabel metal2 s 6734 14200 6790 15000 6 ext_trim[4]
|
||||
rlabel metal3 s 0 12520 800 12640 6 ext_trim[4]
|
||||
port 32 nsew signal input
|
||||
rlabel metal2 s 8206 14200 8262 15000 6 ext_trim[5]
|
||||
rlabel metal3 s 0 13472 800 13592 6 ext_trim[5]
|
||||
port 33 nsew signal input
|
||||
rlabel metal2 s 9678 14200 9734 15000 6 ext_trim[6]
|
||||
rlabel metal3 s 0 14424 800 14544 6 ext_trim[6]
|
||||
port 34 nsew signal input
|
||||
rlabel metal2 s 11242 14200 11298 15000 6 ext_trim[7]
|
||||
rlabel metal2 s 570 14200 626 15000 6 ext_trim[7]
|
||||
port 35 nsew signal input
|
||||
rlabel metal2 s 12714 14200 12770 15000 6 ext_trim[8]
|
||||
rlabel metal2 s 1674 14200 1730 15000 6 ext_trim[8]
|
||||
port 36 nsew signal input
|
||||
rlabel metal2 s 14186 14200 14242 15000 6 ext_trim[9]
|
||||
rlabel metal2 s 2870 14200 2926 15000 6 ext_trim[9]
|
||||
port 37 nsew signal input
|
||||
rlabel metal2 s 2778 0 2834 800 6 osc
|
||||
rlabel metal2 s 11150 0 11206 800 6 osc
|
||||
port 38 nsew signal input
|
||||
rlabel metal2 s 938 0 994 800 6 resetb
|
||||
rlabel metal2 s 3698 0 3754 800 6 resetb
|
||||
port 39 nsew signal input
|
||||
<< properties >>
|
||||
string LEFclass BLOCK
|
||||
string FIXED_BBOX 0 0 15000 15000
|
||||
string LEFview TRUE
|
||||
string GDS_FILE /project/openlane/digital_pll/runs/digital_pll/results/magic/digital_pll.gds
|
||||
string GDS_END 1103818
|
||||
string GDS_START 342938
|
||||
string GDS_FILE /home/ma/ef/caravel_openframe/openlane/digital_pll/runs/digital_pll/results/magic/digital_pll.gds
|
||||
string GDS_END 1056694
|
||||
string GDS_START 339452
|
||||
<< end >>
|
||||
|
||||
|
|
|
|||
|
|
@ -53,8 +53,10 @@ set ::env(PL_TARGET_DENSITY) 0.82
|
|||
|
||||
## Routing
|
||||
set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) 0
|
||||
|
||||
set ::env(GLB_RT_ADJUSTMENT) 0
|
||||
|
||||
set ::env(GLB_RT_MINLAYER) 2
|
||||
set ::env(GLB_RT_MAXLAYER) 6
|
||||
|
||||
## Diode Insertion
|
||||
set ::env(DIODE_INSERTION_STRATEGY) "4"
|
||||
set ::env(DIODE_INSERTION_STRATEGY) "3"
|
||||
|
|
|
|||
|
|
@ -1,18 +1,23 @@
|
|||
#N
|
||||
ext_trim\[[0-9]\]
|
||||
ext_trim\[[7-9]\]
|
||||
ext_trim\[1[0-9]\]
|
||||
|
||||
#E
|
||||
ext_trim\[25\]
|
||||
ext_trim\[24\]
|
||||
ext_trim\[23\]
|
||||
ext_trim\[22\]
|
||||
ext_trim\[21\]
|
||||
ext_trim\[20\]
|
||||
|
||||
#W
|
||||
clockp.*
|
||||
|
||||
#E
|
||||
ext_trim\[1[0-5]\]
|
||||
ext_trim\[1[6-9]\]
|
||||
enable
|
||||
div.*
|
||||
enable
|
||||
dco.*
|
||||
ext_trim\[[0-6]\]
|
||||
|
||||
#S
|
||||
resetb
|
||||
osc
|
||||
ext_trim\[2[0-5]\]
|
||||
|
||||
|
|
|
|||
|
|
@ -1 +1 @@
|
|||
openlane 2021.09.09_03.00.48-60-gcbb562b
|
||||
openlane 2021.09.09_03.00.48-66-gbdb1b56
|
||||
|
|
|
|||
|
|
@ -1,2 +1,2 @@
|
|||
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
|
||||
0,/project/openlane/digital_pll,digital_pll,digital_pll,flow_completed,0h1m45s,-1,110933.33333333334,0.005625,55466.66666666667,81.42,533.2,312,0,-1,-1,-1,-1,0,0,-1,0,0,-1,5954,2241,0.0,0.0,-1,0.0,-1,0.0,0.0,-1,0.0,-1,4109866.0,23.53,31.05,21.81,0.0,0.0,0.0,613,808,120,303,0,0,0,646,0,0,0,0,0,0,0,4,31,72,20,46,50,0,96,90.9090909090909,11.0,10.0,AREA 0,6,50,1,40,40,0.82,0,sky130_fd_sc_hd,0,4
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0,/home/ma/ef/caravel_openframe/openlane/digital_pll,digital_pll,digital_pll,flow_completed,0h1m27s,-1,110933.33333333334,0.005625,55466.66666666667,81.42,528.28,312,0,-1,-1,-1,-1,0,0,-1,0,0,-1,5503,2119,0.0,0.0,-1,0.0,-1,0.0,0.0,-1,0.0,-1,3849516.0,0.0,30.32,23.6,0.0,0.0,0.0,613,808,120,303,0,0,0,646,0,0,0,0,0,0,0,4,31,72,20,46,50,0,96,90.9090909090909,11.0,10.0,AREA 0,6,50,1,40,40,0.82,0,sky130_fd_sc_hd,0,3
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Reference in New Issue