mirror of https://github.com/efabless/caravel.git
- update gpio_control_block config (#57)
- update gpio_control_block views - gitignore gds/*gds
This commit is contained in:
Kareem Farid
GitHub
parent
e9f023f9fa
commit
e3b9a99154
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@ -1 +1,2 @@
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/mgmt_core_wrapper/*
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gds/*.gds
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File diff suppressed because it is too large
Load Diff
Binary file not shown.
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@ -440,12 +440,18 @@ MACRO gpio_control_block
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END
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END zero
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OBS
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LAYER nwell ;
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RECT 4.410 55.705 49.410 57.310 ;
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RECT 4.410 50.265 49.410 53.095 ;
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RECT 4.410 44.825 49.410 47.655 ;
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RECT 4.410 39.385 49.410 42.215 ;
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RECT 4.410 33.945 49.410 36.775 ;
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RECT 4.410 28.505 49.410 31.335 ;
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LAYER li1 ;
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RECT 4.600 5.355 49.220 57.205 ;
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LAYER met1 ;
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RECT 0.070 3.440 110.790 59.460 ;
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RECT 4.600 5.200 83.650 57.760 ;
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LAYER met2 ;
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RECT 0.100 60.720 4.410 61.725 ;
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RECT 5.250 60.720 6.710 61.725 ;
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RECT 7.550 60.720 9.010 61.725 ;
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RECT 9.850 60.720 11.310 61.725 ;
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@ -458,66 +464,68 @@ MACRO gpio_control_block
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RECT 25.950 60.720 27.410 61.725 ;
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RECT 28.250 60.720 29.710 61.725 ;
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RECT 30.550 60.720 32.010 61.725 ;
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RECT 32.850 60.720 110.770 61.725 ;
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RECT 0.100 2.195 110.770 60.720 ;
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RECT 32.850 60.720 83.620 61.725 ;
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RECT 4.970 2.195 83.620 60.720 ;
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LAYER met3 ;
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RECT 3.745 60.840 69.600 61.705 ;
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RECT 3.745 60.200 70.000 60.840 ;
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RECT 3.745 56.760 69.600 58.160 ;
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RECT 3.745 56.120 70.000 56.760 ;
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RECT 3.745 54.720 69.600 56.120 ;
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RECT 3.745 40.440 69.600 41.840 ;
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RECT 3.745 30.240 69.600 31.640 ;
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RECT 3.745 29.600 70.000 30.240 ;
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RECT 3.745 28.200 69.600 29.600 ;
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RECT 3.745 27.560 70.000 28.200 ;
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RECT 3.745 26.160 69.600 27.560 ;
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RECT 3.745 25.520 70.000 26.160 ;
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RECT 3.745 24.120 69.600 25.520 ;
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RECT 3.745 23.480 70.000 24.120 ;
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RECT 3.745 22.080 69.600 23.480 ;
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RECT 3.745 21.440 70.000 22.080 ;
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RECT 3.745 20.040 69.600 21.440 ;
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RECT 3.745 18.000 69.600 19.400 ;
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RECT 3.745 15.320 70.000 15.960 ;
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RECT 3.745 13.920 69.600 15.320 ;
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RECT 3.745 13.280 70.000 13.920 ;
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RECT 3.745 11.880 69.600 13.280 ;
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RECT 3.745 11.240 70.000 11.880 ;
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RECT 3.745 9.840 69.600 11.240 ;
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RECT 3.745 9.200 70.000 9.840 ;
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RECT 3.745 7.800 69.600 9.200 ;
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RECT 3.745 7.160 70.000 7.800 ;
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RECT 3.745 5.760 69.600 7.160 ;
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RECT 3.745 5.120 70.000 5.760 ;
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RECT 3.745 4.255 69.600 5.120 ;
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RECT 6.280 60.840 69.600 61.705 ;
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RECT 6.280 60.200 70.000 60.840 ;
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RECT 6.280 58.800 69.600 60.200 ;
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RECT 6.280 58.160 70.000 58.800 ;
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RECT 6.280 56.760 69.600 58.160 ;
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RECT 6.280 56.120 70.000 56.760 ;
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RECT 6.280 54.720 69.600 56.120 ;
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RECT 6.280 54.080 70.000 54.720 ;
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RECT 6.280 52.680 69.600 54.080 ;
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RECT 6.280 52.040 70.000 52.680 ;
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RECT 6.280 50.640 69.600 52.040 ;
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RECT 6.280 50.000 70.000 50.640 ;
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RECT 6.280 48.600 69.600 50.000 ;
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RECT 6.280 47.960 70.000 48.600 ;
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RECT 6.280 46.560 69.600 47.960 ;
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RECT 6.280 45.920 70.000 46.560 ;
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RECT 6.280 44.520 69.600 45.920 ;
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RECT 6.280 43.880 70.000 44.520 ;
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RECT 6.280 42.480 69.600 43.880 ;
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RECT 6.280 41.840 70.000 42.480 ;
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RECT 6.280 40.440 69.600 41.840 ;
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RECT 6.280 39.800 70.000 40.440 ;
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RECT 6.280 38.400 69.600 39.800 ;
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RECT 6.280 37.760 70.000 38.400 ;
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RECT 6.280 36.360 69.600 37.760 ;
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RECT 6.280 35.720 70.000 36.360 ;
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RECT 6.280 34.320 69.600 35.720 ;
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RECT 6.280 33.680 70.000 34.320 ;
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RECT 6.280 32.280 69.600 33.680 ;
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RECT 6.280 31.640 70.000 32.280 ;
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RECT 6.280 30.240 69.600 31.640 ;
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RECT 6.280 29.600 70.000 30.240 ;
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RECT 6.280 28.200 69.600 29.600 ;
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RECT 6.280 27.560 70.000 28.200 ;
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RECT 6.280 26.160 69.600 27.560 ;
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RECT 6.280 25.520 70.000 26.160 ;
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RECT 6.280 24.120 69.600 25.520 ;
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RECT 6.280 23.480 70.000 24.120 ;
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RECT 6.280 22.080 69.600 23.480 ;
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RECT 6.280 21.440 70.000 22.080 ;
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RECT 6.280 20.040 69.600 21.440 ;
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RECT 6.280 19.400 70.000 20.040 ;
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RECT 6.280 18.000 69.600 19.400 ;
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RECT 6.280 17.360 70.000 18.000 ;
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RECT 6.280 15.960 69.600 17.360 ;
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RECT 6.280 15.320 70.000 15.960 ;
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RECT 6.280 13.920 69.600 15.320 ;
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RECT 6.280 13.280 70.000 13.920 ;
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RECT 6.280 11.880 69.600 13.280 ;
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RECT 6.280 11.240 70.000 11.880 ;
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RECT 6.280 9.840 69.600 11.240 ;
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RECT 6.280 9.200 70.000 9.840 ;
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RECT 6.280 7.800 69.600 9.200 ;
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RECT 6.280 7.160 70.000 7.800 ;
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RECT 6.280 5.760 69.600 7.160 ;
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RECT 6.280 5.120 70.000 5.760 ;
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RECT 6.280 3.720 69.600 5.120 ;
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RECT 6.280 3.080 70.000 3.720 ;
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RECT 6.280 2.215 69.600 3.080 ;
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LAYER met4 ;
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RECT 6.280 8.160 11.380 22.240 ;
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END
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File diff suppressed because it is too large
Load Diff
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@ -1,11 +1,18 @@
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magic
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tech sky130A
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magscale 1 2
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timestamp 1640362204
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timestamp 1649159639
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<< nwell >>
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rect 882 11141 9882 11462
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rect 882 10053 9882 10619
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rect 882 8965 9882 9531
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rect 882 7877 9882 8443
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rect 882 6789 9882 7355
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rect 882 5701 9882 6267
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<< obsli1 >>
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rect 920 1071 9844 11441
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<< obsm1 >>
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rect 14 688 22158 11892
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rect 920 1040 16730 11552
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<< metal2 >>
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rect 938 12200 994 13000
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rect 1398 12200 1454 13000
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@ -21,7 +28,6 @@ rect 5538 12200 5594 13000
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rect 5998 12200 6054 13000
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rect 6458 12200 6514 13000
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<< obsm2 >>
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rect 20 12144 882 12345
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rect 1050 12144 1342 12345
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rect 1510 12144 1802 12345
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rect 1970 12144 2262 12345
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@ -34,8 +40,8 @@ rect 4730 12144 5022 12345
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rect 5190 12144 5482 12345
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rect 5650 12144 5942 12345
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rect 6110 12144 6402 12345
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rect 6570 12144 22154 12345
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rect 20 439 22154 12144
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rect 6570 12144 16724 12345
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rect 994 439 16724 12144
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<< metal3 >>
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rect 14000 12248 34000 12368
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rect 14000 11840 34000 11960
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@ -68,63 +74,65 @@ rect 14000 1232 34000 1352
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rect 14000 824 34000 944
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rect 14000 416 34000 536
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<< obsm3 >>
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rect 749 12168 13920 12341
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rect 749 12040 14000 12168
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rect 749 11760 13920 12040
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rect 749 11632 14000 11760
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rect 749 11352 13920 11632
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rect 749 11224 14000 11352
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rect 749 10944 13920 11224
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rect 749 10816 14000 10944
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rect 749 10536 13920 10816
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rect 749 10408 14000 10536
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rect 749 10128 13920 10408
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rect 749 10000 14000 10128
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rect 749 9720 13920 10000
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rect 749 9592 14000 9720
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rect 749 9312 13920 9592
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rect 749 9184 14000 9312
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rect 749 8904 13920 9184
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rect 749 8776 14000 8904
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rect 749 8496 13920 8776
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rect 749 8368 14000 8496
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rect 749 8088 13920 8368
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rect 749 7960 14000 8088
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rect 749 7680 13920 7960
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rect 749 7552 14000 7680
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||||
rect 749 7272 13920 7552
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rect 749 7144 14000 7272
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rect 749 6864 13920 7144
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||||
rect 749 6736 14000 6864
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||||
rect 749 6456 13920 6736
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rect 749 6328 14000 6456
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rect 749 6048 13920 6328
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rect 749 5920 14000 6048
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rect 749 5640 13920 5920
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rect 749 5512 14000 5640
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||||
rect 749 5232 13920 5512
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rect 749 5104 14000 5232
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||||
rect 749 4824 13920 5104
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||||
rect 749 4696 14000 4824
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||||
rect 749 4416 13920 4696
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||||
rect 749 4288 14000 4416
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||||
rect 749 4008 13920 4288
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||||
rect 749 3880 14000 4008
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rect 749 3600 13920 3880
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||||
rect 749 3472 14000 3600
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rect 749 3192 13920 3472
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||||
rect 749 3064 14000 3192
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||||
rect 749 2784 13920 3064
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||||
rect 749 2656 14000 2784
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||||
rect 749 2376 13920 2656
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||||
rect 749 2248 14000 2376
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||||
rect 749 1968 13920 2248
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||||
rect 749 1840 14000 1968
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||||
rect 749 1560 13920 1840
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||||
rect 749 1432 14000 1560
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||||
rect 749 1152 13920 1432
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||||
rect 749 1024 14000 1152
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||||
rect 749 851 13920 1024
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||||
rect 1256 12168 13920 12341
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||||
rect 1256 12040 14000 12168
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||||
rect 1256 11760 13920 12040
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||||
rect 1256 11632 14000 11760
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||||
rect 1256 11352 13920 11632
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||||
rect 1256 11224 14000 11352
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||||
rect 1256 10944 13920 11224
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||||
rect 1256 10816 14000 10944
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||||
rect 1256 10536 13920 10816
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||||
rect 1256 10408 14000 10536
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||||
rect 1256 10128 13920 10408
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||||
rect 1256 10000 14000 10128
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||||
rect 1256 9720 13920 10000
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||||
rect 1256 9592 14000 9720
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||||
rect 1256 9312 13920 9592
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||||
rect 1256 9184 14000 9312
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||||
rect 1256 8904 13920 9184
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rect 1256 8776 14000 8904
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||||
rect 1256 8496 13920 8776
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||||
rect 1256 8368 14000 8496
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||||
rect 1256 8088 13920 8368
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||||
rect 1256 7960 14000 8088
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||||
rect 1256 7680 13920 7960
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||||
rect 1256 7552 14000 7680
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||||
rect 1256 7272 13920 7552
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||||
rect 1256 7144 14000 7272
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||||
rect 1256 6864 13920 7144
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||||
rect 1256 6736 14000 6864
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||||
rect 1256 6456 13920 6736
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||||
rect 1256 6328 14000 6456
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||||
rect 1256 6048 13920 6328
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||||
rect 1256 5920 14000 6048
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||||
rect 1256 5640 13920 5920
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||||
rect 1256 5512 14000 5640
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||||
rect 1256 5232 13920 5512
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||||
rect 1256 5104 14000 5232
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||||
rect 1256 4824 13920 5104
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||||
rect 1256 4696 14000 4824
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||||
rect 1256 4416 13920 4696
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||||
rect 1256 4288 14000 4416
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||||
rect 1256 4008 13920 4288
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||||
rect 1256 3880 14000 4008
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||||
rect 1256 3600 13920 3880
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||||
rect 1256 3472 14000 3600
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||||
rect 1256 3192 13920 3472
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||||
rect 1256 3064 14000 3192
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||||
rect 1256 2784 13920 3064
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||||
rect 1256 2656 14000 2784
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||||
rect 1256 2376 13920 2656
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||||
rect 1256 2248 14000 2376
|
||||
rect 1256 1968 13920 2248
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||||
rect 1256 1840 14000 1968
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||||
rect 1256 1560 13920 1840
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||||
rect 1256 1432 14000 1560
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||||
rect 1256 1152 13920 1432
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||||
rect 1256 1024 14000 1152
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||||
rect 1256 744 13920 1024
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||||
rect 1256 616 14000 744
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rect 1256 443 13920 616
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<< metal4 >>
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rect 2560 1088 2880 11472
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rect 3560 1088 3880 11424
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@ -271,11 +279,11 @@ port 46 nsew ground input
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rlabel metal3 s 14000 416 34000 536 6 zero
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port 47 nsew signal output
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<< properties >>
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string LEFclass BLOCK
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string FIXED_BBOX 0 0 34000 13000
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string LEFclass BLOCK
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string LEFview TRUE
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string GDS_FILE ../gds/gpio_control_block.gds
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string GDS_END 640944
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string GDS_START 169022
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string GDS_END 564466
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string GDS_FILE /home/kareem_farid/fresh/caravel_timing/openlane/gpio_control_block/runs/gpio_control_block/results/finishing/gpio_control_block.magic.gds
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string GDS_START 191192
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<< end >>
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@ -1,31 +1,110 @@
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create_clock [get_ports {"serial_clock"} ] -name "serial_clock" -period $::env(CLOCK_PERIOD)
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create_clock [get_ports {"serial_load"} ] -name "serial_load" -period $::env(CLOCK_PERIOD)
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###############################################################################
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# Created by write_sdc
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# Thu Mar 17 11:21:00 2022
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###############################################################################
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current_design gpio_control_block
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###############################################################################
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# Timing Constraints
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###############################################################################
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create_clock -name serial_clock -period 50.0000 [get_ports {serial_clock}]
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set_clock_transition 0.1500 [get_clocks {serial_clock}]
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set_clock_uncertainty 0.2500 serial_clock
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set_propagated_clock [get_clocks {serial_clock}]
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create_clock -name serial_load -period 50.0000 [get_ports {serial_load}]
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set_clock_transition 0.1500 [get_clocks {serial_load}]
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set_clock_uncertainty 0.2500 serial_load
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set_propagated_clock [get_clocks {serial_load}]
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set input_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
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set output_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
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puts "\[INFO\]: Setting output delay to: $output_delay_value"
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puts "\[INFO\]: Setting input delay to: $input_delay_value"
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set_max_fanout $::env(SYNTH_MAX_FANOUT) [current_design]
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set_input_delay $input_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [all_inputs]
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set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [all_outputs]
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# TODO set this as parameter
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set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
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set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
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puts "\[INFO\]: Setting load to: $cap_load"
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set_load $cap_load [all_outputs]
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puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 10}] %"
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set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}]
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set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}]
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puts "\[INFO\]: Setting clock uncertainity to: $::env(SYNTH_CLOCK_UNCERTAINITY)"
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set_clock_uncertainty $::env(SYNTH_CLOCK_UNCERTAINITY) [get_clocks {serial_clock}]
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set_clock_uncertainty $::env(SYNTH_CLOCK_UNCERTAINITY) [get_clocks {serial_load}]
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puts "\[INFO\]: Setting clock transition to: $::env(SYNTH_CLOCK_TRANSITION)"
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set_clock_transition $::env(SYNTH_CLOCK_TRANSITION) [get_clocks {serial_clock}]
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set_clock_transition $::env(SYNTH_CLOCK_TRANSITION) [get_clocks {serial_load}]
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set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {gpio_defaults[0]}]
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set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {gpio_defaults[10]}]
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set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {gpio_defaults[11]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {gpio_defaults[12]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {gpio_defaults[1]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {gpio_defaults[2]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {gpio_defaults[3]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {gpio_defaults[4]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {gpio_defaults[5]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {gpio_defaults[6]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {gpio_defaults[7]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {gpio_defaults[8]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {gpio_defaults[9]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {mgmt_gpio_oeb}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {mgmt_gpio_out}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_in}]
|
||||
#set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {resetn}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {serial_data_in}]
|
||||
#set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {serial_load}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {user_gpio_oeb}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {user_gpio_out}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {mgmt_gpio_in}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {one}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_ana_en}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_ana_pol}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_ana_sel}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_dm[0]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_dm[1]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_dm[2]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_holdover}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_ib_mode_sel}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_inenb}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_out}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_outenb}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_slow_sel}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_vtrip_sel}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {resetn_out}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {serial_clock_out}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {serial_data_out}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {serial_load_out}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {user_gpio_in}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {zero}]
|
||||
###############################################################################
|
||||
# Environment
|
||||
###############################################################################
|
||||
set_load -pin_load 0.0334 [get_ports {mgmt_gpio_in}]
|
||||
set_load -pin_load 0.0334 [get_ports {one}]
|
||||
set_load -pin_load 0.0334 [get_ports {pad_gpio_ana_en}]
|
||||
set_load -pin_load 0.0334 [get_ports {pad_gpio_ana_pol}]
|
||||
set_load -pin_load 0.0334 [get_ports {pad_gpio_ana_sel}]
|
||||
set_load -pin_load 0.0334 [get_ports {pad_gpio_holdover}]
|
||||
set_load -pin_load 0.0334 [get_ports {pad_gpio_ib_mode_sel}]
|
||||
set_load -pin_load 0.0334 [get_ports {pad_gpio_inenb}]
|
||||
set_load -pin_load 0.0334 [get_ports {pad_gpio_out}]
|
||||
set_load -pin_load 0.0334 [get_ports {pad_gpio_outenb}]
|
||||
set_load -pin_load 0.0334 [get_ports {pad_gpio_slow_sel}]
|
||||
set_load -pin_load 0.0334 [get_ports {pad_gpio_vtrip_sel}]
|
||||
set_load -pin_load 0.0334 [get_ports {resetn_out}]
|
||||
set_load -pin_load 0.0334 [get_ports {serial_clock_out}]
|
||||
set_load -pin_load 0.0334 [get_ports {serial_data_out}]
|
||||
set_load -pin_load 0.0334 [get_ports {serial_load_out}]
|
||||
set_load -pin_load 0.0334 [get_ports {user_gpio_in}]
|
||||
set_load -pin_load 0.0334 [get_ports {zero}]
|
||||
set_load -pin_load 0.0334 [get_ports {pad_gpio_dm[2]}]
|
||||
set_load -pin_load 0.0334 [get_ports {pad_gpio_dm[1]}]
|
||||
set_load -pin_load 0.0334 [get_ports {pad_gpio_dm[0]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mgmt_gpio_oeb}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mgmt_gpio_out}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {pad_gpio_in}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {resetn}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {serial_clock}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {serial_data_in}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {serial_load}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {user_gpio_oeb}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {user_gpio_out}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[12]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[11]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[10]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[9]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[8]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[7]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[6]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[5]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[4]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[3]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[2]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[1]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[0]}]
|
||||
set_timing_derate -early 0.9500
|
||||
set_timing_derate -late 1.0500
|
||||
###############################################################################
|
||||
# Design Rules
|
||||
###############################################################################
|
||||
set_max_fanout 5.0000 [current_design]
|
||||
|
|
|
|||
|
|
@ -35,6 +35,7 @@ set ::env(BASE_SDC_FILE) $script_dir/base.sdc
|
|||
## Synthesis
|
||||
set ::env(SYNTH_READ_BLACKBOX_LIB) 1
|
||||
set ::env(SYNTH_USE_PG_PINS_DEFINES) "USE_POWER_PINS"
|
||||
set ::env(SYNTH_STRATEGY) "DELAY 0"
|
||||
|
||||
## Floorplan
|
||||
set ::env(FP_SIZING) absolute
|
||||
|
|
@ -59,8 +60,8 @@ set ::env(FP_PDN_AUTO_ADJUST) 0
|
|||
set ::env(FP_PDN_VWIDTH) 1.6
|
||||
set ::env(FP_PDN_HWIDTH) 1.6
|
||||
|
||||
set ::env(FP_HORIZONTAL_HALO) 2
|
||||
set ::env(FP_VERTICAL_HALO) 2
|
||||
set ::env(FP_PDN_HORIZONTAL_HALO) 2
|
||||
set ::env(FP_PDN_VERTICAL_HALO) 2
|
||||
|
||||
set ::env(FP_PDN_HOFFSET) 1.5
|
||||
set ::env(FP_PDN_VOFFSET) 9.0
|
||||
|
|
@ -72,7 +73,7 @@ set ::env(FP_PDN_VSPACING) 3.4
|
|||
set ::env(FP_PDN_HSPACING) 3.4
|
||||
|
||||
## Placement
|
||||
set ::env(PL_TARGET_DENSITY) 0.91
|
||||
set ::env(PL_TARGET_DENSITY) 0.7
|
||||
# for some reason resizer is leaving a floating net after running repair_tie_fanout command
|
||||
set ::env(PL_RESIZER_REPAIR_TIE_FANOUT) 0
|
||||
|
||||
|
|
@ -97,7 +98,10 @@ set ::env(GLB_RT_OBS) "\
|
|||
met1 120 0 170 65"
|
||||
|
||||
## Diode Insertion
|
||||
set ::env(DIODE_INSERTION_STRATEGY) "3"
|
||||
set ::env(DIODE_INSERTION_STRATEGY) 4
|
||||
|
||||
set ::env(FP_TAP_HORIZONTAL_HALO) {2}
|
||||
set ::env(FP_TAP_VERTICAL_HALO) {2}
|
||||
|
||||
## Internal macros
|
||||
set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro_placement.cfg
|
||||
|
|
@ -109,4 +113,19 @@ set ::env(EXTRA_LEFS) "\
|
|||
$script_dir/../../lef/gpio_logic_high.lef"
|
||||
|
||||
set ::env(EXTRA_GDS_FILES) "\
|
||||
$script_dir/../../gds/gpio_logic_high.gds"
|
||||
$script_dir/../../gds/gpio_logic_high.gds"
|
||||
|
||||
set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) 0
|
||||
|
||||
set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 0
|
||||
|
||||
set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 1
|
||||
# 0.07 ns 70 ps
|
||||
set ::env(PL_RESIZER_HOLD_SLACK_MARGIN) 0.05
|
||||
set ::env(PL_RESIZER_ALLOW_SETUP_VIOS) 1
|
||||
#set ::env(PL_RESIZER_HOLD_MAX_BUFFER_PERCENT) 2
|
||||
|
||||
set ::env(QUIT_ON_MAGIC_DRC) 0
|
||||
set ::env(QUIT_ON_LVS_ERROR) 0
|
||||
|
||||
set ::env(SYNTH_EXTRA_MAPPING_FILE) $script_dir/yosys_mapping.v
|
||||
|
|
|
|||
|
|
@ -84,4 +84,4 @@ calc_total_runtime
|
|||
save_state
|
||||
generate_final_summary_report
|
||||
|
||||
check_timing_violations
|
||||
check_timing_violations
|
||||
|
|
|
|||
|
|
@ -3,7 +3,6 @@
|
|||
if { ! [info exists ::env(VDD_NET)] } {
|
||||
set ::env(VDD_NET) $::env(VDD_PIN)
|
||||
}
|
||||
|
||||
if { ! [info exists ::env(GND_NET)] } {
|
||||
set ::env(GND_NET) $::env(GND_PIN)
|
||||
}
|
||||
|
|
@ -26,19 +25,28 @@ set_voltage_domain -name CORE -power $::env(VDD_NET) -ground $::env(GND_NET)
|
|||
|
||||
# Assesses whether the deisgn is the core of the chip or not based on the
|
||||
# value of $::env(DESIGN_IS_CORE) and uses the appropriate stdcell section
|
||||
if { $::env(VDD_NET) == "vccd1" } {
|
||||
# Used if the design is the core of the chip
|
||||
define_pdn_grid -name stdcell_grid -starts_with POWER -voltage_domain CORE -pins [subst {$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)}]
|
||||
add_pdn_stripe -grid stdcell_grid -layer $::env(FP_PDN_LOWER_LAYER) -width $::env(FP_PDN_VWIDTH) -pitch $::env(FP_PDN_VPITCH) -offset $::env(FP_PDN_VOFFSET) -starts_with POWER
|
||||
add_pdn_stripe -grid stdcell_grid -layer $::env(FP_PDN_UPPER_LAYER) -width $::env(FP_PDN_HWIDTH) -pitch $::env(FP_PDN_HPITCH) -offset $::env(FP_PDN_HOFFSET) -starts_with POWER
|
||||
add_pdn_connect -grid stdcell_grid -layers [subst {$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)}]
|
||||
} else {
|
||||
# Used if the design is the core of the chip
|
||||
define_pdn_grid -name stdcell_grid -starts_with POWER -voltage_domain CORE -pins [subst {$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)}]
|
||||
add_pdn_stripe -grid stdcell_grid -layer $::env(FP_PDN_LOWER_LAYER) -width $::env(FP_PDN_VWIDTH) -pitch $::env(FP_PDN_VPITCH) -offset $::env(FP_PDN_VOFFSET) -starts_with POWER
|
||||
add_pdn_stripe -grid stdcell_grid -layer $::env(FP_PDN_UPPER_LAYER) -width $::env(FP_PDN_HWIDTH) -pitch $::env(FP_PDN_HPITCH) -offset $::env(FP_PDN_HOFFSET) -starts_with POWER
|
||||
add_pdn_connect -grid stdcell_grid -layers [subst {$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)}]
|
||||
}
|
||||
define_pdn_grid \
|
||||
-name stdcell_grid \
|
||||
-starts_with POWER \
|
||||
-voltage_domain CORE \
|
||||
-pins [subst {$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)}]
|
||||
add_pdn_stripe \
|
||||
-grid stdcell_grid \
|
||||
-layer $::env(FP_PDN_LOWER_LAYER) \
|
||||
-width $::env(FP_PDN_VWIDTH) \
|
||||
-pitch $::env(FP_PDN_VPITCH) \
|
||||
-offset $::env(FP_PDN_VOFFSET) \
|
||||
-starts_with POWER
|
||||
add_pdn_stripe \
|
||||
-grid stdcell_grid \
|
||||
-layer $::env(FP_PDN_UPPER_LAYER) \
|
||||
-width $::env(FP_PDN_HWIDTH) \
|
||||
-pitch $::env(FP_PDN_HPITCH) \
|
||||
-offset $::env(FP_PDN_HOFFSET) \
|
||||
-starts_with POWER
|
||||
add_pdn_connect \
|
||||
-grid stdcell_grid \
|
||||
-layers [subst {$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)}]
|
||||
|
||||
# Adds the standard cell rails if enabled.
|
||||
if { $::env(FP_PDN_ENABLE_RAILS) == 1 } {
|
||||
|
|
@ -46,7 +54,6 @@ if { $::env(FP_PDN_ENABLE_RAILS) == 1 } {
|
|||
add_pdn_connect -grid stdcell_grid -layers [subst {$::env(FP_PDN_RAILS_LAYER) $::env(FP_PDN_LOWER_LAYER)}]
|
||||
}
|
||||
|
||||
|
||||
# Adds the core ring if enabled.
|
||||
if { $::env(FP_PDN_CORE_RING) == 1 } {
|
||||
add_pdn_ring -grid stdcell_grid -layer [subst {$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)}] \
|
||||
|
|
@ -56,28 +63,38 @@ if { $::env(FP_PDN_CORE_RING) == 1 } {
|
|||
}
|
||||
|
||||
if { $::env(VDD_NET) == "vccd1" } {
|
||||
set macro {
|
||||
orient {R0 R180 MX MY R90 R270 MXR90 MYR90}
|
||||
power_pins "vccd1"
|
||||
ground_pins "vssd1"
|
||||
blockages "met1 met2 met3 met4 met5"
|
||||
straps {
|
||||
}
|
||||
connect {{$::env(FP_PDN_LOWER_LAYER)_PIN_ver $::env(FP_PDN_UPPER_LAYER)}}
|
||||
}
|
||||
set ::halo [list $::env(FP_HORIZONTAL_HALO) $::env(FP_VERTICAL_HALO)]
|
||||
pdngen::specify_grid macro [subst $macro]
|
||||
add_global_connection -net vccd1 -inst_pattern gpio_logic_high -pin_pattern vccd1
|
||||
add_global_connection -net vssd1 -inst_pattern gpio_logic_high -pin_pattern vssd1
|
||||
define_pdn_grid \
|
||||
-macro \
|
||||
-orient {R0 R180 MX MY R90 R270 MXR90 MYR90}
|
||||
add_pdn_connect \
|
||||
-layers { met4_PIN_ver met5 }
|
||||
# set macro {
|
||||
# orient {R0 R180 MX MY R90 R270 MXR90 MYR90}
|
||||
# power_pins "vccd1"
|
||||
# ground_pins "vssd1"
|
||||
# blockages "met1 met2 met3 met4 met5"
|
||||
# straps {
|
||||
# }
|
||||
# connect {{$::env(FP_PDN_LOWER_LAYER)_PIN_ver $::env(FP_PDN_UPPER_LAYER)}}
|
||||
# }
|
||||
# pdngen::specify_grid macro [subst $macro]
|
||||
set ::halo [list $::env(FP_PDN_HORIZONTAL_HALO) $::env(FP_PDN_VERTICAL_HALO)]
|
||||
} else {
|
||||
set macro {
|
||||
orient {R0 R180 MX MY R90 R270 MXR90 MYR90}
|
||||
power_pins "vccd1"
|
||||
ground_pins "vssd1"
|
||||
blockages "met1 met2 met3 met4 met5"
|
||||
straps {
|
||||
}
|
||||
}
|
||||
set ::halo [list $::env(FP_HORIZONTAL_HALO) $::env(FP_VERTICAL_HALO)]
|
||||
pdngen::specify_grid macro [subst $macro]
|
||||
# set macro {
|
||||
# orient {R0 R180 MX MY R90 R270 MXR90 MYR90}
|
||||
# power_pins "vccd1"
|
||||
# ground_pins "vssd1"
|
||||
# blockages "met1 met2 met3 met4 met5"
|
||||
# straps {
|
||||
# }
|
||||
# }
|
||||
# pdngen::specify_grid macro [subst $macro]
|
||||
define_pdn_grid \
|
||||
-macro \
|
||||
-orient {R0 R180 MX MY R90 R270 MXR90 MYR90}
|
||||
set ::halo [list $::env(FP_PDN_HORIZONTAL_HALO) $::env(FP_PDN_VERTICAL_HALO)]
|
||||
}
|
||||
|
||||
# POWER or GROUND #Std. cell rails starting with power or ground rails at the bottom of the core area
|
||||
|
|
|
|||
|
|
@ -0,0 +1,22 @@
|
|||
|
||||
|
||||
|
||||
module \$_ALDFF_PN_ (D, C, L, AD, Q);
|
||||
input D, C, L, AD;
|
||||
output reg Q;
|
||||
|
||||
wire RN, SN;
|
||||
wire L_N;
|
||||
|
||||
\$_OR_ R_NAND ( .Y(RN), .A(L), .B(AD) );
|
||||
\$_NOT_ NAND_NOT ( .A(L), .Y(L_N));
|
||||
\$_NAND_ S_NAND ( .Y(SN), .A(L_N), .B(AD) );
|
||||
|
||||
\$_DFFSR_PNN_ SRFF (.C(C),
|
||||
.S(SN),
|
||||
.R(RN),
|
||||
.D(D),
|
||||
.Q(Q)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
###############################################################################
|
||||
# Created by write_sdc
|
||||
# Fri Dec 24 16:09:28 2021
|
||||
# Tue Apr 5 11:53:33 2022
|
||||
###############################################################################
|
||||
current_design gpio_control_block
|
||||
###############################################################################
|
||||
|
|
@ -30,9 +30,7 @@ set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports
|
|||
set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {mgmt_gpio_oeb}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {mgmt_gpio_out}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_in}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {resetn}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {serial_data_in}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {serial_load}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {user_gpio_oeb}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {user_gpio_out}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {mgmt_gpio_in}]
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -1 +1 @@
|
|||
openlane 2021.11.23_01.42.34-25-g8c734bc
|
||||
openlane 302609248b0947f2497a4684c503deca03ad0259
|
||||
|
|
|
|||
|
|
@ -1,3 +1,4 @@
|
|||
openlane 8c734bc051d0f302abd9a5437688f8dc75ffb32f
|
||||
openlane 00da77e58c86a2fa745dafc2f4b277191cb8d3ac
|
||||
magic 47df9da0d3dfe551b5b67e69cd346b040e7e079f
|
||||
skywater-pdk c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
|
||||
open_pdks 476f7428f7f686de51a5164c702629a9b9f2da46
|
||||
open_pdks 7519dfb04400f224f140749cda44ee7de6f5e095
|
||||
|
|
|
|||
|
|
@ -1,2 +1,2 @@
|
|||
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
|
||||
0,/home/ma/ef/caravel.latest/openlane/gpio_control_block,gpio_control_block,gpio_control_block,flow completed,0h1m36s0ms,0h1m26s0ms,23710.407239819004,0.01105,11855.203619909502,71.48,498.14,131,0,0,0,0,0,0,0,0,0,-1,-1,7257,1291,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,4013998.0,0.0,16.38,25.03,14.93,-1,18.49,81,109,48,76,0,0,0,66,2,13,0,13,0,0,0,4,24,44,4,38,28,0,66,20.0,50.0,50,AREA 0,5,50,1,25,16.9,0.91,0.05,sky130_fd_sc_hd,0,3
|
||||
0,/home/kareem_farid/fresh/caravel_timing/openlane/gpio_control_block,gpio_control_block,gpio_control_block,flow completed,0h1m34s0ms,0h1m22s0ms,-2.0,0.01105,-1,69.84,521.59,-1,0,0,0,0,0,0,0,0,0,-1,-1,4387,1001,0.0,0.0,-1,0.0,0.0,0.0,0.0,-1,0.0,0.0,4147542.0,0.0,12.18,14.64,14.41,-1,13.57,57,85,50,78,0,0,0,42,2,13,13,0,13,0,0,4,29,44,4,38,28,0,66,20.0,50.0,50,DELAY 0,5,50,1,25,16.9,0.7,0.05,sky130_fd_sc_hd,0,4
|
||||
|
|
|
|||
|
File diff suppressed because it is too large
Load Diff
|
|
@ -1,111 +1,123 @@
|
|||
* NGSPICE file created from gpio_control_block.ext - technology: sky130A
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__buf_1 abstract view
|
||||
.subckt sky130_fd_sc_hd__buf_1 A VGND VNB VPB VPWR X
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__clkbuf_1 abstract view
|
||||
.subckt sky130_fd_sc_hd__clkbuf_1 A VGND VNB VPB VPWR X
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__fill_2 abstract view
|
||||
.subckt sky130_fd_sc_hd__fill_2 VGND VNB VPB VPWR
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__diode_2 abstract view
|
||||
.subckt sky130_fd_sc_hd__diode_2 DIODE VGND VNB VPB VPWR
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__buf_2 abstract view
|
||||
.subckt sky130_fd_sc_hd__buf_2 A VGND VNB VPB VPWR X
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__or2b_1 abstract view
|
||||
.subckt sky130_fd_sc_hd__or2b_1 A B_N VGND VNB VPB VPWR X
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__or2_1 abstract view
|
||||
.subckt sky130_fd_sc_hd__or2_1 A B VGND VNB VPB VPWR X
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__dfrtp_2 abstract view
|
||||
.subckt sky130_fd_sc_hd__dfrtp_2 CLK D RESET_B VGND VNB VPB VPWR Q
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__fill_1 abstract view
|
||||
.subckt sky130_fd_sc_hd__fill_1 VGND VNB VPB VPWR
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__decap_4 abstract view
|
||||
.subckt sky130_fd_sc_hd__decap_4 VGND VNB VPB VPWR
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__diode_2 abstract view
|
||||
.subckt sky130_fd_sc_hd__diode_2 DIODE VGND VNB VPB VPWR
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__buf_1 abstract view
|
||||
.subckt sky130_fd_sc_hd__buf_1 A VGND VNB VPB VPWR X
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__clkdlybuf4s25_1 abstract view
|
||||
.subckt sky130_fd_sc_hd__clkdlybuf4s25_1 A VGND VNB VPB VPWR X
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__dlymetal6s2s_1 abstract view
|
||||
.subckt sky130_fd_sc_hd__dlymetal6s2s_1 A VGND VNB VPB VPWR X
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__inv_2 abstract view
|
||||
.subckt sky130_fd_sc_hd__inv_2 A VGND VNB VPB VPWR Y
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__decap_3 abstract view
|
||||
.subckt sky130_fd_sc_hd__decap_3 VGND VNB VPB VPWR
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__conb_1 abstract view
|
||||
.subckt sky130_fd_sc_hd__conb_1 VGND VNB VPB VPWR HI LO
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__dfbbn_1 abstract view
|
||||
.subckt sky130_fd_sc_hd__dfbbn_1 CLK_N D RESET_B SET_B VGND VNB VPB VPWR Q Q_N
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__dfrtp_1 abstract view
|
||||
.subckt sky130_fd_sc_hd__dfrtp_1 CLK D RESET_B VGND VNB VPB VPWR Q
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__einvp_8 abstract view
|
||||
.subckt sky130_fd_sc_hd__einvp_8 A TE VGND VNB VPB VPWR Z
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__tapvpwrvgnd_1 abstract view
|
||||
.subckt sky130_fd_sc_hd__tapvpwrvgnd_1 VGND VPWR
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__dfbbn_2 abstract view
|
||||
.subckt sky130_fd_sc_hd__dfbbn_2 CLK_N D RESET_B SET_B VGND VNB VPB VPWR Q Q_N
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__clkbuf_2 abstract view
|
||||
.subckt sky130_fd_sc_hd__clkbuf_2 A VGND VNB VPB VPWR X
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__inv_2 abstract view
|
||||
.subckt sky130_fd_sc_hd__inv_2 A VGND VNB VPB VPWR Y
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__or2_2 abstract view
|
||||
.subckt sky130_fd_sc_hd__or2_2 A B VGND VNB VPB VPWR X
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__and2_1 abstract view
|
||||
.subckt sky130_fd_sc_hd__and2_1 A B VGND VNB VPB VPWR X
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__decap_3 abstract view
|
||||
.subckt sky130_fd_sc_hd__decap_3 VGND VNB VPB VPWR
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__a31o_2 abstract view
|
||||
.subckt sky130_fd_sc_hd__a31o_2 A1 A2 A3 B1 VGND VNB VPB VPWR X
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__conb_1 abstract view
|
||||
.subckt sky130_fd_sc_hd__conb_1 VGND VNB VPB VPWR HI LO
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__and2b_2 abstract view
|
||||
.subckt sky130_fd_sc_hd__and2b_2 A_N B VGND VNB VPB VPWR X
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__or2b_2 abstract view
|
||||
.subckt sky130_fd_sc_hd__or2b_2 A B_N VGND VNB VPB VPWR X
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__decap_6 abstract view
|
||||
.subckt sky130_fd_sc_hd__decap_6 VGND VNB VPB VPWR
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__decap_8 abstract view
|
||||
.subckt sky130_fd_sc_hd__decap_8 VGND VNB VPB VPWR
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for gpio_logic_high abstract view
|
||||
.subckt gpio_logic_high gpio_logic1 vccd1 vssd1
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__buf_6 abstract view
|
||||
.subckt sky130_fd_sc_hd__buf_6 A VGND VNB VPB VPWR X
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__fill_2 abstract view
|
||||
.subckt sky130_fd_sc_hd__fill_2 VGND VNB VPB VPWR
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__clkbuf_16 abstract view
|
||||
.subckt sky130_fd_sc_hd__clkbuf_16 A VGND VNB VPB VPWR X
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__ebufn_8 abstract view
|
||||
.subckt sky130_fd_sc_hd__ebufn_8 A TE_B VGND VNB VPB VPWR Z
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__einvp_8 abstract view
|
||||
.subckt sky130_fd_sc_hd__einvp_8 A TE VGND VNB VPB VPWR Z
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__mux2_1 abstract view
|
||||
.subckt sky130_fd_sc_hd__mux2_1 A0 A1 S VGND VNB VPB VPWR X
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__decap_8 abstract view
|
||||
.subckt sky130_fd_sc_hd__decap_8 VGND VNB VPB VPWR
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__tapvpwrvgnd_1 abstract view
|
||||
.subckt sky130_fd_sc_hd__tapvpwrvgnd_1 VGND VPWR
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__ebufn_2 abstract view
|
||||
.subckt sky130_fd_sc_hd__ebufn_2 A TE_B VGND VNB VPB VPWR Z
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__buf_2 abstract view
|
||||
.subckt sky130_fd_sc_hd__buf_2 A VGND VNB VPB VPWR X
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__and2_2 abstract view
|
||||
.subckt sky130_fd_sc_hd__and2_2 A B VGND VNB VPB VPWR X
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__o22ai_2 abstract view
|
||||
.subckt sky130_fd_sc_hd__o22ai_2 A1 A2 B1 B2 VGND VNB VPB VPWR Y
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__o31ai_2 abstract view
|
||||
.subckt sky130_fd_sc_hd__o31ai_2 A1 A2 A3 B1 VGND VNB VPB VPWR Y
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__o21a_2 abstract view
|
||||
.subckt sky130_fd_sc_hd__o21a_2 A1 A2 B1 VGND VNB VPB VPWR X
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for gpio_logic_high abstract view
|
||||
.subckt gpio_logic_high gpio_logic1 vccd1 vssd1
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__nand2_2 abstract view
|
||||
.subckt sky130_fd_sc_hd__nand2_2 A B VGND VNB VPB VPWR Y
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__dlygate4sd2_1 abstract view
|
||||
.subckt sky130_fd_sc_hd__dlygate4sd2_1 A VGND VNB VPB VPWR X
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__clkdlybuf4s50_1 abstract view
|
||||
.subckt sky130_fd_sc_hd__clkdlybuf4s50_1 A VGND VNB VPB VPWR X
|
||||
.ends
|
||||
|
||||
.subckt gpio_control_block gpio_defaults[0] gpio_defaults[10] gpio_defaults[11] gpio_defaults[12]
|
||||
|
|
@ -116,340 +128,328 @@
|
|||
+ pad_gpio_in pad_gpio_inenb pad_gpio_out pad_gpio_outenb pad_gpio_slow_sel pad_gpio_vtrip_sel
|
||||
+ resetn resetn_out serial_clock serial_clock_out serial_data_in serial_data_out serial_load
|
||||
+ serial_load_out user_gpio_in user_gpio_oeb user_gpio_out vccd vccd1 vssd vssd1 zero
|
||||
X_200_ _200_/A vssd vssd vccd vccd _201_/A sky130_fd_sc_hd__buf_1
|
||||
X_131_ _131_/A vssd vssd vccd vccd _131_/X sky130_fd_sc_hd__clkbuf_1
|
||||
XFILLER_13_3 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
X_114_ _114_/A vssd vssd vccd vccd _114_/X sky130_fd_sc_hd__clkbuf_1
|
||||
XANTENNA_5 user_gpio_oeb vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
Xoutput31 _205_/X vssd vssd vccd vccd pad_gpio_outenb sky130_fd_sc_hd__buf_2
|
||||
X_130_ _136_/A _132_/B vssd vssd vccd vccd _131_/A sky130_fd_sc_hd__or2b_1
|
||||
X_113_ _187_/A _113_/B vssd vssd vccd vccd _114_/A sky130_fd_sc_hd__or2_1
|
||||
XFILLER_9_45 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XFILLER_0_58 vssd vssd vccd vccd sky130_fd_sc_hd__decap_4
|
||||
XFILLER_0_69 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
Xoutput32 _212_/Q vssd vssd vccd vccd pad_gpio_slow_sel sky130_fd_sc_hd__buf_2
|
||||
XANTENNA_6 user_gpio_out vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
Xoutput21 _220_/Q vssd vssd vccd vccd pad_gpio_ana_en sky130_fd_sc_hd__buf_2
|
||||
X_189_ _189_/A _189_/B vssd vssd vccd vccd _190_/A sky130_fd_sc_hd__or2_1
|
||||
Xhold10 _226_/D vssd vssd vccd vccd _211_/D sky130_fd_sc_hd__clkdlybuf4s25_1
|
||||
X_112_ _202_/A vssd vssd vccd vccd _187_/A sky130_fd_sc_hd__dlymetal6s2s_1
|
||||
XANTENNA_7 serial_data_in vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XFILLER_1_80 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
Xoutput33 _213_/Q vssd vssd vccd vccd pad_gpio_vtrip_sel sky130_fd_sc_hd__buf_2
|
||||
Xoutput22 _222_/Q vssd vssd vccd vccd pad_gpio_ana_pol sky130_fd_sc_hd__buf_2
|
||||
XFILLER_18_67 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
X_188_ _188_/A vssd vssd vccd vccd _188_/X sky130_fd_sc_hd__clkbuf_1
|
||||
X_111_ _111_/A vssd vssd vccd vccd _111_/X sky130_fd_sc_hd__clkbuf_1
|
||||
Xhold11 _224_/D vssd vssd vccd vccd _210_/D sky130_fd_sc_hd__clkdlybuf4s25_1
|
||||
Xoutput34 _202_/X vssd vssd vccd vccd resetn_out sky130_fd_sc_hd__buf_2
|
||||
Xoutput23 _221_/Q vssd vssd vccd vccd pad_gpio_ana_sel sky130_fd_sc_hd__buf_2
|
||||
X_187_ _187_/A _189_/A vssd vssd vccd vccd _188_/A sky130_fd_sc_hd__or2b_1
|
||||
XFILLER_4_92 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
XFILLER_18_57 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
X_110_ _136_/A _113_/B vssd vssd vccd vccd _111_/A sky130_fd_sc_hd__or2b_1
|
||||
Xhold12 _230_/D vssd vssd vccd vccd _221_/D sky130_fd_sc_hd__clkdlybuf4s25_1
|
||||
Xoutput24 _217_/Q vssd vssd vccd vccd pad_gpio_dm[0] sky130_fd_sc_hd__buf_2
|
||||
Xoutput35 _203_/X vssd vssd vccd vccd serial_clock_out sky130_fd_sc_hd__clkbuf_1
|
||||
X_186_ _186_/A vssd vssd vccd vccd _186_/X sky130_fd_sc_hd__buf_1
|
||||
X_169_ _169_/A _171_/B vssd vssd vccd vccd _170_/A sky130_fd_sc_hd__or2b_1
|
||||
Xhold13 _233_/D vssd vssd vccd vccd hold1/A sky130_fd_sc_hd__clkdlybuf4s25_1
|
||||
Xoutput36 _199_/X vssd vssd vccd vccd serial_data_out sky130_fd_sc_hd__buf_2
|
||||
Xoutput25 _218_/Q vssd vssd vccd vccd pad_gpio_dm[1] sky130_fd_sc_hd__buf_2
|
||||
X_200_ _207_/CLK _200_/D resetn vssd vssd vccd vccd _201_/D sky130_fd_sc_hd__dfrtp_2
|
||||
XFILLER_18_31 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XANTENNA__127__B_N gpio_defaults[8] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_114_ resetn vssd vssd vccd vccd _177_/A sky130_fd_sc_hd__buf_1
|
||||
XFILLER_13_3 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XFILLER_3_57 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_130_ _130_/A vssd vssd vccd vccd _130_/X sky130_fd_sc_hd__buf_1
|
||||
XANTENNA__124__B gpio_defaults[8] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XANTENNA__160__B_N gpio_defaults[11] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
Xhold20 hold20/A vssd vssd vccd vccd _190_/D sky130_fd_sc_hd__clkdlybuf4s25_1
|
||||
X_179__3 _179__3/A vssd vssd vccd vccd _179__3/Y sky130_fd_sc_hd__inv_2
|
||||
X_189_ _154__11/Y _189_/D _153_/X _156_/X vssd vssd vccd vccd pad_gpio_dm[0] _104_/A2
|
||||
+ sky130_fd_sc_hd__dfbbn_2
|
||||
XANTENNA__200__RESET_B resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
Xclkbuf_1_1_0__077_ clkbuf_0__077_/X vssd vssd vccd vccd _131__7/A sky130_fd_sc_hd__clkbuf_2
|
||||
X_112_ _210_/A vssd vssd vccd vccd _112_/X sky130_fd_sc_hd__buf_1
|
||||
Xhold10 _207_/D vssd vssd vccd vccd hold20/A sky130_fd_sc_hd__clkdlybuf4s25_1
|
||||
Xhold21 _203_/D vssd vssd vccd vccd _194_/D sky130_fd_sc_hd__clkdlybuf4s25_1
|
||||
XFILLER_3_26 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_111_ _111_/A vssd vssd vccd vccd _111_/X sky130_fd_sc_hd__buf_1
|
||||
XANTENNA__146__B gpio_defaults[1] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_188_ _148__10/Y _188_/D _147_/X _150_/X vssd vssd vccd vccd _188_/Q _188_/Q_N sky130_fd_sc_hd__dfbbn_2
|
||||
XFILLER_15_24 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
Xhold22 _202_/D vssd vssd vccd vccd _193_/D sky130_fd_sc_hd__clkdlybuf4s25_1
|
||||
XFILLER_6_26 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
Xhold11 hold1/X vssd vssd vccd vccd _187_/D sky130_fd_sc_hd__clkdlybuf4s25_1
|
||||
X_187_ _142__9/Y _187_/D _140_/X _145_/X vssd vssd vccd vccd pad_gpio_ib_mode_sel
|
||||
+ _187_/Q_N sky130_fd_sc_hd__dfbbn_2
|
||||
X_110_ _180_/A gpio_defaults[0] vssd vssd vccd vccd _111_/A sky130_fd_sc_hd__or2_2
|
||||
Xhold12 _200_/D vssd vssd vccd vccd hold1/A sky130_fd_sc_hd__clkdlybuf4s25_1
|
||||
Xhold23 _201_/D vssd vssd vccd vccd _192_/D sky130_fd_sc_hd__clkdlybuf4s25_1
|
||||
XFILLER_1_82 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XANTENNA__162__B gpio_defaults[12] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XFILLER_1_93 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XANTENNA__157__B gpio_defaults[11] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_186_ _136__8/Y _186_/D _135_/X _138_/X vssd vssd vccd vccd pad_gpio_inenb _186_/Q_N
|
||||
+ sky130_fd_sc_hd__dfbbn_2
|
||||
Xhold13 hold2/X vssd vssd vccd vccd _191_/D sky130_fd_sc_hd__clkdlybuf4s25_1
|
||||
XPHY_0 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
X_185_ _185_/A vssd vssd vccd vccd _186_/A sky130_fd_sc_hd__buf_1
|
||||
XANTENNA__203__RESET_B resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_185_ _131__7/Y _185_/D _130_/X _133_/X vssd vssd vccd vccd pad_gpio_vtrip_sel _185_/Q_N
|
||||
+ sky130_fd_sc_hd__dfbbn_2
|
||||
XANTENNA__196__RESET_B resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_099_ _188_/Q mgmt_gpio_oeb _182_/Q _098_/X vssd vssd vccd vccd pad_gpio_outenb sky130_fd_sc_hd__a31o_2
|
||||
Xhold14 hold4/X vssd vssd vccd vccd _188_/D sky130_fd_sc_hd__clkdlybuf4s25_1
|
||||
X_168_ _168_/A vssd vssd vccd vccd _168_/X sky130_fd_sc_hd__buf_1
|
||||
Xhold14 _231_/D vssd vssd vccd vccd _222_/D sky130_fd_sc_hd__clkdlybuf4s25_1
|
||||
XFILLER_1_62 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
XFILLER_1_73 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
XFILLER_15_49 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XPHY_1 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
Xoutput37 _204_/X vssd vssd vccd vccd serial_load_out sky130_fd_sc_hd__clkbuf_1
|
||||
Xoutput26 _219_/Q vssd vssd vccd vccd pad_gpio_dm[2] sky130_fd_sc_hd__buf_2
|
||||
XFILLER_18_49 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_184_ _184_/A vssd vssd vccd vccd _184_/X sky130_fd_sc_hd__clkbuf_1
|
||||
X_164__13 _164__13/A vssd vssd vccd vccd _164__13/Y sky130_fd_sc_hd__inv_2
|
||||
X_184_ _126__6/Y hold8/X _125_/X _128_/X vssd vssd vccd vccd pad_gpio_slow_sel _184_/Q_N
|
||||
+ sky130_fd_sc_hd__dfbbn_2
|
||||
XFILLER_18_27 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
Xconst_source vssd vssd vccd vccd one zero sky130_fd_sc_hd__conb_1
|
||||
X_167_ _173_/A vssd vssd vccd vccd _168_/A sky130_fd_sc_hd__buf_1
|
||||
Xhold15 _232_/D vssd vssd vccd vccd hold4/A sky130_fd_sc_hd__clkdlybuf4s25_1
|
||||
X_219_ _129_/X hold8/X _133_/X _131_/X vssd vssd vccd vccd _219_/Q _219_/Q_N sky130_fd_sc_hd__dfbbn_1
|
||||
XFILLER_1_30 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
Xoutput27 _211_/Q vssd vssd vccd vccd pad_gpio_holdover sky130_fd_sc_hd__buf_2
|
||||
X_098_ _182_/Q user_gpio_oeb vssd vssd vccd vccd _098_/X sky130_fd_sc_hd__and2b_2
|
||||
Xhold15 hold5/X vssd vssd vccd vccd _183_/D sky130_fd_sc_hd__clkdlybuf4s25_1
|
||||
X_167_ _172_/A gpio_defaults[5] vssd vssd vccd vccd _168_/A sky130_fd_sc_hd__or2_2
|
||||
XFILLER_16_93 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XPHY_2 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XFILLER_12_29 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
XFILLER_18_39 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
X_183_ _183_/A _183_/B vssd vssd vccd vccd _184_/A sky130_fd_sc_hd__or2_1
|
||||
X_166_ _166_/A vssd vssd vccd vccd _166_/X sky130_fd_sc_hd__clkbuf_1
|
||||
X_235_ _203_/A _235_/D _202_/A vssd vssd vccd vccd hold8/A sky130_fd_sc_hd__dfrtp_1
|
||||
XFILLER_1_53 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
Xoutput28 _215_/Q vssd vssd vccd vccd pad_gpio_ib_mode_sel sky130_fd_sc_hd__buf_2
|
||||
Xhold16 _228_/D vssd vssd vccd vccd hold2/A sky130_fd_sc_hd__clkdlybuf4s25_1
|
||||
X_149_ _149_/A vssd vssd vccd vccd _149_/X sky130_fd_sc_hd__buf_1
|
||||
X_218_ _135_/X hold5/X _139_/X _137_/X vssd vssd vccd vccd _218_/Q _218_/Q_N sky130_fd_sc_hd__dfbbn_1
|
||||
X_183_ _120__5/Y _183_/D _119_/X _122_/X vssd vssd vccd vccd pad_gpio_holdover _183_/Q_N
|
||||
+ sky130_fd_sc_hd__dfbbn_2
|
||||
X_166_ _166_/A vssd vssd vccd vccd _166_/X sky130_fd_sc_hd__buf_1
|
||||
X_097_ _097_/A vssd vssd vccd vccd _097_/X sky130_fd_sc_hd__buf_1
|
||||
Xhold16 hold6/X vssd vssd vccd vccd _182_/D sky130_fd_sc_hd__clkdlybuf4s25_1
|
||||
X_149_ _165_/A gpio_defaults[1] vssd vssd vccd vccd _150_/A sky130_fd_sc_hd__or2b_2
|
||||
XPHY_3 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XFILLER_18_29 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
X_182_ _182_/A vssd vssd vccd vccd _182_/X sky130_fd_sc_hd__clkbuf_1
|
||||
XFILLER_13_62 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
X_148_ _173_/A vssd vssd vccd vccd _149_/A sky130_fd_sc_hd__buf_1
|
||||
X_165_ _183_/A _165_/B vssd vssd vccd vccd _166_/A sky130_fd_sc_hd__or2_1
|
||||
X_217_ _141_/X hold6/X _146_/X _144_/X vssd vssd vccd vccd _217_/Q _206_/A0 sky130_fd_sc_hd__dfbbn_1
|
||||
X_234_ _203_/A _234_/D _202_/A vssd vssd vccd vccd _235_/D sky130_fd_sc_hd__dfrtp_1
|
||||
Xhold17 _234_/D vssd vssd vccd vccd hold6/A sky130_fd_sc_hd__clkdlybuf4s25_1
|
||||
Xoutput29 _214_/Q vssd vssd vccd vccd pad_gpio_inenb sky130_fd_sc_hd__buf_2
|
||||
XANTENNA__100__A user_gpio_out vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_182_ _113__4/Y _182_/D _111_/X _117_/X vssd vssd vccd vccd _182_/Q _182_/Q_N sky130_fd_sc_hd__dfbbn_2
|
||||
Xhold17 hold3/X vssd vssd vccd vccd _189_/D sky130_fd_sc_hd__clkdlybuf4s25_1
|
||||
X_096_ pad_gpio_inenb _188_/Q vssd vssd vccd vccd _097_/A sky130_fd_sc_hd__or2b_2
|
||||
X_165_ _165_/A gpio_defaults[12] vssd vssd vccd vccd _166_/A sky130_fd_sc_hd__or2b_2
|
||||
XANTENNA__206__RESET_B resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XPHY_4 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
X_181_ _187_/A _183_/B vssd vssd vccd vccd _182_/A sky130_fd_sc_hd__or2b_1
|
||||
X_164_ _164_/A vssd vssd vccd vccd _164_/X sky130_fd_sc_hd__clkbuf_1
|
||||
X_233_ _203_/A _233_/D _202_/A vssd vssd vccd vccd _234_/D sky130_fd_sc_hd__dfrtp_1
|
||||
XFILLER_18_3 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
Xhold18 _225_/D vssd vssd vccd vccd hold3/A sky130_fd_sc_hd__clkdlybuf4s25_1
|
||||
X_216_ _149_/X hold3/X _153_/X _151_/X vssd vssd vccd vccd _216_/Q _216_/Q_N sky130_fd_sc_hd__dfbbn_1
|
||||
X_147_ _147_/A vssd vssd vccd vccd _173_/A sky130_fd_sc_hd__buf_1
|
||||
XFILLER_16_85 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XANTENNA__199__RESET_B resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
Xclkbuf_1_1_0_serial_load clkbuf_0_serial_load/X vssd vssd vccd vccd _210_/A sky130_fd_sc_hd__clkbuf_2
|
||||
XANTENNA__195__D serial_data_in vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_181_ _181_/A vssd vssd vccd vccd _181_/X sky130_fd_sc_hd__buf_1
|
||||
XFILLER_18_3 vssd vssd vccd vccd sky130_fd_sc_hd__decap_6
|
||||
X_147_ _147_/A vssd vssd vccd vccd _147_/X sky130_fd_sc_hd__buf_1
|
||||
Xhold18 hold7/X vssd vssd vccd vccd _186_/D sky130_fd_sc_hd__clkdlybuf4s25_1
|
||||
XANTENNA__106__A pad_gpio_in vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XPHY_5 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
X_180_ _180_/A vssd vssd vccd vccd _180_/X sky130_fd_sc_hd__buf_1
|
||||
X_232_ _203_/A _232_/D _202_/A vssd vssd vccd vccd _233_/D sky130_fd_sc_hd__dfrtp_1
|
||||
X_163_ _169_/A _165_/B vssd vssd vccd vccd _164_/A sky130_fd_sc_hd__or2b_1
|
||||
Xhold19 _235_/D vssd vssd vccd vccd hold5/A sky130_fd_sc_hd__clkdlybuf4s25_1
|
||||
X_146_ _146_/A vssd vssd vccd vccd _146_/X sky130_fd_sc_hd__clkbuf_1
|
||||
XFILLER_7_88 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
X_215_ _155_/X hold2/X _160_/X _157_/X vssd vssd vccd vccd _215_/Q _215_/Q_N sky130_fd_sc_hd__dfbbn_1
|
||||
XANTENNA__114__A resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_180_ _180_/A gpio_defaults[7] vssd vssd vccd vccd _181_/A sky130_fd_sc_hd__or2b_2
|
||||
X_169__1 _179__3/A vssd vssd vccd vccd _169__1/Y sky130_fd_sc_hd__inv_2
|
||||
XANTENNA__109__A resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
Xhold19 hold9/X vssd vssd vccd vccd _185_/D sky130_fd_sc_hd__clkdlybuf4s25_1
|
||||
X_163_ _163_/A vssd vssd vccd vccd _163_/X sky130_fd_sc_hd__buf_1
|
||||
XANTENNA__149__B_N gpio_defaults[1] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XFILLER_1_34 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
XFILLER_1_78 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_129_ _146_/A gpio_defaults[9] vssd vssd vccd vccd _130_/A sky130_fd_sc_hd__or2_2
|
||||
Xclkbuf_0__077_ _112_/X vssd vssd vccd vccd clkbuf_0__077_/X sky130_fd_sc_hd__clkbuf_16
|
||||
Xclkbuf_1_0_0__077_ clkbuf_0__077_/X vssd vssd vccd vccd _136__8/A sky130_fd_sc_hd__clkbuf_2
|
||||
X_146_ _146_/A gpio_defaults[1] vssd vssd vccd vccd _147_/A sky130_fd_sc_hd__or2_2
|
||||
XPHY_6 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
X_129_ _129_/A vssd vssd vccd vccd _129_/X sky130_fd_sc_hd__buf_1
|
||||
XFILLER_16_75 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_231_ _231_/CLK _231_/D _202_/A vssd vssd vccd vccd _232_/D sky130_fd_sc_hd__dfrtp_1
|
||||
X_162_ _162_/A vssd vssd vccd vccd _162_/X sky130_fd_sc_hd__buf_1
|
||||
XFILLER_8_3 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
X_145_ _152_/A _145_/B vssd vssd vccd vccd _146_/A sky130_fd_sc_hd__or2_1
|
||||
X_214_ _162_/X hold7/X _166_/X _164_/X vssd vssd vccd vccd _214_/Q _214_/Q_N sky130_fd_sc_hd__dfbbn_1
|
||||
Xinput1 gpio_defaults[0] vssd vssd vccd vccd _189_/A sky130_fd_sc_hd__clkbuf_1
|
||||
XFILLER_1_35 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
X_174__2 _179__3/A vssd vssd vccd vccd _174__2/Y sky130_fd_sc_hd__inv_2
|
||||
X_162_ _172_/A gpio_defaults[12] vssd vssd vccd vccd _163_/A sky130_fd_sc_hd__or2_2
|
||||
X_145_ _145_/A vssd vssd vccd vccd _145_/X sky130_fd_sc_hd__buf_1
|
||||
XANTENNA__116__B_N gpio_defaults[0] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_128_ _128_/A vssd vssd vccd vccd _128_/X sky130_fd_sc_hd__buf_1
|
||||
XFILLER_7_78 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XPHY_7 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
X_128_ _140_/A vssd vssd vccd vccd _129_/A sky130_fd_sc_hd__buf_1
|
||||
XFILLER_4_46 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
X_161_ _173_/A vssd vssd vccd vccd _162_/A sky130_fd_sc_hd__buf_1
|
||||
X_230_ _231_/CLK _230_/D _202_/A vssd vssd vccd vccd _231_/D sky130_fd_sc_hd__dfrtp_1
|
||||
Xinput2 gpio_defaults[10] vssd vssd vccd vccd _145_/B sky130_fd_sc_hd__clkbuf_1
|
||||
XFILLER_1_58 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
Xgpio_in_buf _197_/Y gpio_in_buf/TE vssd vssd vccd vccd user_gpio_in sky130_fd_sc_hd__einvp_8
|
||||
X_144_ _144_/A vssd vssd vccd vccd _144_/X sky130_fd_sc_hd__clkbuf_1
|
||||
XFILLER_16_3 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
X_213_ _168_/X hold1/X _172_/X _170_/X vssd vssd vccd vccd _213_/Q _213_/Q_N sky130_fd_sc_hd__dfbbn_1
|
||||
X_161_ _161_/A vssd vssd vccd vccd _161_/X sky130_fd_sc_hd__buf_1
|
||||
Xgpio_in_buf _106_/Y gpio_in_buf/TE vssd vssd vccd vccd user_gpio_in sky130_fd_sc_hd__einvp_8
|
||||
XANTENNA_clkbuf_0_serial_load_A serial_load vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_127_ _137_/A gpio_defaults[8] vssd vssd vccd vccd _128_/A sky130_fd_sc_hd__or2b_2
|
||||
XFILLER_16_3 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_144_ _165_/A gpio_defaults[4] vssd vssd vccd vccd _145_/A sky130_fd_sc_hd__or2b_2
|
||||
XPHY_8 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
X_127_ _127_/A vssd vssd vccd vccd _127_/X sky130_fd_sc_hd__clkbuf_1
|
||||
X_212_ _174_/X hold4/X _178_/X _176_/X vssd vssd vccd vccd _212_/Q _212_/Q_N sky130_fd_sc_hd__dfbbn_1
|
||||
X_143_ _169_/A _145_/B vssd vssd vccd vccd _144_/A sky130_fd_sc_hd__or2b_1
|
||||
X_160_ _160_/A vssd vssd vccd vccd _160_/X sky130_fd_sc_hd__clkbuf_1
|
||||
XFILLER_1_26 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
Xinput3 gpio_defaults[11] vssd vssd vccd vccd _138_/B sky130_fd_sc_hd__clkbuf_1
|
||||
X_143_ _177_/A vssd vssd vccd vccd _165_/A sky130_fd_sc_hd__buf_1
|
||||
X_136__8 _136__8/A vssd vssd vccd vccd _136__8/Y sky130_fd_sc_hd__inv_2
|
||||
X_160_ _165_/A gpio_defaults[11] vssd vssd vccd vccd _161_/A sky130_fd_sc_hd__or2b_2
|
||||
XFILLER_1_26 vssd vssd vccd vccd sky130_fd_sc_hd__decap_8
|
||||
XPHY_9 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
X_126_ _152_/A _126_/B vssd vssd vccd vccd _127_/A sky130_fd_sc_hd__or2_1
|
||||
X_109_ _189_/B vssd vssd vccd vccd _136_/A sky130_fd_sc_hd__dlymetal6s2s_1
|
||||
XANTENNA__139__B gpio_defaults[4] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_109_ resetn vssd vssd vccd vccd _180_/A sky130_fd_sc_hd__buf_1
|
||||
XTAP_60 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
Xinput4 gpio_defaults[12] vssd vssd vccd vccd _132_/B sky130_fd_sc_hd__clkbuf_1
|
||||
X_211_ _180_/X _211_/D _184_/X _182_/X vssd vssd vccd vccd _211_/Q _211_/Q_N sky130_fd_sc_hd__dfbbn_1
|
||||
X_125_ _189_/B vssd vssd vccd vccd _152_/A sky130_fd_sc_hd__dlymetal6s2s_1
|
||||
X_142_ _189_/B vssd vssd vccd vccd _169_/A sky130_fd_sc_hd__dlymetal6s2s_1
|
||||
XFILLER_7_26 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XFILLER_2_70 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_108_ _202_/A vssd vssd vccd vccd _189_/B sky130_fd_sc_hd__clkbuf_1
|
||||
XFILLER_13_36 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
XANTENNA__152__B gpio_defaults[10] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_125_ _125_/A vssd vssd vccd vccd _125_/X sky130_fd_sc_hd__buf_1
|
||||
X_211_ pad_gpio_in _097_/X vssd vssd vccd vccd mgmt_gpio_in sky130_fd_sc_hd__ebufn_2
|
||||
X_108_ _108_/A vssd vssd vccd vccd serial_data_out sky130_fd_sc_hd__buf_1
|
||||
X_154__11 _142__9/A vssd vssd vccd vccd _154__11/Y sky130_fd_sc_hd__inv_2
|
||||
XFILLER_13_69 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XANTENNA__175__B_N gpio_defaults[6] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_210_ _210_/A vssd vssd vccd vccd serial_load_out sky130_fd_sc_hd__buf_2
|
||||
XTAP_61 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
X_210_ _186_/X _210_/D _190_/X _188_/X vssd vssd vccd vccd _210_/Q _210_/Q_N sky130_fd_sc_hd__dfbbn_1
|
||||
X_141_ _141_/A vssd vssd vccd vccd _141_/X sky130_fd_sc_hd__buf_1
|
||||
XTAP_50 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XFILLER_10_37 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
Xinput5 gpio_defaults[1] vssd vssd vccd vccd _152_/B sky130_fd_sc_hd__clkbuf_1
|
||||
XFILLER_1_39 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
Xclkbuf_1_1_0_serial_clock clkbuf_0_serial_clock/X vssd vssd vccd vccd _203_/A sky130_fd_sc_hd__clkbuf_2
|
||||
X_124_ _124_/A vssd vssd vccd vccd _124_/X sky130_fd_sc_hd__clkbuf_1
|
||||
X_115__1 serial_load vssd vssd vccd vccd _200_/A sky130_fd_sc_hd__inv_2
|
||||
X_141_ _210_/A vssd vssd vccd vccd _141_/X sky130_fd_sc_hd__buf_1
|
||||
X_124_ _146_/A gpio_defaults[8] vssd vssd vccd vccd _125_/A sky130_fd_sc_hd__or2_2
|
||||
Xclkbuf_1_1_0_serial_clock clkbuf_0_serial_clock/X vssd vssd vccd vccd _209_/A sky130_fd_sc_hd__clkbuf_2
|
||||
XANTENNA__202__RESET_B resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XANTENNA__195__RESET_B resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XFILLER_14_3 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_107_ one _107_/B vssd vssd vccd vccd _108_/A sky130_fd_sc_hd__and2_2
|
||||
XANTENNA__165__B_N gpio_defaults[12] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XTAP_62 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
X_140_ _140_/A vssd vssd vccd vccd _140_/X sky130_fd_sc_hd__buf_1
|
||||
XFILLER_10_27 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XTAP_51 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
X_140_ _140_/A vssd vssd vccd vccd _141_/A sky130_fd_sc_hd__buf_1
|
||||
Xinput6 gpio_defaults[2] vssd vssd vccd vccd _183_/B sky130_fd_sc_hd__clkbuf_1
|
||||
XFILLER_2_50 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XTAP_40 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XFILLER_16_37 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
XFILLER_8_82 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
Xinput20 user_gpio_out vssd vssd vccd vccd _208_/A0 sky130_fd_sc_hd__clkbuf_1
|
||||
X_123_ _136_/A _126_/B vssd vssd vccd vccd _124_/A sky130_fd_sc_hd__or2b_1
|
||||
X_123_ _177_/A vssd vssd vccd vccd _146_/A sky130_fd_sc_hd__buf_1
|
||||
X_106_ pad_gpio_in vssd vssd vccd vccd _106_/Y sky130_fd_sc_hd__inv_2
|
||||
X_148__10 _142__9/A vssd vssd vccd vccd _148__10/Y sky130_fd_sc_hd__inv_2
|
||||
XANTENNA__177__B gpio_defaults[7] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XANTENNA__132__B_N gpio_defaults[9] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XTAP_63 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
X_115__2 serial_load vssd vssd vccd vccd _185_/A sky130_fd_sc_hd__inv_2
|
||||
XTAP_52 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
Xinput7 gpio_defaults[3] vssd vssd vccd vccd _165_/B sky130_fd_sc_hd__clkbuf_1
|
||||
XTAP_41 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XFILLER_11_93 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_199_ _199_/A vssd vssd vccd vccd _199_/X sky130_fd_sc_hd__clkbuf_1
|
||||
Xinput10 gpio_defaults[6] vssd vssd vccd vccd _119_/B sky130_fd_sc_hd__clkbuf_1
|
||||
XANTENNA__155__B_N gpio_defaults[10] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XFILLER_16_27 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XFILLER_11_60 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_122_ _122_/A vssd vssd vccd vccd _122_/X sky130_fd_sc_hd__buf_1
|
||||
X_115__3 serial_load vssd vssd vccd vccd _179_/A sky130_fd_sc_hd__inv_2
|
||||
X_199_ _207_/CLK hold7/A resetn vssd vssd vccd vccd _200_/D sky130_fd_sc_hd__dfrtp_2
|
||||
X_105_ _182_/Q _100_/Y _103_/X _104_/Y vssd vssd vccd vccd pad_gpio_out sky130_fd_sc_hd__o22ai_2
|
||||
XTAP_64 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XFILLER_14_93 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XTAP_53 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
X_198_ one hold8/A vssd vssd vccd vccd _199_/A sky130_fd_sc_hd__and2_1
|
||||
X_198_ _209_/A hold5/A resetn vssd vssd vccd vccd hold7/A sky130_fd_sc_hd__dfrtp_2
|
||||
XTAP_42 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
Xinput8 gpio_defaults[4] vssd vssd vccd vccd _159_/B sky130_fd_sc_hd__clkbuf_1
|
||||
XFILLER_2_41 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
Xinput11 gpio_defaults[7] vssd vssd vccd vccd _113_/B sky130_fd_sc_hd__clkbuf_1
|
||||
X_121_ _140_/A vssd vssd vccd vccd _122_/A sky130_fd_sc_hd__buf_1
|
||||
XANTENNA__098__B user_gpio_oeb vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_121_ _137_/A gpio_defaults[2] vssd vssd vccd vccd _122_/A sky130_fd_sc_hd__or2b_2
|
||||
X_104_ pad_gpio_dm[2] _104_/A2 _101_/Y _182_/Q vssd vssd vccd vccd _104_/Y sky130_fd_sc_hd__o31ai_2
|
||||
XFILLER_12_3 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XTAP_65 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XANTENNA__205__RESET_B resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XTAP_54 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
X_115__4 serial_load vssd vssd vccd vccd _147_/A sky130_fd_sc_hd__inv_2
|
||||
Xinput9 gpio_defaults[5] vssd vssd vccd vccd _126_/B sky130_fd_sc_hd__clkbuf_1
|
||||
XTAP_43 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
Xinput12 gpio_defaults[8] vssd vssd vccd vccd _177_/B sky130_fd_sc_hd__clkbuf_1
|
||||
X_120_ _120_/A vssd vssd vccd vccd _120_/X sky130_fd_sc_hd__clkbuf_1
|
||||
X_197_ _209_/A vssd vssd vccd vccd _197_/Y sky130_fd_sc_hd__inv_2
|
||||
XFILLER_2_75 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_197_ _209_/A hold4/A resetn vssd vssd vccd vccd hold5/A sky130_fd_sc_hd__dfrtp_2
|
||||
XANTENNA__198__RESET_B resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_103_ pad_gpio_dm[2] _101_/Y _102_/Y vssd vssd vccd vccd _103_/X sky130_fd_sc_hd__o21a_2
|
||||
X_120__5 _136__8/A vssd vssd vccd vccd _120__5/Y sky130_fd_sc_hd__inv_2
|
||||
Xhold1 hold1/A vssd vssd vccd vccd hold1/X sky130_fd_sc_hd__clkdlybuf4s25_1
|
||||
X_115__5 serial_load vssd vssd vccd vccd _116_/A sky130_fd_sc_hd__inv_2
|
||||
XTAP_55 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
X_196_ _196_/A vssd vssd vccd vccd _206_/S sky130_fd_sc_hd__clkbuf_1
|
||||
X_196_ _209_/A hold6/A resetn vssd vssd vccd vccd hold4/A sky130_fd_sc_hd__dfrtp_2
|
||||
XANTENNA__101__A mgmt_gpio_oeb vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XTAP_44 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XFILLER_2_32 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
X_179_ _179_/A vssd vssd vccd vccd _180_/A sky130_fd_sc_hd__buf_1
|
||||
Xinput13 gpio_defaults[9] vssd vssd vccd vccd _171_/B sky130_fd_sc_hd__clkbuf_1
|
||||
X_102_ mgmt_gpio_out vssd vssd vccd vccd _102_/Y sky130_fd_sc_hd__inv_2
|
||||
Xclkbuf_0_serial_load serial_load vssd vssd vccd vccd clkbuf_0_serial_load/X sky130_fd_sc_hd__clkbuf_16
|
||||
Xhold2 hold2/A vssd vssd vccd vccd hold2/X sky130_fd_sc_hd__clkdlybuf4s25_1
|
||||
XTAP_56 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XTAP_45 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
Xgpio_logic_high gpio_in_buf/TE vccd1 vssd1 gpio_logic_high
|
||||
X_195_ _219_/Q _218_/Q vssd vssd vccd vccd _196_/A sky130_fd_sc_hd__or2b_1
|
||||
Xinput14 mgmt_gpio_oeb vssd vssd vccd vccd _207_/S sky130_fd_sc_hd__clkbuf_1
|
||||
XFILLER_2_55 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_178_ _178_/A vssd vssd vccd vccd _178_/X sky130_fd_sc_hd__clkbuf_1
|
||||
X_195_ _209_/A serial_data_in resetn vssd vssd vccd vccd hold6/A sky130_fd_sc_hd__dfrtp_2
|
||||
X_101_ mgmt_gpio_oeb pad_gpio_dm[1] vssd vssd vccd vccd _101_/Y sky130_fd_sc_hd__nand2_2
|
||||
X_178_ _178_/A vssd vssd vccd vccd _178_/X sky130_fd_sc_hd__buf_1
|
||||
Xhold3 hold3/A vssd vssd vccd vccd hold3/X sky130_fd_sc_hd__clkdlybuf4s25_1
|
||||
XFILLER_10_3 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
Xclkbuf_1_1_0__049_ clkbuf_0__049_/X vssd vssd vccd vccd _142__9/A sky130_fd_sc_hd__clkbuf_2
|
||||
Xclkbuf_1_0_0_serial_load clkbuf_0_serial_load/X vssd vssd vccd vccd _179__3/A sky130_fd_sc_hd__clkbuf_2
|
||||
XFILLER_10_3 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_126__6 _131__7/A vssd vssd vccd vccd _126__6/Y sky130_fd_sc_hd__inv_2
|
||||
XFILLER_14_42 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XTAP_57 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XPHY_30 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XTAP_46 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
X_194_ _194_/A vssd vssd vccd vccd _194_/X sky130_fd_sc_hd__clkbuf_1
|
||||
X_177_ _183_/A _177_/B vssd vssd vccd vccd _178_/A sky130_fd_sc_hd__or2_1
|
||||
Xinput15 mgmt_gpio_out vssd vssd vccd vccd _207_/A0 sky130_fd_sc_hd__clkbuf_1
|
||||
X_194_ _179__3/Y _194_/D _178_/X _181_/X vssd vssd vccd vccd pad_gpio_ana_pol _194_/Q_N
|
||||
+ sky130_fd_sc_hd__dfbbn_2
|
||||
X_100_ user_gpio_out vssd vssd vccd vccd _100_/Y sky130_fd_sc_hd__inv_2
|
||||
XANTENNA__208__A resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_177_ _177_/A gpio_defaults[7] vssd vssd vccd vccd _178_/A sky130_fd_sc_hd__or2_2
|
||||
Xhold4 hold4/A vssd vssd vccd vccd hold4/X sky130_fd_sc_hd__clkdlybuf4s25_1
|
||||
XFILLER_8_55 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_229_ _231_/CLK hold9/A _202_/A vssd vssd vccd vccd _230_/D sky130_fd_sc_hd__dfrtp_1
|
||||
X_131__7 _131__7/A vssd vssd vccd vccd _131__7/Y sky130_fd_sc_hd__inv_2
|
||||
XTAP_58 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XFILLER_14_43 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XTAP_47 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XPHY_31 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
X_193_ _216_/Q _207_/S vssd vssd vccd vccd _194_/A sky130_fd_sc_hd__and2_1
|
||||
XPHY_20 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XFILLER_2_46 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_176_ _176_/A vssd vssd vccd vccd _176_/X sky130_fd_sc_hd__clkbuf_1
|
||||
X_159_ _183_/A _159_/B vssd vssd vccd vccd _160_/A sky130_fd_sc_hd__or2_1
|
||||
X_228_ _231_/CLK _228_/D _202_/A vssd vssd vccd vccd hold9/A sky130_fd_sc_hd__dfrtp_1
|
||||
Xinput16 pad_gpio_in vssd vssd vccd vccd _209_/A sky130_fd_sc_hd__clkbuf_1
|
||||
X_193_ _174__2/Y _193_/D _173_/X _176_/X vssd vssd vccd vccd pad_gpio_ana_sel _193_/Q_N
|
||||
+ sky130_fd_sc_hd__dfbbn_2
|
||||
XANTENNA__118__B gpio_defaults[2] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_176_ _176_/A vssd vssd vccd vccd _176_/X sky130_fd_sc_hd__buf_1
|
||||
Xhold5 hold5/A vssd vssd vccd vccd hold5/X sky130_fd_sc_hd__clkdlybuf4s25_1
|
||||
Xdata_delay_1 hold2/A vssd vssd vccd vccd data_delay_2/A sky130_fd_sc_hd__dlygate4sd2_1
|
||||
XPHY_32 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XTAP_59 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XPHY_21 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XTAP_48 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
X_192_ _192_/A vssd vssd vccd vccd _192_/X sky130_fd_sc_hd__clkbuf_1
|
||||
XPHY_10 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
Xinput17 resetn vssd vssd vccd vccd _202_/A sky130_fd_sc_hd__buf_6
|
||||
X_175_ _187_/A _177_/B vssd vssd vccd vccd _176_/A sky130_fd_sc_hd__or2b_1
|
||||
XFILLER_3_90 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XFILLER_2_36 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
XFILLER_17_55 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_158_ _189_/B vssd vssd vccd vccd _183_/A sky130_fd_sc_hd__clkbuf_1
|
||||
XFILLER_17_11 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_192_ _169__1/Y _192_/D _168_/X _171_/X vssd vssd vccd vccd pad_gpio_ana_en _192_/Q_N
|
||||
+ sky130_fd_sc_hd__dfbbn_2
|
||||
X_175_ _180_/A gpio_defaults[6] vssd vssd vccd vccd _176_/A sky130_fd_sc_hd__or2b_2
|
||||
XFILLER_2_47 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XANTENNA__129__B gpio_defaults[9] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XANTENNA__134__B gpio_defaults[3] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
Xhold6 hold6/A vssd vssd vccd vccd hold6/X sky130_fd_sc_hd__clkdlybuf4s25_1
|
||||
X_227_ _231_/CLK hold7/A _202_/A vssd vssd vccd vccd _228_/D sky130_fd_sc_hd__dfrtp_1
|
||||
Xclkbuf_1_0_0_serial_clock clkbuf_0_serial_clock/X vssd vssd vccd vccd _231_/CLK sky130_fd_sc_hd__clkbuf_2
|
||||
X_158_ _158_/A vssd vssd vccd vccd _158_/X sky130_fd_sc_hd__buf_1
|
||||
XTAP_49 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XTAP_38 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XFILLER_0_80 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
Xclkbuf_1_0_0_serial_clock clkbuf_0_serial_clock/X vssd vssd vccd vccd _207_/CLK sky130_fd_sc_hd__clkbuf_2
|
||||
Xdata_delay_2 data_delay_2/A vssd vssd vccd vccd _107_/B sky130_fd_sc_hd__dlygate4sd2_1
|
||||
XPHY_33 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XFILLER_11_57 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
Xclkbuf_0_serial_clock serial_clock vssd vssd vccd vccd clkbuf_0_serial_clock/X sky130_fd_sc_hd__clkbuf_16
|
||||
XFILLER_11_24 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XPHY_22 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
X_191_ _214_/Q _216_/Q vssd vssd vccd vccd _192_/A sky130_fd_sc_hd__or2b_1
|
||||
Xclkbuf_0_serial_clock serial_clock vssd vssd vccd vccd clkbuf_0_serial_clock/X sky130_fd_sc_hd__clkbuf_16
|
||||
X_191_ _164__13/Y _191_/D _163_/X _166_/X vssd vssd vccd vccd pad_gpio_dm[2] _191_/Q_N
|
||||
+ sky130_fd_sc_hd__dfbbn_2
|
||||
XPHY_11 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
X_174_ _174_/A vssd vssd vccd vccd _174_/X sky130_fd_sc_hd__buf_1
|
||||
X_226_ _231_/CLK _226_/D _202_/A vssd vssd vccd vccd hold7/A sky130_fd_sc_hd__dfrtp_1
|
||||
X_157_ _157_/A vssd vssd vccd vccd _157_/X sky130_fd_sc_hd__clkbuf_1
|
||||
XFILLER_3_80 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
Xinput18 serial_data_in vssd vssd vccd vccd _223_/D sky130_fd_sc_hd__clkbuf_1
|
||||
X_157_ _172_/A gpio_defaults[11] vssd vssd vccd vccd _158_/A sky130_fd_sc_hd__or2_2
|
||||
X_209_ _209_/A vssd vssd vccd vccd serial_clock_out sky130_fd_sc_hd__buf_2
|
||||
Xhold7 hold7/A vssd vssd vccd vccd hold7/X sky130_fd_sc_hd__clkdlybuf4s25_1
|
||||
X_209_ _209_/A _192_/X vssd vssd vccd vccd mgmt_gpio_in sky130_fd_sc_hd__ebufn_8
|
||||
XFILLER_5_26 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
XFILLER_14_24 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XPHY_12 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XFILLER_5_26 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_142__9 _142__9/A vssd vssd vccd vccd _142__9/Y sky130_fd_sc_hd__inv_2
|
||||
XANTENNA__201__RESET_B resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XTAP_39 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
X_173_ _173_/A vssd vssd vccd vccd _174_/A sky130_fd_sc_hd__buf_1
|
||||
XPHY_12 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XPHY_34 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XPHY_23 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
X_190_ _190_/A vssd vssd vccd vccd _190_/X sky130_fd_sc_hd__clkbuf_1
|
||||
Xinput19 user_gpio_oeb vssd vssd vccd vccd _205_/A0 sky130_fd_sc_hd__clkbuf_1
|
||||
XFILLER_17_57 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_225_ _231_/CLK _225_/D _202_/A vssd vssd vccd vccd _226_/D sky130_fd_sc_hd__dfrtp_1
|
||||
X_156_ _169_/A _159_/B vssd vssd vccd vccd _157_/A sky130_fd_sc_hd__or2b_1
|
||||
Xhold8 hold8/A vssd vssd vccd vccd hold8/X sky130_fd_sc_hd__clkdlybuf4s25_1
|
||||
XFILLER_3_70 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_208_ _208_/A0 _207_/X _210_/Q vssd vssd vccd vccd _208_/X sky130_fd_sc_hd__mux2_1
|
||||
XFILLER_0_93 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_139_ _139_/A vssd vssd vccd vccd _139_/X sky130_fd_sc_hd__clkbuf_1
|
||||
X_190_ _159__12/Y _190_/D _158_/X _161_/X vssd vssd vccd vccd pad_gpio_dm[1] _190_/Q_N
|
||||
+ sky130_fd_sc_hd__dfbbn_2
|
||||
X_173_ _173_/A vssd vssd vccd vccd _173_/X sky130_fd_sc_hd__buf_1
|
||||
X_156_ _156_/A vssd vssd vccd vccd _156_/X sky130_fd_sc_hd__buf_1
|
||||
XFILLER_8_37 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
Xhold8 hold8/A vssd vssd vccd vccd hold8/X sky130_fd_sc_hd__clkdlybuf4s50_1
|
||||
X_208_ resetn vssd vssd vccd vccd resetn_out sky130_fd_sc_hd__buf_2
|
||||
X_139_ _146_/A gpio_defaults[4] vssd vssd vccd vccd _140_/A sky130_fd_sc_hd__or2_2
|
||||
XPHY_35 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XPHY_24 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XPHY_13 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
X_172_ _172_/A vssd vssd vccd vccd _172_/X sky130_fd_sc_hd__clkbuf_1
|
||||
X_224_ _231_/CLK _224_/D _202_/A vssd vssd vccd vccd _225_/D sky130_fd_sc_hd__dfrtp_1
|
||||
X_155_ _155_/A vssd vssd vccd vccd _155_/X sky130_fd_sc_hd__buf_1
|
||||
X_207_ _207_/A0 _206_/X _207_/S vssd vssd vccd vccd _207_/X sky130_fd_sc_hd__mux2_1
|
||||
X_138_ _152_/A _138_/B vssd vssd vccd vccd _139_/A sky130_fd_sc_hd__or2_1
|
||||
XFILLER_0_50 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XFILLER_9_3 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_155_ _165_/A gpio_defaults[10] vssd vssd vccd vccd _156_/A sky130_fd_sc_hd__or2b_2
|
||||
X_172_ _172_/A gpio_defaults[6] vssd vssd vccd vccd _173_/A sky130_fd_sc_hd__or2_2
|
||||
XFILLER_3_93 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_138_ _138_/A vssd vssd vccd vccd _138_/X sky130_fd_sc_hd__buf_1
|
||||
Xhold9 hold9/A vssd vssd vccd vccd hold9/X sky130_fd_sc_hd__clkdlybuf4s25_1
|
||||
X_171_ _183_/A _171_/B vssd vssd vccd vccd _172_/A sky130_fd_sc_hd__or2_1
|
||||
XFILLER_0_72 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_207_ _207_/CLK _207_/D resetn vssd vssd vccd vccd hold2/A sky130_fd_sc_hd__dfrtp_2
|
||||
XANTENNA__172__B gpio_defaults[6] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XANTENNA__167__B gpio_defaults[5] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XPHY_36 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XPHY_25 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
X_171_ _171_/A vssd vssd vccd vccd _171_/X sky130_fd_sc_hd__buf_1
|
||||
XPHY_14 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
X_223_ _203_/A _223_/D _202_/A vssd vssd vccd vccd _224_/D sky130_fd_sc_hd__dfrtp_1
|
||||
X_154_ _173_/A vssd vssd vccd vccd _155_/A sky130_fd_sc_hd__buf_1
|
||||
X_206_ _206_/A0 _207_/A0 _206_/S vssd vssd vccd vccd _206_/X sky130_fd_sc_hd__mux2_1
|
||||
XFILLER_0_73 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
X_137_ _137_/A vssd vssd vccd vccd _137_/X sky130_fd_sc_hd__clkbuf_1
|
||||
XFILLER_18_80 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_137_ _137_/A gpio_defaults[3] vssd vssd vccd vccd _138_/A sky130_fd_sc_hd__or2b_2
|
||||
XFILLER_17_3 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XANTENNA__096__A pad_gpio_inenb vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_206_ _209_/A hold3/A resetn vssd vssd vccd vccd _207_/D sky130_fd_sc_hd__dfrtp_2
|
||||
XPHY_37 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XPHY_26 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XPHY_15 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
X_170_ _170_/A vssd vssd vccd vccd _170_/X sky130_fd_sc_hd__clkbuf_1
|
||||
X_153_ _153_/A vssd vssd vccd vccd _153_/X sky130_fd_sc_hd__clkbuf_1
|
||||
X_205_ _205_/A0 _194_/X _210_/Q vssd vssd vccd vccd _205_/X sky130_fd_sc_hd__mux2_1
|
||||
X_222_ _201_/X _222_/D _114_/X _111_/X vssd vssd vccd vccd _222_/Q _222_/Q_N sky130_fd_sc_hd__dfbbn_1
|
||||
X_136_ _136_/A _138_/B vssd vssd vccd vccd _137_/A sky130_fd_sc_hd__or2b_1
|
||||
X_119_ _187_/A _119_/B vssd vssd vccd vccd _120_/A sky130_fd_sc_hd__or2_1
|
||||
XANTENNA__121__B_N gpio_defaults[2] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_170_ _180_/A gpio_defaults[5] vssd vssd vccd vccd _171_/A sky130_fd_sc_hd__or2b_2
|
||||
XANTENNA__204__RESET_B resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XFILLER_12_93 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_205_ _209_/A hold9/A resetn vssd vssd vccd vccd hold3/A sky130_fd_sc_hd__dfrtp_2
|
||||
X_153_ _153_/A vssd vssd vccd vccd _153_/X sky130_fd_sc_hd__buf_1
|
||||
XANTENNA__144__B_N gpio_defaults[4] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_119_ _119_/A vssd vssd vccd vccd _119_/X sky130_fd_sc_hd__buf_1
|
||||
XANTENNA__197__RESET_B resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XFILLER_15_93 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XPHY_27 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XPHY_16 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XANTENNA_0 mgmt_gpio_oeb vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_152_ _152_/A _152_/B vssd vssd vccd vccd _153_/A sky130_fd_sc_hd__or2_1
|
||||
X_221_ _140_/A _221_/D _120_/X _118_/X vssd vssd vccd vccd _221_/Q _221_/Q_N sky130_fd_sc_hd__dfbbn_1
|
||||
X_204_ serial_load vssd vssd vccd vccd _204_/X sky130_fd_sc_hd__buf_2
|
||||
X_118_ _118_/A vssd vssd vccd vccd _118_/X sky130_fd_sc_hd__clkbuf_1
|
||||
X_113__4 _136__8/A vssd vssd vccd vccd _113__4/Y sky130_fd_sc_hd__inv_2
|
||||
X_152_ _172_/A gpio_defaults[10] vssd vssd vccd vccd _153_/A sky130_fd_sc_hd__or2_2
|
||||
X_135_ _135_/A vssd vssd vccd vccd _135_/X sky130_fd_sc_hd__buf_1
|
||||
X_204_ _209_/A hold8/A resetn vssd vssd vccd vccd hold9/A sky130_fd_sc_hd__dfrtp_2
|
||||
X_118_ _180_/A gpio_defaults[2] vssd vssd vccd vccd _119_/A sky130_fd_sc_hd__or2_2
|
||||
XPHY_28 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XPHY_17 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XFILLER_6_52 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XANTENNA_1 mgmt_gpio_out vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XFILLER_3_86 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
X_203_ _203_/A vssd vssd vccd vccd _203_/X sky130_fd_sc_hd__buf_2
|
||||
X_151_ _151_/A vssd vssd vccd vccd _151_/X sky130_fd_sc_hd__clkbuf_1
|
||||
X_134_ _140_/A vssd vssd vccd vccd _135_/A sky130_fd_sc_hd__buf_1
|
||||
X_220_ _122_/X hold9/X _127_/X _124_/X vssd vssd vccd vccd _220_/Q _220_/Q_N sky130_fd_sc_hd__dfbbn_1
|
||||
XFILLER_0_65 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
X_117_ _136_/A _119_/B vssd vssd vccd vccd _118_/A sky130_fd_sc_hd__or2b_1
|
||||
Xclkbuf_0__049_ _141_/X vssd vssd vccd vccd clkbuf_0__049_/X sky130_fd_sc_hd__clkbuf_16
|
||||
Xclkbuf_1_0_0__049_ clkbuf_0__049_/X vssd vssd vccd vccd _164__13/A sky130_fd_sc_hd__clkbuf_2
|
||||
X_134_ _146_/A gpio_defaults[3] vssd vssd vccd vccd _135_/A sky130_fd_sc_hd__or2_2
|
||||
X_203_ _207_/CLK _203_/D resetn vssd vssd vccd vccd hold8/A sky130_fd_sc_hd__dfrtp_2
|
||||
X_151_ _177_/A vssd vssd vccd vccd _172_/A sky130_fd_sc_hd__buf_1
|
||||
XFILLER_18_61 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
X_117_ _117_/A vssd vssd vccd vccd _117_/X sky130_fd_sc_hd__buf_1
|
||||
XPHY_29 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XFILLER_15_73 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XPHY_18 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XANTENNA_2 one vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_150_ _169_/A _152_/B vssd vssd vccd vccd _151_/A sky130_fd_sc_hd__or2b_1
|
||||
X_133_ _133_/A vssd vssd vccd vccd _133_/X sky130_fd_sc_hd__clkbuf_1
|
||||
X_202_ _202_/A vssd vssd vccd vccd _202_/X sky130_fd_sc_hd__clkbuf_1
|
||||
XFILLER_0_77 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
XANTENNA__102__A mgmt_gpio_out vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_150_ _150_/A vssd vssd vccd vccd _150_/X sky130_fd_sc_hd__buf_1
|
||||
X_159__12 _164__13/A vssd vssd vccd vccd _159__12/Y sky130_fd_sc_hd__inv_2
|
||||
X_133_ _133_/A vssd vssd vccd vccd _133_/X sky130_fd_sc_hd__buf_1
|
||||
X_202_ _207_/CLK _202_/D resetn vssd vssd vccd vccd _203_/D sky130_fd_sc_hd__dfrtp_2
|
||||
X_116_ _137_/A gpio_defaults[0] vssd vssd vccd vccd _117_/A sky130_fd_sc_hd__or2b_2
|
||||
XPHY_19 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
X_116_ _116_/A vssd vssd vccd vccd _140_/A sky130_fd_sc_hd__buf_1
|
||||
XANTENNA_3 one vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XFILLER_3_55 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_132_ _152_/A _132_/B vssd vssd vccd vccd _133_/A sky130_fd_sc_hd__or2_1
|
||||
X_201_ _201_/A vssd vssd vccd vccd _201_/X sky130_fd_sc_hd__buf_1
|
||||
XFILLER_18_85 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
Xoutput30 _208_/X vssd vssd vccd vccd pad_gpio_out sky130_fd_sc_hd__buf_2
|
||||
XANTENNA_4 pad_gpio_in vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XANTENNA__180__B_N gpio_defaults[7] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XANTENNA__207__RESET_B resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XANTENNA_clkbuf_0_serial_clock_A serial_clock vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XANTENNA__137__B_N gpio_defaults[3] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_132_ _137_/A gpio_defaults[9] vssd vssd vccd vccd _133_/A sky130_fd_sc_hd__or2b_2
|
||||
XANTENNA__099__A2 mgmt_gpio_oeb vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_201_ _207_/CLK _201_/D resetn vssd vssd vccd vccd _202_/D sky130_fd_sc_hd__dfrtp_2
|
||||
XANTENNA__110__B gpio_defaults[0] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_115_ _177_/A vssd vssd vccd vccd _137_/A sky130_fd_sc_hd__buf_1
|
||||
XANTENNA__211__A pad_gpio_in vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XANTENNA__170__B_N gpio_defaults[5] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
.ends
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue