mirror of https://github.com/efabless/caravel.git
[DATA] Update caravel_clocking
This commit is contained in:
manarabdelaty
parent
07db7f0599
commit
ef1019b62a
11439
def/caravel_clocking.def
11439
def/caravel_clocking.def
File diff suppressed because it is too large
Load Diff
Binary file not shown.
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@ -12,31 +12,31 @@ MACRO caravel_clocking
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USE GROUND ;
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PORT
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LAYER met5 ;
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RECT 1.840 24.060 94.300 25.660 ;
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RECT 0.000 24.060 94.300 25.660 ;
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END
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PORT
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LAYER met5 ;
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RECT 1.840 40.960 94.300 42.560 ;
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RECT 0.000 40.960 94.300 42.560 ;
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END
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PORT
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LAYER met4 ;
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RECT 25.110 -0.240 26.710 54.640 ;
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RECT 23.270 -0.240 24.870 54.640 ;
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END
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PORT
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LAYER met4 ;
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RECT 40.610 -0.240 42.210 54.640 ;
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RECT 38.770 -0.240 40.370 54.640 ;
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END
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PORT
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LAYER met4 ;
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RECT 56.110 -0.240 57.710 54.640 ;
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RECT 54.270 -0.240 55.870 54.640 ;
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END
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PORT
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LAYER met4 ;
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RECT 71.610 -0.240 73.210 54.640 ;
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RECT 69.770 -0.240 71.370 54.640 ;
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END
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PORT
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LAYER met4 ;
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RECT 87.110 -0.240 88.710 54.640 ;
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RECT 85.270 -0.240 86.870 54.640 ;
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END
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END VGND
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PIN VPWR
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@ -44,35 +44,35 @@ MACRO caravel_clocking
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USE POWER ;
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PORT
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LAYER met5 ;
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RECT 1.840 15.610 94.300 17.210 ;
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RECT 0.000 15.610 94.300 17.210 ;
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END
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PORT
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LAYER met5 ;
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RECT 1.840 32.510 94.300 34.110 ;
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RECT 0.000 32.510 94.300 34.110 ;
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END
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PORT
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LAYER met5 ;
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RECT 1.840 49.410 94.300 51.010 ;
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RECT 0.000 49.410 94.300 51.010 ;
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END
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PORT
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LAYER met4 ;
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RECT 17.360 -0.240 18.960 54.640 ;
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RECT 15.520 -0.240 17.120 54.640 ;
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END
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PORT
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LAYER met4 ;
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RECT 32.860 -0.240 34.460 54.640 ;
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RECT 31.020 -0.240 32.620 54.640 ;
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END
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PORT
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LAYER met4 ;
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RECT 48.360 -0.240 49.960 54.640 ;
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RECT 46.520 -0.240 48.120 54.640 ;
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END
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PORT
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LAYER met4 ;
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RECT 63.860 -0.240 65.460 54.640 ;
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RECT 62.020 -0.240 63.620 54.640 ;
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END
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PORT
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LAYER met4 ;
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RECT 79.360 -0.240 80.960 54.640 ;
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RECT 77.520 -0.240 79.120 54.640 ;
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END
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END VPWR
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PIN core_clk
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@ -196,55 +196,61 @@ MACRO caravel_clocking
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END
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END user_clk
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OBS
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LAYER nwell ;
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RECT -0.190 50.265 94.490 53.095 ;
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RECT -0.190 44.825 94.490 47.655 ;
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RECT -0.190 39.385 94.490 42.215 ;
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RECT -0.190 33.945 94.490 36.775 ;
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RECT -0.190 28.505 94.490 31.335 ;
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RECT -0.190 23.065 94.490 25.895 ;
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RECT -0.190 17.625 94.490 20.455 ;
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RECT -0.190 12.185 94.490 15.015 ;
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RECT -0.190 6.745 94.490 9.575 ;
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RECT -0.190 1.305 94.490 4.135 ;
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LAYER pwell ;
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RECT 1.985 -0.085 2.155 0.085 ;
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RECT 3.365 -0.085 3.535 0.085 ;
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RECT 7.055 -0.050 7.215 0.060 ;
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RECT 8.425 -0.085 8.595 0.085 ;
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RECT 14.405 -0.085 14.575 0.085 ;
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RECT 20.385 -0.085 20.555 0.085 ;
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RECT 24.060 -0.055 24.180 0.055 ;
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RECT 25.450 -0.085 25.620 0.085 ;
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RECT 26.360 -0.055 26.480 0.055 ;
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RECT 27.285 -0.085 27.455 0.085 ;
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RECT 27.755 -0.050 27.915 0.060 ;
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RECT 30.040 -0.085 30.210 0.085 ;
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RECT 30.505 -0.085 30.675 0.085 ;
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RECT 32.350 -0.085 32.520 0.085 ;
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RECT 34.185 -0.085 34.355 0.085 ;
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RECT 38.335 -0.050 38.495 0.060 ;
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RECT 39.245 -0.085 39.415 0.085 ;
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RECT 42.465 -0.085 42.635 0.085 ;
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RECT 44.305 -0.085 44.475 0.085 ;
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RECT 47.525 -0.085 47.695 0.085 ;
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RECT 49.360 -0.055 49.480 0.055 ;
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RECT 0.145 -0.085 0.315 0.085 ;
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RECT 1.525 -0.085 1.695 0.085 ;
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RECT 5.215 -0.050 5.375 0.060 ;
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RECT 6.585 -0.085 6.755 0.085 ;
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RECT 12.565 -0.085 12.735 0.085 ;
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RECT 16.700 -0.085 16.870 0.085 ;
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RECT 17.175 -0.050 17.335 0.060 ;
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RECT 19.470 -0.085 19.640 0.085 ;
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RECT 19.925 -0.085 20.095 0.085 ;
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RECT 23.600 -0.055 23.720 0.055 ;
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RECT 24.525 -0.085 24.695 0.085 ;
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RECT 26.365 -0.085 26.535 0.085 ;
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RECT 29.580 -0.055 29.700 0.055 ;
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RECT 30.780 -0.085 30.950 0.085 ;
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RECT 34.645 -0.085 34.815 0.085 ;
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RECT 36.485 -0.085 36.655 0.085 ;
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RECT 45.685 -0.085 45.855 0.085 ;
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RECT 46.145 -0.085 46.315 0.085 ;
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RECT 48.445 -0.085 48.615 0.085 ;
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RECT 50.285 -0.085 50.455 0.085 ;
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RECT 56.265 -0.085 56.435 0.085 ;
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RECT 62.245 -0.085 62.415 0.085 ;
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RECT 65.460 -0.055 65.580 0.055 ;
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RECT 66.840 -0.085 67.010 0.085 ;
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RECT 67.300 -0.055 67.420 0.055 ;
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RECT 68.225 -0.085 68.395 0.085 ;
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RECT 74.200 -0.055 74.320 0.055 ;
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RECT 75.125 -0.085 75.295 0.085 ;
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RECT 53.500 -0.055 53.620 0.055 ;
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RECT 54.425 -0.085 54.595 0.085 ;
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RECT 60.400 -0.055 60.520 0.055 ;
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RECT 60.865 -0.085 61.035 0.085 ;
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RECT 64.545 -0.085 64.715 0.085 ;
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RECT 66.385 -0.085 66.555 0.085 ;
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RECT 72.375 -0.050 72.535 0.060 ;
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RECT 75.585 -0.085 75.755 0.085 ;
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RECT 79.260 -0.055 79.380 0.055 ;
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RECT 80.185 -0.085 80.355 0.085 ;
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RECT 86.165 -0.085 86.335 0.085 ;
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RECT 89.395 -0.050 89.555 0.060 ;
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RECT 91.225 -0.085 91.395 0.085 ;
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RECT 92.145 -0.085 92.315 0.085 ;
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RECT 76.045 -0.085 76.215 0.085 ;
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RECT 78.345 -0.085 78.515 0.085 ;
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RECT 84.325 -0.085 84.495 0.085 ;
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RECT 86.170 -0.085 86.340 0.085 ;
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RECT 88.935 -0.050 89.095 0.060 ;
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RECT 90.310 -0.085 90.480 0.085 ;
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RECT 93.985 -0.085 94.155 0.085 ;
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LAYER li1 ;
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RECT 1.065 0.085 94.300 54.485 ;
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RECT 1.065 0.000 1.840 0.085 ;
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RECT 0.000 0.085 94.300 54.485 ;
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LAYER li1 ;
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RECT 1.840 -0.085 94.300 0.085 ;
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RECT 0.000 -0.085 94.300 0.085 ;
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LAYER met1 ;
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RECT 1.005 0.000 94.300 54.640 ;
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RECT 1.840 -0.240 94.300 0.000 ;
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RECT 0.000 -0.240 94.300 54.640 ;
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LAYER met2 ;
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RECT 3.320 55.720 6.710 56.285 ;
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RECT 1.480 55.720 6.710 56.285 ;
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RECT 7.550 55.720 20.970 56.285 ;
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RECT 21.810 55.720 35.230 56.285 ;
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RECT 36.070 55.720 49.490 56.285 ;
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@ -252,34 +258,34 @@ MACRO caravel_clocking
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RECT 64.590 55.720 78.010 56.285 ;
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RECT 78.850 55.720 92.270 56.285 ;
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RECT 93.110 55.720 94.210 56.285 ;
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RECT 3.320 0.000 94.210 55.720 ;
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RECT 25.140 -0.240 26.680 0.000 ;
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RECT 40.640 -0.240 42.180 0.000 ;
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RECT 56.140 -0.240 57.680 0.000 ;
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RECT 71.640 -0.240 73.180 0.000 ;
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RECT 87.140 -0.240 88.680 0.000 ;
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RECT 1.480 0.000 94.210 55.720 ;
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RECT 23.300 -0.240 24.840 0.000 ;
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RECT 38.800 -0.240 40.340 0.000 ;
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RECT 54.300 -0.240 55.840 0.000 ;
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RECT 69.800 -0.240 71.340 0.000 ;
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RECT 85.300 -0.240 86.840 0.000 ;
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LAYER met3 ;
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RECT 12.485 55.400 95.600 56.265 ;
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RECT 12.485 49.320 96.000 55.400 ;
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RECT 12.485 47.920 95.600 49.320 ;
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RECT 12.485 41.840 96.000 47.920 ;
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RECT 12.485 40.440 95.600 41.840 ;
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RECT 12.485 34.360 96.000 40.440 ;
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RECT 12.485 32.960 95.600 34.360 ;
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RECT 12.485 26.880 96.000 32.960 ;
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RECT 12.485 25.480 95.600 26.880 ;
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RECT 12.485 19.400 96.000 25.480 ;
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RECT 12.485 18.000 95.600 19.400 ;
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RECT 12.485 11.920 96.000 18.000 ;
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RECT 12.485 10.520 95.600 11.920 ;
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RECT 12.485 4.440 96.000 10.520 ;
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RECT 12.485 3.040 95.600 4.440 ;
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RECT 12.485 0.000 96.000 3.040 ;
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RECT 25.110 -0.165 26.710 0.000 ;
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RECT 40.610 -0.165 42.210 0.000 ;
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RECT 56.110 -0.165 57.710 0.000 ;
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RECT 71.610 -0.165 73.210 0.000 ;
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RECT 87.110 -0.165 88.710 0.000 ;
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RECT 12.025 55.400 95.600 56.265 ;
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RECT 12.025 49.320 96.000 55.400 ;
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RECT 12.025 47.920 95.600 49.320 ;
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RECT 12.025 41.840 96.000 47.920 ;
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RECT 12.025 40.440 95.600 41.840 ;
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RECT 12.025 34.360 96.000 40.440 ;
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RECT 12.025 32.960 95.600 34.360 ;
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RECT 12.025 26.880 96.000 32.960 ;
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RECT 12.025 25.480 95.600 26.880 ;
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RECT 12.025 19.400 96.000 25.480 ;
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RECT 12.025 18.000 95.600 19.400 ;
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RECT 12.025 11.920 96.000 18.000 ;
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RECT 12.025 10.520 95.600 11.920 ;
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RECT 12.025 4.440 96.000 10.520 ;
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RECT 12.025 3.040 95.600 4.440 ;
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RECT 12.025 0.000 96.000 3.040 ;
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RECT 23.270 -0.165 24.870 0.000 ;
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RECT 38.770 -0.165 40.370 0.000 ;
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RECT 54.270 -0.165 55.870 0.000 ;
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RECT 69.770 -0.165 71.370 0.000 ;
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RECT 85.270 -0.165 86.870 0.000 ;
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END
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END caravel_clocking
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END LIBRARY
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47272
mag/caravel_clocking.mag
47272
mag/caravel_clocking.mag
File diff suppressed because it is too large
Load Diff
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@ -1,52 +1,58 @@
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magic
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tech sky130A
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magscale 1 2
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timestamp 1638470713
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timestamp 1638477074
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<< nwell >>
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rect -38 10053 18898 10619
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rect -38 8965 18898 9531
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rect -38 7877 18898 8443
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rect -38 6789 18898 7355
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rect -38 5701 18898 6267
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rect -38 4613 18898 5179
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rect -38 3525 18898 4091
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rect -38 2437 18898 3003
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rect -38 1349 18898 1915
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rect -38 261 18898 827
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<< pwell >>
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rect 397 -17 431 17
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rect 673 -17 707 17
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rect 1411 -10 1443 12
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rect 1685 -17 1719 17
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rect 2881 -17 2915 17
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rect 4077 -17 4111 17
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rect 17787 -10 17819 12
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rect 18062 -17 18096 17
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rect 18797 -17 18831 17
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<< obsli1 >>
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rect 213 0 18860 10897
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rect 368 -17 18860 0
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rect 0 -17 18860 10897
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<< obsm1 >>
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rect 201 0 18860 10928
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rect 368 -48 18860 0
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rect 0 -48 18860 10928
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<< metal2 >>
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rect 1398 11200 1454 12000
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rect 4250 11200 4306 12000
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@ -56,7 +62,7 @@ rect 12806 11200 12862 12000
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rect 15658 11200 15714 12000
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rect 18510 11200 18566 12000
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<< obsm2 >>
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rect 664 11144 1342 11257
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rect 4362 11144 7046 11257
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rect 17060 -48 17368 0
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<< metal3 >>
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rect 19200 11160 20000 11280
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rect 19200 9664 20000 9784
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rect 19200 2184 20000 2304
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rect 19200 688 20000 808
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<< obsm3 >>
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||||
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||||
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|
||||
rect 2405 888 19200 2104
|
||||
rect 2405 608 19120 888
|
||||
rect 2405 0 19200 608
|
||||
rect 4654 -33 4974 0
|
||||
rect 7754 -33 8074 0
|
||||
rect 10854 -33 11174 0
|
||||
rect 13954 -33 14274 0
|
||||
rect 17054 -33 17374 0
|
||||
<< metal4 >>
|
||||
rect 3472 -48 3792 10928
|
||||
rect 5022 -48 5342 10928
|
||||
rect 6572 -48 6892 10928
|
||||
rect 8122 -48 8442 10928
|
||||
rect 9672 -48 9992 10928
|
||||
rect 11222 -48 11542 10928
|
||||
rect 12772 -48 13092 10928
|
||||
rect 14322 -48 14642 10928
|
||||
rect 15872 -48 16192 10928
|
||||
rect 17422 -48 17742 10928
|
||||
rect 3104 -48 3424 10928
|
||||
rect 4654 -48 4974 10928
|
||||
rect 6204 -48 6524 10928
|
||||
rect 7754 -48 8074 10928
|
||||
rect 9304 -48 9624 10928
|
||||
rect 10854 -48 11174 10928
|
||||
rect 12404 -48 12724 10928
|
||||
rect 13954 -48 14274 10928
|
||||
rect 15504 -48 15824 10928
|
||||
rect 17054 -48 17374 10928
|
||||
<< metal5 >>
|
||||
rect 368 9882 18860 10202
|
||||
rect 368 8192 18860 8512
|
||||
rect 368 6502 18860 6822
|
||||
rect 368 4812 18860 5132
|
||||
rect 368 3122 18860 3442
|
||||
rect 0 9882 18860 10202
|
||||
rect 0 8192 18860 8512
|
||||
rect 0 6502 18860 6822
|
||||
rect 0 4812 18860 5132
|
||||
rect 0 3122 18860 3442
|
||||
<< labels >>
|
||||
rlabel metal5 s 368 4812 18860 5132 6 VGND
|
||||
rlabel metal5 s 0 4812 18860 5132 6 VGND
|
||||
port 1 nsew ground input
|
||||
rlabel metal5 s 368 8192 18860 8512 6 VGND
|
||||
rlabel metal5 s 0 8192 18860 8512 6 VGND
|
||||
port 1 nsew ground input
|
||||
rlabel metal4 s 5022 -48 5342 10928 6 VGND
|
||||
rlabel metal4 s 4654 -48 4974 10928 6 VGND
|
||||
port 1 nsew ground input
|
||||
rlabel metal4 s 8122 -48 8442 10928 6 VGND
|
||||
rlabel metal4 s 7754 -48 8074 10928 6 VGND
|
||||
port 1 nsew ground input
|
||||
rlabel metal4 s 11222 -48 11542 10928 6 VGND
|
||||
rlabel metal4 s 10854 -48 11174 10928 6 VGND
|
||||
port 1 nsew ground input
|
||||
rlabel metal4 s 14322 -48 14642 10928 6 VGND
|
||||
rlabel metal4 s 13954 -48 14274 10928 6 VGND
|
||||
port 1 nsew ground input
|
||||
rlabel metal4 s 17422 -48 17742 10928 6 VGND
|
||||
rlabel metal4 s 17054 -48 17374 10928 6 VGND
|
||||
port 1 nsew ground input
|
||||
rlabel metal5 s 368 3122 18860 3442 6 VPWR
|
||||
rlabel metal5 s 0 3122 18860 3442 6 VPWR
|
||||
port 2 nsew power input
|
||||
rlabel metal5 s 368 6502 18860 6822 6 VPWR
|
||||
rlabel metal5 s 0 6502 18860 6822 6 VPWR
|
||||
port 2 nsew power input
|
||||
rlabel metal5 s 368 9882 18860 10202 6 VPWR
|
||||
rlabel metal5 s 0 9882 18860 10202 6 VPWR
|
||||
port 2 nsew power input
|
||||
rlabel metal4 s 3472 -48 3792 10928 6 VPWR
|
||||
rlabel metal4 s 3104 -48 3424 10928 6 VPWR
|
||||
port 2 nsew power input
|
||||
rlabel metal4 s 6572 -48 6892 10928 6 VPWR
|
||||
rlabel metal4 s 6204 -48 6524 10928 6 VPWR
|
||||
port 2 nsew power input
|
||||
rlabel metal4 s 9672 -48 9992 10928 6 VPWR
|
||||
rlabel metal4 s 9304 -48 9624 10928 6 VPWR
|
||||
port 2 nsew power input
|
||||
rlabel metal4 s 12772 -48 13092 10928 6 VPWR
|
||||
rlabel metal4 s 12404 -48 12724 10928 6 VPWR
|
||||
port 2 nsew power input
|
||||
rlabel metal4 s 15872 -48 16192 10928 6 VPWR
|
||||
rlabel metal4 s 15504 -48 15824 10928 6 VPWR
|
||||
port 2 nsew power input
|
||||
rlabel metal2 s 7102 11200 7158 12000 6 core_clk
|
||||
port 3 nsew signal output
|
||||
|
|
@ -184,7 +190,7 @@ string LEFclass BLOCK
|
|||
string FIXED_BBOX 0 0 20000 12000
|
||||
string LEFview TRUE
|
||||
string GDS_FILE ../gds/caravel_clocking.gds
|
||||
string GDS_END 1177254
|
||||
string GDS_START 407686
|
||||
string GDS_END 1127518
|
||||
string GDS_START 370986
|
||||
<< end >>
|
||||
|
||||
|
|
|
|||
|
|
@ -5,20 +5,20 @@ create_clock [get_ports {"pll_clk90"} ] -name "pll_clk90" -period 6.66666666666
|
|||
|
||||
## GENERATED CLOCKS
|
||||
# divided PLL clocks
|
||||
create_generated_clock -name pll_clk_divided -source [get_ports pll_clk] -divide_by 2 [get_pins _351_/Y]
|
||||
create_generated_clock -name pll_clk90_divided -source [get_ports pll_clk90] -divide_by 2 [get_pins _354_/Y]
|
||||
create_generated_clock -name pll_clk_divided -source [get_ports pll_clk] -divide_by 2 [get_pins _357_/Y]
|
||||
create_generated_clock -name pll_clk90_divided -source [get_ports pll_clk90] -divide_by 2 [get_pins _360_/Y]
|
||||
|
||||
# assign core_ext_clk = (use_pll_first) ? ext_clk_syncd : ext_clk;
|
||||
create_generated_clock -name core_ext_clk -source [get_ports ext_clk] -divide_by 1 [get_pins _412_/X]
|
||||
create_generated_clock -name core_ext_clk_syncd -source [get_pins _426_/Q] -divide_by 1 [get_pins _412_/X]
|
||||
create_generated_clock -name core_ext_clk -source [get_ports ext_clk] -divide_by 1 [get_pins _418_/X]
|
||||
create_generated_clock -name core_ext_clk_syncd -source [get_pins _432_/Q] -divide_by 1 [get_pins _418_/X]
|
||||
|
||||
# assign core_clk = (use_pll_second) ? pll_clk_divided : core_ext_clk;
|
||||
create_generated_clock -name core_clk -source [get_pins _412_/X] -divide_by 1 [get_pins _393_/X]
|
||||
create_generated_clock -name core_clk_pll -source [get_pins _351_/Y] -divide_by 1 [get_pins _393_/X]
|
||||
create_generated_clock -name core_clk -source [get_pins _418_/X] -divide_by 1 [get_pins _399_/X]
|
||||
create_generated_clock -name core_clk_pll -source [get_pins _357_/Y] -divide_by 1 [get_pins _399_/X]
|
||||
|
||||
# assign user_clk = (use_pll_second) ? pll_clk90_divided : core_ext_clk;
|
||||
create_generated_clock -name user_clk -source [get_pins _412_/X] -divide_by 1 [get_pins _394_/X]
|
||||
create_generated_clock -name user_clk_pll -source [get_pins _354_/Y] -divide_by 1 [get_pins _394_/X]
|
||||
create_generated_clock -name user_clk -source [get_pins _418_/X] -divide_by 1 [get_pins _400_/X]
|
||||
create_generated_clock -name user_clk_pll -source [get_pins _360_/Y] -divide_by 1 [get_pins _400_/X]
|
||||
|
||||
# logically exclusive clocks, the generated pll clocks and the ext core clk
|
||||
set_clock_groups -logically_exclusive -group core_ext_clk -group core_ext_clk_syncd
|
||||
|
|
|
|||
|
|
@ -45,7 +45,7 @@ set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
|
|||
|
||||
set ::env(FP_TAPCELL_DIST) 6
|
||||
|
||||
set ::env(LEFT_MARGIN_MULT) 4
|
||||
set ::env(LEFT_MARGIN_MULT) 0
|
||||
set ::env(BOTTOM_MARGIN_MULT) 0
|
||||
set ::env(TOP_MARGIN_MULT) "2"
|
||||
|
||||
|
|
@ -56,7 +56,7 @@ set ::env(FP_PDN_HPITCH) 16.9
|
|||
set ::env(FP_PDN_VPITCH) 15.5
|
||||
|
||||
## Placement
|
||||
set ::env(PL_TARGET_DENSITY) 0.71
|
||||
set ::env(PL_TARGET_DENSITY) 0.70
|
||||
|
||||
set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 1
|
||||
set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 1
|
||||
|
|
@ -72,7 +72,7 @@ set ::env(GLB_RT_OBS) "\
|
|||
li1 0 54.64000 100.0 60,\
|
||||
li1 94.29500 0 100 60"
|
||||
|
||||
set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) 1
|
||||
set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) 0
|
||||
|
||||
## Diode Insertion
|
||||
set ::env(DIODE_INSERTION_STRATEGY) 4
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
###############################################################################
|
||||
# Created by write_sdc
|
||||
# Thu Dec 2 18:44:19 2021
|
||||
# Thu Dec 2 20:30:29 2021
|
||||
###############################################################################
|
||||
current_design caravel_clocking
|
||||
###############################################################################
|
||||
|
|
@ -18,15 +18,15 @@ create_clock -name pll_clk90 -period 6.6667 [get_ports {pll_clk90}]
|
|||
set_clock_transition 0.1500 [get_clocks {pll_clk90}]
|
||||
set_clock_uncertainty 0.2500 pll_clk90
|
||||
set_propagated_clock [get_clocks {pll_clk90}]
|
||||
create_generated_clock -name pll_clk_divided -source [get_ports {pll_clk}] -divide_by 2 [get_pins {_351_/Y}]
|
||||
create_generated_clock -name pll_clk_divided -source [get_ports {pll_clk}] -divide_by 2 [get_pins {_357_/Y}]
|
||||
set_propagated_clock [get_clocks {pll_clk_divided}]
|
||||
create_generated_clock -name pll_clk90_divided -source [get_ports {pll_clk90}] -divide_by 2 [get_pins {_354_/Y}]
|
||||
create_generated_clock -name pll_clk90_divided -source [get_ports {pll_clk90}] -divide_by 2 [get_pins {_360_/Y}]
|
||||
set_propagated_clock [get_clocks {pll_clk90_divided}]
|
||||
create_generated_clock -name core_ext_clk_syncd -source [get_pins {_426_/Q}] -divide_by 1 [get_pins {_412_/X}]
|
||||
create_generated_clock -name core_ext_clk_syncd -source [get_pins {_432_/Q}] -divide_by 1 [get_pins {_418_/X}]
|
||||
set_propagated_clock [get_clocks {core_ext_clk_syncd}]
|
||||
create_generated_clock -name core_clk_pll -source [get_pins {_351_/Y}] -divide_by 1 [get_pins {_393_/X}]
|
||||
create_generated_clock -name core_clk_pll -source [get_pins {_357_/Y}] -divide_by 1 [get_pins {_399_/X}]
|
||||
set_propagated_clock [get_clocks {core_clk_pll}]
|
||||
create_generated_clock -name user_clk_pll -source [get_pins {_354_/Y}] -divide_by 1 [get_pins {_394_/X}]
|
||||
create_generated_clock -name user_clk_pll -source [get_pins {_360_/Y}] -divide_by 1 [get_pins {_400_/X}]
|
||||
set_propagated_clock [get_clocks {user_clk_pll}]
|
||||
set_clock_groups -name group1 -logically_exclusive \
|
||||
-group [get_clocks {core_ext_clk_syncd}]
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,2 +1,2 @@
|
|||
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
|
||||
0,/home/ma/ef/caravel_openframe/openlane/caravel_clocking,caravel_clocking,caravel_clocking,flow completed,0h2m10s0ms,0h1m53s0ms,89000.0,0.006,44500.0,70.2,722.36,267,0,0,0,0,0,0,0,0,0,0,-1,5468,1980,0.0,0.0,-0.0,-0.01,0.0,0.0,0.0,-0.0,-0.01,0.0,3378159.0,0.0,34.85,17.54,3.08,0.0,0.0,202,252,67,117,0,0,0,200,0,0,0,0,0,0,0,4,72,71,6,40,165,0,205,100.0,10.0,10.0,DELAY 0,5,50,1,15.5,16.9,0.71,0,sky130_fd_sc_hd,0,4
|
||||
0,/home/ma/ef/caravel_openframe/openlane/caravel_clocking,caravel_clocking,caravel_clocking,flow completed,0h1m51s0ms,0h1m36s0ms,90000.0,0.006,45000.0,68.96,668.83,270,0,0,0,0,0,0,0,0,0,0,-1,5326,1956,0.0,0.0,-1,-0.06,-1,0.0,0.0,-1,-0.15,-1,3312107.0,0.0,31.15,16.61,4.43,0.0,0.0,202,252,67,117,0,0,0,200,0,0,0,0,0,0,0,4,73,74,6,40,165,0,205,90.9090909090909,11.0,10.0,DELAY 0,5,50,1,15.5,16.9,0.7,0,sky130_fd_sc_hd,0,4
|
||||
|
|
|
|||
|
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue