[DATA] Update HK pin placement

maglef/housekeeping.mag

@@ -1,31 +1,21 @@
 magic
 tech sky130A
 magscale 1 2
-timestamp 1636934803
+timestamp 1637253363
 << obsli1 >>
-rect 581 87295 60046 107729
-rect 581 84813 60047 87295
-rect 581 80495 60046 84813
-rect 581 78489 60047 80495
-rect 581 78455 60046 78489
-rect 581 70397 60047 78455
-rect 581 69955 60046 70397
-rect 581 61761 60047 69955
-rect 581 61727 60046 61761
-rect 581 55029 60047 61727
-rect 581 54927 60046 55029
-rect 581 51221 60047 54927
-rect 581 50847 60046 51221
-rect 581 41769 60047 50847
-rect 581 41735 60046 41769
-rect 581 34357 60047 41735
-rect 581 34187 60046 34357
-rect 581 22185 60047 34187
-rect 581 22015 60046 22185
-rect 581 17561 60047 22015
-rect 581 901 60046 17561
+rect 949 100759 60046 107831
+rect 949 80257 60047 100759
+rect 949 78183 60046 80257
+rect 949 55913 60047 78183
+rect 949 51731 60046 55913
+rect 949 42245 60047 51731
+rect 949 42007 60046 42245
+rect 949 36873 60047 42007
+rect 949 36567 60046 36873
+rect 949 23069 60047 36567
+rect 949 901 60046 23069
 << obsm1 >>
-rect 14 892 60044 107976
+rect 14 892 60044 108044
 << metal2 >>
 rect 202 109390 258 110190
 rect 662 109390 718 110190
@@ -648,344 +638,344 @@ rect 0 1368 800 1488
 rect 59246 824 60046 944
 rect 0 416 800 536
 << obsm3 >>
-rect 880 109416 60016 109578
+rect 880 109416 59971 109578
 rect 880 109408 59166 109416
 rect 105 109136 59166 109408
-rect 105 108736 60016 109136
-rect 880 108456 60016 108736
-rect 105 107784 60016 108456
+rect 105 108736 59971 109136
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+rect 105 107784 59971 108456
 rect 105 107648 59166 107784
 rect 880 107504 59166 107648
-rect 880 107368 60016 107504
-rect 105 106696 60016 107368
-rect 880 106416 60016 106696
-rect 105 106016 60016 106416
+rect 880 107368 59971 107504
+rect 105 106696 59971 107368
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+rect 105 106016 59971 106416
 rect 105 105736 59166 106016
-rect 105 105608 60016 105736
-rect 880 105328 60016 105608
-rect 105 104656 60016 105328
-rect 880 104384 60016 104656
+rect 105 105608 59971 105736
+rect 880 105328 59971 105608
+rect 105 104656 59971 105328
+rect 880 104384 59971 104656
 rect 880 104376 59166 104384
 rect 105 104104 59166 104376
-rect 105 103568 60016 104104
-rect 880 103288 60016 103568
-rect 105 102616 60016 103288
+rect 105 103568 59971 104104
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+rect 105 102616 59971 103288
 rect 880 102336 59166 102616
-rect 105 101528 60016 102336
-rect 880 101248 60016 101528
-rect 105 100984 60016 101248
+rect 105 101528 59971 102336
+rect 880 101248 59971 101528
+rect 105 100984 59971 101248
 rect 105 100704 59166 100984
-rect 105 100576 60016 100704
-rect 880 100296 60016 100576
-rect 105 99488 60016 100296
-rect 880 99216 60016 99488
+rect 105 100576 59971 100704
+rect 880 100296 59971 100576
+rect 105 99488 59971 100296
+rect 880 99216 59971 99488
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 rect 105 98936 59166 99208
-rect 105 98536 60016 98936
-rect 880 98256 60016 98536
-rect 105 97584 60016 98256
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+rect 105 97584 59971 98256
 rect 105 97448 59166 97584
 rect 880 97304 59166 97448
-rect 880 97168 60016 97304
-rect 105 96496 60016 97168
-rect 880 96216 60016 96496
-rect 105 95816 60016 96216
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 rect 880 89008 59166 89152
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-rect 880 88056 60016 88336
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 rect 105 87248 59166 87384
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 rect 880 83976 59166 83984
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 rect 880 78808 59166 78952
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 rect 105 77048 59166 77184
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 rect 880 73776 59166 73784
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+rect 105 72968 59971 73504
+rect 880 72688 59971 72968
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 rect 105 72016 59166 72152
 rect 880 71872 59166 72016
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-rect 880 70648 60016 70928
-rect 105 70384 60016 70648
+rect 880 71736 59971 71872
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+rect 105 70384 59971 70648
 rect 105 70104 59166 70384
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+rect 105 69976 59971 70104
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 rect 880 68608 59166 68752
 rect 105 68472 59166 68608
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+rect 105 64808 59971 65072
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 rect 880 63576 59166 63720
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+rect 880 61536 59971 61672
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 rect 105 60040 59166 60320
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-rect 880 59496 60016 59776
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-rect 880 58552 60016 58688
+rect 105 59776 59971 60040
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 rect 880 58408 59166 58552
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+rect 105 54608 59971 54872
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 rect 105 51616 59166 51752
 rect 880 51472 59166 51616
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+rect 880 46168 59971 46440
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 rect 105 44808 59166 45088
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+rect 105 44408 59971 44808
+rect 880 44128 59971 44408
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+rect 105 39376 59971 39640
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+rect 105 37336 59971 38008
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+rect 105 36520 59971 37056
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+rect 880 35016 59971 35296
+rect 105 34888 59971 35016
 rect 105 34608 59166 34888
-rect 105 34208 60016 34608
-rect 880 33928 60016 34208
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+rect 105 34208 59971 34608
+rect 880 33928 59971 34208
+rect 105 33256 59971 33928
+rect 880 33120 59971 33256
 rect 880 32976 59166 33120
 rect 105 32840 59166 32976
-rect 105 32168 60016 32840
-rect 880 31888 60016 32168
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+rect 105 32168 59971 32840
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+rect 880 13528 59971 13808
+rect 105 12856 59971 13528
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-rect 105 11768 60016 12576
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-rect 105 11088 60016 11488
+rect 105 11768 59971 12576
+rect 880 11488 59971 11768
+rect 105 11088 59971 11488
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 rect 880 10808 59166 10816
-rect 880 10536 60016 10808
-rect 105 9728 60016 10536
-rect 880 9456 60016 9728
+rect 880 10536 59971 10808
+rect 105 9728 59971 10536
+rect 880 9456 59971 9728
 rect 880 9448 59166 9456
 rect 105 9176 59166 9448
-rect 105 8776 60016 9176
-rect 880 8496 60016 8776
-rect 105 7688 60016 8496
+rect 105 8776 59971 9176
+rect 880 8496 59971 8776
+rect 105 7688 59971 8496
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-rect 105 6736 60016 7408
-rect 880 6456 60016 6736
-rect 105 6056 60016 6456
+rect 105 6736 59971 7408
+rect 880 6456 59971 6736
+rect 105 6056 59971 6456
 rect 105 5776 59166 6056
-rect 105 5648 60016 5776
-rect 880 5368 60016 5648
-rect 105 4696 60016 5368
-rect 880 4416 60016 4696
-rect 105 4288 60016 4416
+rect 105 5648 59971 5776
+rect 880 5368 59971 5648
+rect 105 4696 59971 5368
+rect 880 4416 59971 4696
+rect 105 4288 59971 4416
 rect 105 4008 59166 4288
-rect 105 3608 60016 4008
-rect 880 3328 60016 3608
-rect 105 2656 60016 3328
+rect 105 3608 59971 4008
+rect 880 3328 59971 3608
+rect 105 2656 59971 3328
 rect 880 2376 59166 2656
-rect 105 1568 60016 2376
-rect 880 1288 60016 1568
-rect 105 1024 60016 1288
+rect 105 1568 59971 2376
+rect 880 1288 59971 1568
+rect 105 1024 59971 1288
 rect 105 744 59166 1024
-rect 105 616 60016 744
-rect 880 446 60016 616
+rect 105 616 59971 744
+rect 880 446 59971 616
 << metal4 >>
 rect 4208 2128 4528 107760
 rect 19568 2128 19888 107760
 rect 34928 2128 35248 107760
 rect 50288 2128 50608 107760
 << obsm4 >>
-rect 1163 4659 4128 107541
-rect 4608 4659 19488 107541
-rect 19968 4659 34848 107541
-rect 35328 4659 50208 107541
-rect 50688 4659 59925 107541
+rect 979 3979 4128 104141
+rect 4608 3979 19488 104141
+rect 19968 3979 34848 104141
+rect 35328 3979 50208 104141
+rect 50688 3979 59925 104141
 << metal5 >>
 rect 1104 97206 58880 97526
 rect 1104 81888 58880 82208
@@ -995,9 +985,8 @@ rect 1104 35934 58880 36254
 rect 1104 20616 58880 20936
 rect 1104 5298 58880 5618
 << obsm5 >>
-rect 21276 67210 51036 78020
-rect 21276 51892 51036 66250
-rect 21276 48460 51036 50932
+rect 2508 51892 58212 58980
+rect 2508 38940 58212 50932
 << labels >>
 rlabel metal5 s 1104 20616 58880 20936 6 VGND
 port 1 nsew ground input
@@ -1035,69 +1024,69 @@ rlabel metal3 s 0 49376 800 49496 6 irq[1]
 port 8 nsew signal output
 rlabel metal3 s 0 50328 800 50448 6 irq[2]
 port 9 nsew signal output
-rlabel metal2 s 39394 0 39450 800 6 mask_rev_in[0]
+rlabel metal2 s 36818 0 36874 800 6 mask_rev_in[0]
 port 10 nsew signal input
-rlabel metal2 s 45926 0 45982 800 6 mask_rev_in[10]
+rlabel metal2 s 43350 0 43406 800 6 mask_rev_in[10]
 port 11 nsew signal input
-rlabel metal2 s 46570 0 46626 800 6 mask_rev_in[11]
+rlabel metal2 s 43994 0 44050 800 6 mask_rev_in[11]
 port 12 nsew signal input
-rlabel metal2 s 47306 0 47362 800 6 mask_rev_in[12]
+rlabel metal2 s 44638 0 44694 800 6 mask_rev_in[12]
 port 13 nsew signal input
-rlabel metal2 s 47950 0 48006 800 6 mask_rev_in[13]
+rlabel metal2 s 45282 0 45338 800 6 mask_rev_in[13]
 port 14 nsew signal input
-rlabel metal2 s 48594 0 48650 800 6 mask_rev_in[14]
+rlabel metal2 s 45926 0 45982 800 6 mask_rev_in[14]
 port 15 nsew signal input
-rlabel metal2 s 49238 0 49294 800 6 mask_rev_in[15]
+rlabel metal2 s 46570 0 46626 800 6 mask_rev_in[15]
 port 16 nsew signal input
-rlabel metal2 s 49882 0 49938 800 6 mask_rev_in[16]
+rlabel metal2 s 47306 0 47362 800 6 mask_rev_in[16]
 port 17 nsew signal input
-rlabel metal2 s 50526 0 50582 800 6 mask_rev_in[17]
+rlabel metal2 s 47950 0 48006 800 6 mask_rev_in[17]
 port 18 nsew signal input
-rlabel metal2 s 51170 0 51226 800 6 mask_rev_in[18]
+rlabel metal2 s 48594 0 48650 800 6 mask_rev_in[18]
 port 19 nsew signal input
-rlabel metal2 s 51814 0 51870 800 6 mask_rev_in[19]
+rlabel metal2 s 49238 0 49294 800 6 mask_rev_in[19]
 port 20 nsew signal input
-rlabel metal2 s 40038 0 40094 800 6 mask_rev_in[1]
+rlabel metal2 s 37462 0 37518 800 6 mask_rev_in[1]
 port 21 nsew signal input
-rlabel metal2 s 52458 0 52514 800 6 mask_rev_in[20]
+rlabel metal2 s 49882 0 49938 800 6 mask_rev_in[20]
 port 22 nsew signal input
-rlabel metal2 s 53102 0 53158 800 6 mask_rev_in[21]
+rlabel metal2 s 50526 0 50582 800 6 mask_rev_in[21]
 port 23 nsew signal input
-rlabel metal2 s 53838 0 53894 800 6 mask_rev_in[22]
+rlabel metal2 s 51170 0 51226 800 6 mask_rev_in[22]
 port 24 nsew signal input
-rlabel metal2 s 54482 0 54538 800 6 mask_rev_in[23]
+rlabel metal2 s 51814 0 51870 800 6 mask_rev_in[23]
 port 25 nsew signal input
-rlabel metal2 s 55126 0 55182 800 6 mask_rev_in[24]
+rlabel metal2 s 52458 0 52514 800 6 mask_rev_in[24]
 port 26 nsew signal input
-rlabel metal2 s 55770 0 55826 800 6 mask_rev_in[25]
+rlabel metal2 s 53102 0 53158 800 6 mask_rev_in[25]
 port 27 nsew signal input
-rlabel metal2 s 56414 0 56470 800 6 mask_rev_in[26]
+rlabel metal2 s 53838 0 53894 800 6 mask_rev_in[26]
 port 28 nsew signal input
-rlabel metal2 s 57058 0 57114 800 6 mask_rev_in[27]
+rlabel metal2 s 54482 0 54538 800 6 mask_rev_in[27]
 port 29 nsew signal input
-rlabel metal2 s 57702 0 57758 800 6 mask_rev_in[28]
+rlabel metal2 s 55126 0 55182 800 6 mask_rev_in[28]
 port 30 nsew signal input
-rlabel metal2 s 58346 0 58402 800 6 mask_rev_in[29]
+rlabel metal2 s 55770 0 55826 800 6 mask_rev_in[29]
 port 31 nsew signal input
-rlabel metal2 s 40774 0 40830 800 6 mask_rev_in[2]
+rlabel metal2 s 38106 0 38162 800 6 mask_rev_in[2]
 port 32 nsew signal input
-rlabel metal2 s 58990 0 59046 800 6 mask_rev_in[30]
+rlabel metal2 s 56414 0 56470 800 6 mask_rev_in[30]
 port 33 nsew signal input
-rlabel metal2 s 59634 0 59690 800 6 mask_rev_in[31]
+rlabel metal2 s 57058 0 57114 800 6 mask_rev_in[31]
 port 34 nsew signal input
-rlabel metal2 s 41418 0 41474 800 6 mask_rev_in[3]
+rlabel metal2 s 38750 0 38806 800 6 mask_rev_in[3]
 port 35 nsew signal input
-rlabel metal2 s 42062 0 42118 800 6 mask_rev_in[4]
+rlabel metal2 s 39394 0 39450 800 6 mask_rev_in[4]
 port 36 nsew signal input
-rlabel metal2 s 42706 0 42762 800 6 mask_rev_in[5]
+rlabel metal2 s 40038 0 40094 800 6 mask_rev_in[5]
 port 37 nsew signal input
-rlabel metal2 s 43350 0 43406 800 6 mask_rev_in[6]
+rlabel metal2 s 40774 0 40830 800 6 mask_rev_in[6]
 port 38 nsew signal input
-rlabel metal2 s 43994 0 44050 800 6 mask_rev_in[7]
+rlabel metal2 s 41418 0 41474 800 6 mask_rev_in[7]
 port 39 nsew signal input
-rlabel metal2 s 44638 0 44694 800 6 mask_rev_in[8]
+rlabel metal2 s 42062 0 42118 800 6 mask_rev_in[8]
 port 40 nsew signal input
-rlabel metal2 s 45282 0 45338 800 6 mask_rev_in[9]
+rlabel metal2 s 42706 0 42762 800 6 mask_rev_in[9]
 port 41 nsew signal input
 rlabel metal3 s 59246 9256 60046 9376 6 mgmt_gpio_in[0]
 port 42 nsew signal input
@@ -1327,123 +1316,123 @@ rlabel metal3 s 59246 53320 60046 53440 6 mgmt_gpio_out[8]
 port 154 nsew signal output
 rlabel metal3 s 59246 58352 60046 58472 6 mgmt_gpio_out[9]
 port 155 nsew signal output
-rlabel metal2 s 30930 0 30986 800 6 pad_flash_clk
+rlabel metal2 s 294 0 350 800 6 pad_flash_clk
 port 156 nsew signal output
-rlabel metal2 s 31574 0 31630 800 6 pad_flash_clk_oeb
+rlabel metal2 s 938 0 994 800 6 pad_flash_clk_oeb
 port 157 nsew signal output
-rlabel metal2 s 32218 0 32274 800 6 pad_flash_csb
+rlabel metal2 s 1582 0 1638 800 6 pad_flash_csb
 port 158 nsew signal output
-rlabel metal2 s 32862 0 32918 800 6 pad_flash_csb_oeb
+rlabel metal2 s 2226 0 2282 800 6 pad_flash_csb_oeb
 port 159 nsew signal output
-rlabel metal2 s 33506 0 33562 800 6 pad_flash_io0_di
+rlabel metal2 s 2870 0 2926 800 6 pad_flash_io0_di
 port 160 nsew signal input
-rlabel metal2 s 34242 0 34298 800 6 pad_flash_io0_do
+rlabel metal2 s 3514 0 3570 800 6 pad_flash_io0_do
 port 161 nsew signal output
-rlabel metal2 s 34886 0 34942 800 6 pad_flash_io0_ieb
+rlabel metal2 s 4158 0 4214 800 6 pad_flash_io0_ieb
 port 162 nsew signal output
-rlabel metal2 s 35530 0 35586 800 6 pad_flash_io0_oeb
+rlabel metal2 s 4802 0 4858 800 6 pad_flash_io0_oeb
 port 163 nsew signal output
-rlabel metal2 s 36174 0 36230 800 6 pad_flash_io1_di
+rlabel metal2 s 5446 0 5502 800 6 pad_flash_io1_di
 port 164 nsew signal input
-rlabel metal2 s 36818 0 36874 800 6 pad_flash_io1_do
+rlabel metal2 s 6090 0 6146 800 6 pad_flash_io1_do
 port 165 nsew signal output
-rlabel metal2 s 37462 0 37518 800 6 pad_flash_io1_ieb
+rlabel metal2 s 6734 0 6790 800 6 pad_flash_io1_ieb
 port 166 nsew signal output
-rlabel metal2 s 38106 0 38162 800 6 pad_flash_io1_oeb
+rlabel metal2 s 7470 0 7526 800 6 pad_flash_io1_oeb
 port 167 nsew signal output
-rlabel metal2 s 6734 0 6790 800 6 pll90_sel[0]
+rlabel metal2 s 15934 0 15990 800 6 pll90_sel[0]
 port 168 nsew signal output
-rlabel metal2 s 7470 0 7526 800 6 pll90_sel[1]
+rlabel metal2 s 16578 0 16634 800 6 pll90_sel[1]
 port 169 nsew signal output
-rlabel metal2 s 8114 0 8170 800 6 pll90_sel[2]
+rlabel metal2 s 17222 0 17278 800 6 pll90_sel[2]
 port 170 nsew signal output
-rlabel metal2 s 25686 0 25742 800 6 pll_bypass
+rlabel metal2 s 34886 0 34942 800 6 pll_bypass
 port 171 nsew signal output
-rlabel metal2 s 938 0 994 800 6 pll_dco_ena
+rlabel metal2 s 10046 0 10102 800 6 pll_dco_ena
 port 172 nsew signal output
-rlabel metal2 s 1582 0 1638 800 6 pll_div[0]
+rlabel metal2 s 10690 0 10746 800 6 pll_div[0]
 port 173 nsew signal output
-rlabel metal2 s 2226 0 2282 800 6 pll_div[1]
+rlabel metal2 s 11334 0 11390 800 6 pll_div[1]
 port 174 nsew signal output
-rlabel metal2 s 2870 0 2926 800 6 pll_div[2]
+rlabel metal2 s 11978 0 12034 800 6 pll_div[2]
 port 175 nsew signal output
-rlabel metal2 s 3514 0 3570 800 6 pll_div[3]
+rlabel metal2 s 12622 0 12678 800 6 pll_div[3]
 port 176 nsew signal output
-rlabel metal2 s 4158 0 4214 800 6 pll_div[4]
+rlabel metal2 s 13266 0 13322 800 6 pll_div[4]
 port 177 nsew signal output
-rlabel metal2 s 294 0 350 800 6 pll_ena
+rlabel metal2 s 9402 0 9458 800 6 pll_ena
 port 178 nsew signal output
-rlabel metal2 s 4802 0 4858 800 6 pll_sel[0]
+rlabel metal2 s 14002 0 14058 800 6 pll_sel[0]
 port 179 nsew signal output
-rlabel metal2 s 5446 0 5502 800 6 pll_sel[1]
+rlabel metal2 s 14646 0 14702 800 6 pll_sel[1]
 port 180 nsew signal output
-rlabel metal2 s 6090 0 6146 800 6 pll_sel[2]
+rlabel metal2 s 15290 0 15346 800 6 pll_sel[2]
 port 181 nsew signal output
-rlabel metal2 s 8758 0 8814 800 6 pll_trim[0]
+rlabel metal2 s 17866 0 17922 800 6 pll_trim[0]
 port 182 nsew signal output
-rlabel metal2 s 15290 0 15346 800 6 pll_trim[10]
+rlabel metal2 s 24398 0 24454 800 6 pll_trim[10]
 port 183 nsew signal output
-rlabel metal2 s 15934 0 15990 800 6 pll_trim[11]
+rlabel metal2 s 25042 0 25098 800 6 pll_trim[11]
 port 184 nsew signal output
-rlabel metal2 s 16578 0 16634 800 6 pll_trim[12]
+rlabel metal2 s 25686 0 25742 800 6 pll_trim[12]
 port 185 nsew signal output
-rlabel metal2 s 17222 0 17278 800 6 pll_trim[13]
+rlabel metal2 s 26330 0 26386 800 6 pll_trim[13]
 port 186 nsew signal output
-rlabel metal2 s 17866 0 17922 800 6 pll_trim[14]
+rlabel metal2 s 27066 0 27122 800 6 pll_trim[14]
 port 187 nsew signal output
-rlabel metal2 s 18510 0 18566 800 6 pll_trim[15]
+rlabel metal2 s 27710 0 27766 800 6 pll_trim[15]
 port 188 nsew signal output
-rlabel metal2 s 19154 0 19210 800 6 pll_trim[16]
+rlabel metal2 s 28354 0 28410 800 6 pll_trim[16]
 port 189 nsew signal output
-rlabel metal2 s 19798 0 19854 800 6 pll_trim[17]
+rlabel metal2 s 28998 0 29054 800 6 pll_trim[17]
 port 190 nsew signal output
-rlabel metal2 s 20534 0 20590 800 6 pll_trim[18]
+rlabel metal2 s 29642 0 29698 800 6 pll_trim[18]
 port 191 nsew signal output
-rlabel metal2 s 21178 0 21234 800 6 pll_trim[19]
+rlabel metal2 s 30286 0 30342 800 6 pll_trim[19]
 port 192 nsew signal output
-rlabel metal2 s 9402 0 9458 800 6 pll_trim[1]
+rlabel metal2 s 18510 0 18566 800 6 pll_trim[1]
 port 193 nsew signal output
-rlabel metal2 s 21822 0 21878 800 6 pll_trim[20]
+rlabel metal2 s 30930 0 30986 800 6 pll_trim[20]
 port 194 nsew signal output
-rlabel metal2 s 22466 0 22522 800 6 pll_trim[21]
+rlabel metal2 s 31574 0 31630 800 6 pll_trim[21]
 port 195 nsew signal output
-rlabel metal2 s 23110 0 23166 800 6 pll_trim[22]
+rlabel metal2 s 32218 0 32274 800 6 pll_trim[22]
 port 196 nsew signal output
-rlabel metal2 s 23754 0 23810 800 6 pll_trim[23]
+rlabel metal2 s 32862 0 32918 800 6 pll_trim[23]
 port 197 nsew signal output
-rlabel metal2 s 24398 0 24454 800 6 pll_trim[24]
+rlabel metal2 s 33506 0 33562 800 6 pll_trim[24]
 port 198 nsew signal output
-rlabel metal2 s 25042 0 25098 800 6 pll_trim[25]
+rlabel metal2 s 34242 0 34298 800 6 pll_trim[25]
 port 199 nsew signal output
-rlabel metal2 s 10046 0 10102 800 6 pll_trim[2]
+rlabel metal2 s 19154 0 19210 800 6 pll_trim[2]
 port 200 nsew signal output
-rlabel metal2 s 10690 0 10746 800 6 pll_trim[3]
+rlabel metal2 s 19798 0 19854 800 6 pll_trim[3]
 port 201 nsew signal output
-rlabel metal2 s 11334 0 11390 800 6 pll_trim[4]
+rlabel metal2 s 20534 0 20590 800 6 pll_trim[4]
 port 202 nsew signal output
-rlabel metal2 s 11978 0 12034 800 6 pll_trim[5]
+rlabel metal2 s 21178 0 21234 800 6 pll_trim[5]
 port 203 nsew signal output
-rlabel metal2 s 12622 0 12678 800 6 pll_trim[6]
+rlabel metal2 s 21822 0 21878 800 6 pll_trim[6]
 port 204 nsew signal output
-rlabel metal2 s 13266 0 13322 800 6 pll_trim[7]
+rlabel metal2 s 22466 0 22522 800 6 pll_trim[7]
 port 205 nsew signal output
-rlabel metal2 s 14002 0 14058 800 6 pll_trim[8]
+rlabel metal2 s 23110 0 23166 800 6 pll_trim[8]
 port 206 nsew signal output
-rlabel metal2 s 14646 0 14702 800 6 pll_trim[9]
+rlabel metal2 s 23754 0 23810 800 6 pll_trim[9]
 port 207 nsew signal output
-rlabel metal2 s 38750 0 38806 800 6 porb
+rlabel metal2 s 8114 0 8170 800 6 porb
 port 208 nsew signal input
-rlabel metal2 s 27066 0 27122 800 6 pwr_ctrl_out[0]
+rlabel metal2 s 57702 0 57758 800 6 pwr_ctrl_out[0]
 port 209 nsew signal output
-rlabel metal2 s 27710 0 27766 800 6 pwr_ctrl_out[1]
+rlabel metal2 s 58346 0 58402 800 6 pwr_ctrl_out[1]
 port 210 nsew signal output
-rlabel metal2 s 28354 0 28410 800 6 pwr_ctrl_out[2]
+rlabel metal2 s 58990 0 59046 800 6 pwr_ctrl_out[2]
 port 211 nsew signal output
-rlabel metal2 s 28998 0 29054 800 6 pwr_ctrl_out[3]
+rlabel metal2 s 59634 0 59690 800 6 pwr_ctrl_out[3]
 port 212 nsew signal output
 rlabel metal3 s 0 58488 800 58608 6 qspi_enabled
 port 213 nsew signal input
-rlabel metal2 s 26330 0 26386 800 6 reset
+rlabel metal2 s 8758 0 8814 800 6 reset
 port 214 nsew signal output
 rlabel metal3 s 0 57536 800 57656 6 ser_rx
 port 215 nsew signal output
@@ -1663,7 +1652,7 @@ rlabel metal2 s 3882 109390 3938 110190 6 wb_adr_i[8]
 port 322 nsew signal input
 rlabel metal2 s 4342 109390 4398 110190 6 wb_adr_i[9]
 port 323 nsew signal input
-rlabel metal2 s 29642 0 29698 800 6 wb_clk_i
+rlabel metal2 s 35530 0 35586 800 6 wb_clk_i
 port 324 nsew signal input
 rlabel metal2 s 32310 109390 32366 110190 6 wb_cyc_i
 port 325 nsew signal input
@@ -1795,7 +1784,7 @@ rlabel metal3 s 0 71816 800 71936 6 wb_dat_o[8]
 port 388 nsew signal output
 rlabel metal3 s 0 72768 800 72888 6 wb_dat_o[9]
 port 389 nsew signal output
-rlabel metal2 s 30286 0 30342 800 6 wb_rst_i
+rlabel metal2 s 36174 0 36230 800 6 wb_rstn_i
 port 390 nsew signal input
 rlabel metal2 s 29918 109390 29974 110190 6 wb_sel_i[0]
 port 391 nsew signal input
@@ -1813,8 +1802,8 @@ port 396 nsew signal input
 string LEFclass BLOCK
 string FIXED_BBOX 0 0 60046 110190
 string LEFview TRUE
-string GDS_FILE /project/openlane/housekeeping/runs/housekeeping/results/magic/housekeeping.gds
-string GDS_END 22792468
-string GDS_START 1089928
+string GDS_FILE /home/ma/ef/caravel_openframe/openlane/housekeeping/runs/housekeeping/results/magic/housekeeping.gds
+string GDS_END 22484834
+string GDS_START 1111786
 << end >>
 

openlane/housekeeping/base.sdc

@@ -1,14 +1,26 @@
-create_clock [get_ports {"wb_clk_i"} ] -name "wb_clk_i"  -period 25
-create_clock [get_pins {"_09582_/X"} ] -name "csclk"  -period 100
-create_clock [get_ports {"mgmt_gpio_in[4]"} ] -name "mgmt_gpio_in"  -period 100
+set ::env(WB_CLK_PERIOD) 25 
+set ::env(SCK_CLK_PERIOD) 100
 
-set input_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
-set output_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
+create_clock [get_ports {"wb_clk_i"} ] -name "wb_clk_i"  -period $::env(WB_CLK_PERIOD)
+create_clock [get_ports {"mgmt_gpio_in[4]"} ] -name "mgmt_gpio_in"  -period $::env(SCK_CLK_PERIOD)
+
+# change the csclk pin whenever the synthesis receipe changes 
+create_generated_clock -name "csclk" -source [get_ports {"mgmt_gpio_in[4]"} ] -divide_by 1 [get_pins {"_8889_/X"} ] 
+
+set input_delay_value [expr $::env(WB_CLK_PERIOD) * $::env(IO_PCT)]
+set output_delay_value [expr $::env(WB_CLK_PERIOD) * $::env(IO_PCT)]
 puts "\[INFO\]: Setting output delay to: $output_delay_value"
 puts "\[INFO\]: Setting input delay to: $input_delay_value"
 
+
+set sck_clk_indx [lsearch [all_inputs] [get_port "mgmt_gpio_in[4]"]]
+#set rst_indx [lsearch [all_inputs] [get_port resetn]]
+set all_inputs_wo_clk [lreplace [all_inputs] $sck_clk_indx $sck_clk_indx]
+#set all_inputs_wo_clk_rst [lreplace $all_inputs_wo_clk $rst_indx $rst_indx]
+set all_inputs_wo_clk_rst $all_inputs_wo_clk
+
 set_max_fanout $::env(SYNTH_MAX_FANOUT) [current_design]
-set_input_delay $input_delay_value  -clock [get_clocks $::env(CLOCK_PORT)] [all_inputs]
+set_input_delay $input_delay_value  -clock [get_clocks $::env(CLOCK_PORT)] $all_inputs_wo_clk
 set_output_delay $output_delay_value  -clock [get_clocks $::env(CLOCK_PORT)] [all_outputs]
 
 # TODO set this as parameter

openlane/housekeeping/config.tcl

@@ -25,14 +25,14 @@ set ::env(VERILOG_FILES) "\
     $script_dir/../../verilog/rtl/housekeeping.v"
 
 set ::env(CLOCK_PORT) "wb_clk_i"
-set ::env(CLOCK_NET) {$::env(CLOCK_PORT) csclk mgmt_gpio_in\[4\]}
+set ::env(CLOCK_NET) {wb_clk_i csclk mgmt_gpio_in[4]}
 
 set ::env(BASE_SDC_FILE) $script_dir/base.sdc
 
 ## Synthesis 
 set ::env(NO_SYNTH_CELL_LIST) $script_dir/no_synth.list 
 
-set ::env(SYNTH_MAX_FANOUT) 5
+set ::env(SYNTH_MAX_FANOUT) 10
 
 ## Floorplan
 set ::env(FP_SIZING) absolute
@@ -48,13 +48,17 @@ set ::env(CELL_PAD) 0
 set ::env(GLB_RT_ADJUSTMENT) 0.05 
 set ::env(GLB_RT_OVERFLOW_ITERS) 100
 
+set ::env(GLB_RESIZER_HOLD_SLACK_MARGIN) 0.17
+
 ## Placement
 set ::env(PL_TARGET_DENSITY) 0.384
 
+set ::env(PL_RESIZER_HOLD_SLACK_MARGIN) .17
 set ::env(PL_RESIZER_MAX_SLEW_MARGIN) "30"
 
 ## Diode Insertion
 set ::env(DIODE_INSERTION_STRATEGY) "3"
+set ::env(GLB_RT_ANT_ITERS) "7"
 
 # Disbale timing checks for now till the issue with the clock gating path is fixed 
 # The timing reports show only one violating path from the mgmt_gpio_ 

openlane/housekeeping/pin_order.cfg

@@ -90,6 +90,9 @@ mgmt_gpio_(in|out|oeb)\[36\]
 mgmt_gpio_(in|out|oeb)\[37\]
 
 #S
+pad_flash_.*
+porb
+reset
 pll_ena
 pll_dco_ena
 pll_div.*
@@ -97,10 +100,7 @@ pll_sel.*
 pll90_sel.*
 pll_trim.*
 pll_bypass.*
-reset
-pwr_ctrl_out.*
 wb_clk_i
-wb_rst_i
-pad_flash_.*
-porb
-mask_rev_in.*
+wb_rstn_i
+mask_rev_in.*
+pwr_ctrl_out.*

signoff/housekeeping/OPENLANE_VERSION

@@ -1 +1 @@
-openlane 2021.09.09_03.00.48-60-gcbb562b
+openlane 2021.09.09_03.00.48-66-gbdb1b56

signoff/housekeeping/final_summary_report.csv

@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/housekeeping,housekeeping,housekeeping,flow_completed,0h36m47s,-1,69039.84858847831,0.16541171850000005,34519.92429423916,38.33,933.62,5710,0,0,0,0,0,0,0,29,0,66,-1,469741,62613,0.0,-7.95,-1,-0.11,-1,0.0,-4011.93,-1,-0.11,-1,340480133.0,42.45,39.79,63.92,14.53,39.21,1.7,8462,9596,194,1275,0,0,0,9223,0,0,0,0,0,0,0,4,1066,1020,50,388,2156,0,2544,90.9090909090909,11.0,10.0,AREA 0,5,50,1,153.6,153.18,0.384,0.05,sky130_fd_sc_hd,0,3
+0,/home/ma/ef/caravel_openframe/openlane/housekeeping,housekeeping,housekeeping,flow_completed,0h28m56s,-1,64928.89438180887,0.16541171850000005,32464.447190904433,37.52,961.92,5370,0,0,0,0,0,0,0,57,0,66,-1,454178,61924,-1.5,-11.43,-1,0.0,-1,-753.9,-6155.54,-1,0.0,-1,313455162.0,27.26,39.37,64.05,15.67,30.22,1.82,8469,9603,194,1275,0,0,0,9230,0,0,0,0,0,0,0,4,1066,991,49,388,2156,0,2544,90.9090909090909,11.0,10.0,AREA 0,10,50,1,153.6,153.18,0.384,0.05,sky130_fd_sc_hd,0,3