[DATA] Add user_analog_project_wrapper and chip_io_alt gds/lef views

2021-11-22 23:07:13 +02:00 · 2021-11-22 23:07:13 +02:00 · 38f64d08a3
parent cd68a2aeff
commit 38f64d08a3
15 changed files with 29634 additions and 10 deletions
--- a/21
+++ b/21
@ -410,19 +410,34 @@ $(MAG_BLOCKS): mag2gds-% : ./mag/%.mag uncompress
 	echo "Converting mag file $* to GDS..."
 	echo "addpath $(CARAVEL_ROOT)/mag/hexdigits;\
 		addpath ${PDKPATH}/libs.ref/sky130_ml_xx_hd/mag;\
-		addpath ${CARAVEL_ROOT}/subcells/simple_por/mag;\
+		addpath $(CARAVEL_ROOT)/mag/primitives;\
 		drc off;\
 		gds rescale false;\
 		load $* -dereference;\
 		select top cell;\
 		expand;\
-		cif *hier write disable;\
 		gds write $*.gds;\
 		exit;" > ./mag/mag2gds_$*.tcl
 	cd ./mag && magic -rcfile ${PDK_ROOT}/sky130A/libs.tech/magic/sky130A.magicrc -noc -dnull mag2gds_$*.tcl < /dev/null
 	rm ./mag/mag2gds_$*.tcl
 	mv -f ./mag/$*.gds ./gds/
-	
+
+# MAG2LEF 
+BLOCKS = $(shell cd openlane && find * -maxdepth 0 -type d)
+MAG_BLOCKS = $(foreach block, $(BLOCKS), mag2lef-$(block))
+$(MAG_BLOCKS): mag2lef-% : ./mag/%.mag uncompress
+	echo "Converting mag file $* to LEF..."
+	echo "addpath $(CARAVEL_ROOT)/mag/hexdigits;\
+		addpath ${PDKPATH}/libs.ref/sky130_ml_xx_hd/mag;\
+		addpath $(CARAVEL_ROOT)/mag/primitives;\
+		drc off;\
+		load $*;\
+		lef write $*.lef;\
+		exit;" > ./mag/mag2lef_$*.tcl
+	cd ./mag && magic -rcfile ${PDK_ROOT}/sky130A/libs.tech/magic/sky130A.magicrc -noc -dnull mag2lef_$*.tcl < /dev/null
+	rm ./mag/mag2lef_$*.tcl
+	mv -f ./mag/$*.lef ./lef/
+
 .PHONY: help
 help:
 	@$(MAKE) -pRrq -f $(lastword $(MAKEFILE_LIST)) : 2>/dev/null | awk -v RS= -F: '/^# File/,/^# Finished Make data base/ {if ($$1 !~ "^[#.]") {print $$1}}' | sort | egrep -v -e '^[^[:alnum:]]' -e '^$@$$'
--- a/def/user_analog_project_wrapper.def
+++ b/def/user_analog_project_wrapper.def
--- a/gds/chip_io_alt.gds.gz
+++ b/gds/chip_io_alt.gds.gz
--- a/gds/user_analog_project_wrapper.gds.gz
+++ b/gds/user_analog_project_wrapper.gds.gz
--- a/lef/chip_io_alt.lef
+++ b/lef/chip_io_alt.lef
--- a/lef/user_analog_project_wrapper.lef
+++ b/lef/user_analog_project_wrapper.lef
--- a/mag/user_analog_project_wrapper.mag
+++ b/mag/user_analog_project_wrapper.mag
@ -1,6 +1,6 @@
 magic
 tech sky130A
-timestamp 1620244087
+timestamp 1632839657
 << checkpaint >>
 rect -680 351370 292680 352680
 rect -680 630 630 351370
@ -686,6 +686,20 @@ rect -400 1363 240 1419
 rect 291760 1363 292400 1419
 rect -400 772 240 828
 rect 291760 772 292400 828
+<< metal4 >>
+rect 82797 351150 85297 352400
+rect 87947 351150 90447 352400
+rect 108647 351150 111147 352400
+rect 113797 351150 116297 352400
+rect 159497 351150 161997 352400
+rect 164647 351150 167147 352400
+<< metal5 >>
+rect 82797 351150 85297 352400
+rect 87947 351150 90447 352400
+rect 108647 351150 111147 352400
+rect 113797 351150 116297 352400
+rect 159497 351150 161997 352400
+rect 164647 351150 167147 352400
 << comment >>
 rect -50 352000 292050 352050
 rect -50 0 0 352000
@ -776,10 +790,22 @@ flabel metal3 s 206697 351150 209197 352400 0 FreeSans 960 180 0 0 io_analog[3]
 port 40 nsew signal bidirectional
 flabel metal3 s 164647 351150 167147 352400 0 FreeSans 960 180 0 0 io_analog[4]
 port 41 nsew signal bidirectional
+flabel metal4 s 164647 351150 167147 352400 0 FreeSans 960 180 0 0 io_analog[4]
+port 41 nsew signal bidirectional
+flabel metal5 s 164647 351150 167147 352400 0 FreeSans 960 180 0 0 io_analog[4]
+port 41 nsew signal bidirectional
 flabel metal3 s 113797 351150 116297 352400 0 FreeSans 960 180 0 0 io_analog[5]
 port 42 nsew signal bidirectional
+flabel metal4 s 113797 351150 116297 352400 0 FreeSans 960 180 0 0 io_analog[5]
+port 42 nsew signal bidirectional
+flabel metal5 s 113797 351150 116297 352400 0 FreeSans 960 180 0 0 io_analog[5]
+port 42 nsew signal bidirectional
 flabel metal3 s 87947 351150 90447 352400 0 FreeSans 960 180 0 0 io_analog[6]
 port 43 nsew signal bidirectional
+flabel metal4 s 87947 351150 90447 352400 0 FreeSans 960 180 0 0 io_analog[6]
+port 43 nsew signal bidirectional
+flabel metal5 s 87947 351150 90447 352400 0 FreeSans 960 180 0 0 io_analog[6]
+port 43 nsew signal bidirectional
 flabel metal3 s 60097 351150 62597 352400 0 FreeSans 960 180 0 0 io_analog[7]
 port 44 nsew signal bidirectional
 flabel metal3 s 34097 351150 36597 352400 0 FreeSans 960 180 0 0 io_analog[8]
@ -788,10 +814,22 @@ flabel metal3 s 8097 351150 10597 352400 0 FreeSans 960 180 0 0 io_analog[9]
 port 46 nsew signal bidirectional
 flabel metal3 s 159497 351150 161997 352400 0 FreeSans 960 180 0 0 io_analog[4]
 port 47 nsew signal bidirectional
+flabel metal4 s 159497 351150 161997 352400 0 FreeSans 960 180 0 0 io_analog[4]
+port 47 nsew signal bidirectional
+flabel metal5 s 159497 351150 161997 352400 0 FreeSans 960 180 0 0 io_analog[4]
+port 47 nsew signal bidirectional
 flabel metal3 s 108647 351150 111147 352400 0 FreeSans 960 180 0 0 io_analog[5]
 port 48 nsew signal bidirectional
+flabel metal4 s 108647 351150 111147 352400 0 FreeSans 960 180 0 0 io_analog[5]
+port 48 nsew signal bidirectional
+flabel metal5 s 108647 351150 111147 352400 0 FreeSans 960 180 0 0 io_analog[5]
+port 48 nsew signal bidirectional
 flabel metal3 s 82797 351150 85297 352400 0 FreeSans 960 180 0 0 io_analog[6]
 port 49 nsew signal bidirectional
+flabel metal4 s 82797 351150 85297 352400 0 FreeSans 960 180 0 0 io_analog[6]
+port 49 nsew signal bidirectional
+flabel metal5 s 82797 351150 85297 352400 0 FreeSans 960 180 0 0 io_analog[6]
+port 49 nsew signal bidirectional
 flabel metal3 s 163397 351150 164497 352400 0 FreeSans 960 180 0 0 io_clamp_high[0]
 port 50 nsew signal bidirectional
 flabel metal3 s 112547 351150 113647 352400 0 FreeSans 960 180 0 0 io_clamp_high[1]
@ -2050,4 +2088,4 @@ flabel metal2 s 3217 -400 3273 240 0 FreeSans 560 90 0 0 wbs_we_i
 port 677 nsew signal input
 << properties >>
 string FIXED_BBOX 0 0 292000 352000
-<< end >>
+<< end >>
--- a/openlane/Makefile
+++ b/openlane/Makefile
@ -20,8 +20,8 @@ CLEAN = $(foreach block,$(BLOCKS), clean-$(block))

 OPENLANE_TAG ?= v0.20
 OPENLANE_IMAGE_NAME ?= efabless/openlane:$(OPENLANE_TAG)
-OPENLANE_BASIC_COMMAND = "cd /project/openlane && flow.tcl -design ./$* -save_path .. -save -tag $* -overwrite"
-OPENLANE_INTERACTIVE_COMMAND = "cd /project/openlane && flow.tcl -it -file ./$*/interactive.tcl"
+OPENLANE_BASIC_COMMAND = "cd $(PWD)/../openlane && flow.tcl -design ./$* -save_path .. -save -tag $* -overwrite"
+OPENLANE_INTERACTIVE_COMMAND = "cd $(PWD)/../openlane && flow.tcl -it -file ./$*/interactive.tcl"

 all: $(BLOCKS)

@ -42,10 +42,11 @@ endif
 	@sleep 1

 	@if [ -f ./$*/interactive.tcl ]; then\
-		docker run -it -v $(OPENLANE_ROOT):/openLane \
+		docker run -it -v $(OPENLANE_ROOT):/openlane \
 		-v $(PDK_ROOT):$(PDK_ROOT) \
-		-v $(PWD)/..:/project \
+		-v $(PWD)/..:$(PWD)/.. \
 		-v $(CARAVEL_ROOT):$(CARAVEL_ROOT) \
+		-v $(MGMT_AREA_ROOT):$(MGMT_AREA_ROOT) \
 		-e PDK_ROOT=$(PDK_ROOT) \
 		-e CARAVEL_ROOT=$(CARAVEL_ROOT) \
 		-u $(shell id -u $(USER)):$(shell id -g $(USER)) \
@ -53,8 +54,9 @@ endif
 	else\
 		docker run -it -v $(OPENLANE_ROOT):/openlane \
 		-v $(PDK_ROOT):$(PDK_ROOT) \
-		-v $(PWD)/..:/project \
+		-v $(PWD)/..:$(PWD)/.. \
 		-v $(CARAVEL_ROOT):$(CARAVEL_ROOT) \
+		-v $(MGMT_AREA_ROOT):$(MGMT_AREA_ROOT) \
 		-e PDK_ROOT=$(PDK_ROOT) \
 		-e CARAVEL_ROOT=$(CARAVEL_ROOT) \
 		-u $(shell id -u $(USER)):$(shell id -g $(USER)) \
--- a/openlane/chip_io_alt/config.tcl
+++ b/openlane/chip_io_alt/config.tcl
@ -0,0 +1,59 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+set script_dir [file dirname [file normalize [info script]]]
+
+set ::env(DESIGN_NAME) chip_io_alt
+
+set ::env(VERILOG_FILES) "\
+	$script_dir/../../verilog/rtl/defines.v\
+	$script_dir/../../verilog/rtl/pads.v\
+	$script_dir/../../verilog/rtl/mprj_io.v\
+	$script_dir/../../verilog/rtl/chip_io_alt.v"
+
+# The removal of this line is pending the IO verilog files being parsable by yosys...
+set ::env(VERILOG_FILES_BLACKBOX) "\
+    $script_dir/../../verilog/stubs/sky130_fd_io__top_xres4v2.v\
+    $script_dir/../../verilog/stubs/sky130_fd_io__top_ground_lvc_wpad.v\
+    $script_dir/../../verilog/stubs/sky130_fd_io__top_power_lvc_wpad.v"
+
+set ::env(GPIO_PADS_VERILOG) "\
+	$::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/verilog/sky130_ef_io.v"
+
+
+set ::env(DESIGN_IS_PADFRAME) 1
+set ::env(SYNTH_FLAT_TOP) 1
+set ::env(USE_GPIO_PADS) 1
+
+
+set ::env(FP_SIZING) absolute
+
+set fd [open "$script_dir/../chip_dimensions.txt" "r"]
+set ::env(DIE_AREA) [read $fd]
+close $fd
+
+
+set ::env(MAGIC_WRITE_FULL_LEF) 1
+
+set ::env(DIODE_INSERTION_STRATEGY) 0
+set ::env(GLB_RT_TILES) 30
+set ::env(GLB_RT_MAXLAYER) 4
+set ::env(GLB_RT_UNIDIRECTIONAL) 0
+# set ::env(GLB_RT_ALLOW_CONGESTION) 1
+# set ::env(GLB_RT_OVERFLOW_ITERS) 150
+
+set ::env(LVS_CONNECT_BY_LABEL) 1
+
+set ::env(QUIT_ON_ILLEGAL_OVERLAPS) 0
--- a/openlane/chip_io_alt/interactive.tcl
+++ b/openlane/chip_io_alt/interactive.tcl
@ -0,0 +1,153 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+package require openlane
+set script_dir [file dirname [file normalize [info script]]]
+set save_path $script_dir/../..
+
+# FOR LVS AND CREATING PORT LABELS
+set ::env(USE_GPIO_ROUTING_LEF) 0
+prep -design $script_dir -tag chip_io_alt_lvs -overwrite
+
+# Needed for the sky130_ef_io__analog_pad verilog views
+set ::env(SYNTH_DEFINES) "USE_POWER_PINS"
+verilog_elaborate
+#init_floorplan
+#file copy -force $::env(CURRENT_DEF) $::env(TMP_DIR)/lvs.def
+#file copy -force $::env(CURRENT_NETLIST) $::env(TMP_DIR)/lvs.v
+
+# ACTUAL CHIP INTEGRATION
+set ::env(USE_GPIO_ROUTING_LEF) 1
+prep -design $script_dir -tag chip_io_alt -overwrite
+
+# file copy $script_dir/runs/chip_io_alt_lvs/tmp/merged_unpadded.lef $::env(TMP_DIR)/lvs.lef
+# file copy $script_dir/runs/chip_io_alt_lvs/tmp/lvs.def $::env(TMP_DIR)/lvs.def
+# file copy $script_dir/runs/chip_io_alt_lvs/tmp/lvs.v $::env(TMP_DIR)/lvs.v
+
+set ::env(SYNTH_DEFINES) "TOP_ROUTING USE_POWER_PINS"
+verilog_elaborate
+
+#init_floorplan
+
+puts_info "Generating pad frame"
+exec python3 $::env(SCRIPTS_DIR)/padringer.py\
+	--def-netlist $::env(CURRENT_DEF)\
+	--design $::env(DESIGN_NAME)\
+	--lefs $::env(TECH_LEF) {*}$::env(GPIO_PADS_LEF)\
+	-cfg $script_dir/padframe.cfg\
+	--working-dir $::env(TMP_DIR)\
+	-o $::env(RESULTS_DIR)/floorplan/padframe.def   2>&1
+puts_info "Generated pad frame"
+
+set_def $::env(RESULTS_DIR)/floorplan/padframe.def
+
+# modify to a different file
+remove_pins -input $::env(CURRENT_DEF)
+remove_empty_nets -input $::env(CURRENT_DEF)
+
+set core_obs "
+	met1 225 235 3365 4950, \
+	met2 225 235 3365 4950, \
+	met3 225 235 3365 4950, \
+	met4 225 235 3365 4955, \ 
+	met5 225 235 3365 4955
+"
+
+set gpio_m3_pins_west_0 "met3 198.400 1002.125 215.185 2202.125"
+
+set gpio_m3_pins_west_1 "met3 198.400 2726.820 215.185 4126.82"
+
+set gpio_m3_pins_west_2 "met3 198.400 4641.655 215.185 4755.305"
+
+set gpio_m3_pins_east "met3 3370.840 600.050 3387.01 4731.99"
+
+# South Power Pads
+set vssa_south_obs "
+	met3 393.99000 198.45500 468.60000 222.76000"
+
+set vssd_south_obs "
+	met3 1205.66500 196.21000 1280.500 276.98500"
+
+set vssio_south_obs "
+	met3 2845.04000 198.49500 2919.58500 230.61000"
+
+# East Power Pads
+set vssa1_p2_east_obs "
+	met3 3317.33500 2040.81500 3389.89500 2117.49500"
+
+set vssd1_east_obs "
+	met3 3316.26500 2285.19500 3379.17500 2385.12500, \
+	met4 3316.26500 2285.19500 3379.17500 2385.12500"
+
+set vdda1_p2_east_obs "
+	met3 3338.51500 2474.03500 3389.27500 2550.56000, \
+	met4 3338.51500 2474.03500 3389.27500 2550.5600"
+
+set vdda1_east_obs "
+	met3 3340.13500 4017.53500 3385.45000 4094.53500"
+
+
+set ::env(GLB_RT_OBS) "
+	$core_obs, \ 
+	$gpio_m3_pins_west_0, \
+	$gpio_m3_pins_west_1, \
+	$gpio_m3_pins_west_2, \
+	$gpio_m3_pins_east, \
+	$vssd_south_obs, \
+	$vssio_south_obs, \
+	$vssd1_east_obs, \
+	$vdda1_p2_east_obs, \
+	$vdda1_east_obs
+"
+
+try_catch python3 $::env(SCRIPTS_DIR)/add_def_obstructions.py \
+	--input-def $::env(CURRENT_DEF) \
+	--lef $::env(MERGED_LEF) \
+	--obstructions $::env(GLB_RT_OBS) \
+	--output [file rootname $::env(CURRENT_DEF)].obs.def |& tee $::env(TERMINAL_OUTPUT) $::env(LOG_DIR)/obs.log
+
+set_def [file rootname $::env(CURRENT_DEF)].obs.def
+
+li1_hack_start
+global_routing
+detailed_routing
+li1_hack_end
+
+label_macro_pins\
+	-lef $::env(TMP_DIR)/lvs.lef\
+	-netlist_def $::env(TMP_DIR)/lvs.def\
+	-pad_pin_name "PAD"
+
+
+run_magic
+
+# run_magic_drc
+
+run_magic_spice_export
+
+save_views       -lef_path $::env(magic_result_file_tag).lef \
+                 -def_path $::env(CURRENT_DEF) \
+                 -gds_path $::env(magic_result_file_tag).gds \
+                 -mag_path $::env(magic_result_file_tag).mag \
+                 -maglef_path $::env(magic_result_file_tag).lef.mag \
+				 -verilog_path $::env(TMP_DIR)/lvs.v \
+				 -spice_path $::env(magic_result_file_tag).spice \
+                 -save_path $save_path \
+                 -tag $::env(RUN_TAG)
+
+run_lvs $::env(magic_result_file_tag).spice $::env(TMP_DIR)/lvs.v
+
+calc_total_runtime
+generate_final_summary_report
--- a/openlane/chip_io_alt/padframe.cfg
+++ b/openlane/chip_io_alt/padframe.cfg
@ -0,0 +1,294 @@
+AREA 3588 5188 ;
+
+CORNER mgmt_corner\[0\] SW sky130_ef_io__corner_pad ;
+CORNER mgmt_corner\[1\] SE sky130_ef_io__corner_pad ;
+CORNER user1_corner NE sky130_ef_io__corner_pad ;
+CORNER user2_corner NW sky130_ef_io__corner_pad ;
+
+SPACE 178 ;
+PAD user2_analog_pad\[2\] N sky130_ef_io__analog_pad ;
+SPACE 182 ;
+PAD user2_analog_pad\[1\] N sky130_ef_io__analog_pad ;
+SPACE 182 ;
+PAD user2_analog_pad\[0\] N sky130_ef_io__analog_pad ;
+SPACE 130 ;
+PAD user2_analog_pad_with_clamp\[1\] N sky130_ef_io__top_power_hvc ;
+SPACE 89 ;
+PAD user2_analog_pad_with_clamp\[0\] N sky130_ef_io__top_power_hvc ;
+SPACE 135 ;
+PAD mgmt_vssio_hvclamp_pad\[1\] N sky130_ef_io__vssio_hvc_clamped_pad ;
+SPACE 120 ;
+PAD disconnect_vdda_0 N sky130_ef_io__disconnect_vdda_slice_5um ;
+SPACE 0 ;
+PAD disconnect_vccd_0 N sky130_ef_io__disconnect_vccd_slice_5um ;
+SPACE 0 ;
+PAD user1_analog_pad_with_clamp N sky130_ef_io__top_power_hvc ; 
+SPACE 328 ;
+PAD user1_analog_pad\[3\] N sky130_ef_io__analog_pad ;
+SPACE 182 ;
+PAD user1_analog_pad\[2\] N sky130_ef_io__analog_pad ;
+SPACE 177 ;
+PAD user1_vssa_hvclamp_pad\[0\] N sky130_ef_io__vssa_hvc_clamped_pad ;
+SPACE 182 ;
+PAD user1_analog_pad\[1\] N sky130_ef_io__analog_pad ;
+SPACE 178 ;
+
+
+PAD disconnect_vdda_1 E sky130_ef_io__disconnect_vdda_slice_5um ;
+SPACE 0 ;
+PAD disconnect_vccd_1 E sky130_ef_io__disconnect_vccd_slice_5um ;
+PAD mprj_pads.area1_io_pad\[0\] E sky130_ef_io__gpiov2_pad_wrapped ;
+SPACE 146 ;
+PAD mprj_pads.area1_io_pad\[1\] E sky130_ef_io__gpiov2_pad_wrapped ;
+SPACE 145 ;
+PAD mprj_pads.area1_io_pad\[2\] E sky130_ef_io__gpiov2_pad_wrapped ;
+SPACE 146 ;
+PAD mprj_pads.area1_io_pad\[3\] E sky130_ef_io__gpiov2_pad_wrapped ;
+SPACE 145 ;
+PAD mprj_pads.area1_io_pad\[4\] E sky130_ef_io__gpiov2_pad_wrapped ;
+SPACE 145 ;
+PAD mprj_pads.area1_io_pad\[5\] E sky130_ef_io__gpiov2_pad_wrapped ;
+SPACE 146 ;
+PAD mprj_pads.area1_io_pad\[6\] E sky130_ef_io__gpiov2_pad_wrapped ;
+SPACE 145 ;
+PAD user1_vssa_hvclamp_pad\[1\] E sky130_ef_io__vssa_hvc_clamped_pad ;
+SPACE 146 ;
+PAD user1_vssd_lvclmap_pad E sky130_ef_io__vssd_lvc_clamped3_pad ;
+SPACE 145 ;
+PAD user1_vdda_hvclamp_pad\[1\] E sky130_ef_io__vdda_hvc_clamped_pad ;
+SPACE 145 ;
+PAD mprj_pads.area1_io_pad\[7\] E sky130_ef_io__gpiov2_pad_wrapped ;
+SPACE 146 ;
+PAD mprj_pads.area1_io_pad\[8\] E sky130_ef_io__gpiov2_pad_wrapped ;
+SPACE 145 ;
+PAD mprj_pads.area1_io_pad\[9\] E sky130_ef_io__gpiov2_pad_wrapped ;
+SPACE 146 ;
+PAD mprj_pads.area1_io_pad\[10\] E sky130_ef_io__gpiov2_pad_wrapped ;
+SPACE 145 ;
+PAD mprj_pads.area1_io_pad\[11\] E sky130_ef_io__gpiov2_pad_wrapped ;
+SPACE 145 ;
+PAD mprj_pads.area1_io_pad\[12\] E sky130_ef_io__gpiov2_pad_wrapped ;
+SPACE 146 ;
+PAD user1_vdda_hvclamp_pad\[0\] E sky130_ef_io__vdda_hvc_clamped_pad ;
+SPACE 145 ;
+PAD mprj_pads.area1_io_pad\[13\] E sky130_ef_io__gpiov2_pad_wrapped ;
+SPACE 146 ;
+PAD user1_vccd_lvclamp_pad E sky130_ef_io__vccd_lvc_clamped3_pad ;
+SPACE 155 ;
+PAD user1_analog_pad\[0\] E sky130_ef_io__analog_pad ;
+SPACE 141 ;
+
+
+PAD bus_tie_1 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_2 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_3 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_4 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_5 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_6 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+
+PAD mgmt_vssa_hvclamp_pad S sky130_ef_io__vssa_hvc_clamped_pad ;
+
+PAD bus_tie_7 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_8 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_9 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_10 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_11 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_12 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+
+
+PAD resetb_pad S sky130_fd_io__top_xres4v2 ;
+
+PAD bus_tie_13 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_14 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_15 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_16 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_17 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_18 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+
+PAD clock_pad S sky130_ef_io__gpiov2_pad_wrapped ;
+
+PAD bus_tie_19 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_20 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_21 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_22 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_23 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_24 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+
+PAD mgmt_vssd_lvclmap_pad S sky130_ef_io__vssd_lvc_clamped_pad ;
+
+PAD bus_tie_25 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_26 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_27 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_28 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_29 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_30 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+
+PAD flash_csb_pad S sky130_ef_io__gpiov2_pad_wrapped ;
+
+PAD bus_tie_31 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_32 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_33 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_34 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_35 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_36 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+
+PAD flash_clk_pad S sky130_ef_io__gpiov2_pad_wrapped ;
+
+PAD bus_tie_37 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_38 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_39 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_40 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_41 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_42 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+
+PAD flash_io0_pad S sky130_ef_io__gpiov2_pad_wrapped ;
+
+PAD bus_tie_43 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_44 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_45 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_46 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_47 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_48 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+
+PAD flash_io1_pad S sky130_ef_io__gpiov2_pad_wrapped ;
+
+PAD bus_tie_49 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_50 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_51 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_52 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_53 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_54 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+
+PAD gpio_pad S sky130_ef_io__gpiov2_pad_wrapped ;
+
+PAD bus_tie_55 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_56 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_57 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_58 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_59 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_60 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+
+PAD mgmt_vssio_hvclamp_pad\[0\] S sky130_ef_io__vssio_hvc_clamped_pad ;
+
+PAD bus_tie_61 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_62 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_63 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_64 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_65 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_66 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+
+PAD mgmt_vdda_hvclamp_pad S sky130_ef_io__vdda_hvc_clamped_pad ;
+
+PAD bus_tie_67 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_68 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_69 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_70 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_71 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+SPACE 0 ;
+PAD bus_tie_72 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
+
+PAD mgmt_vccd_lvclamp_pad W sky130_ef_io__vccd_lvc_clamped_pad ;
+SPACE 136 ;
+PAD mgmt_vddio_hvclamp_pad\[0\] W sky130_ef_io__vddio_hvc_clamped_pad ;
+SPACE 0 ;
+PAD disconnect_vdda_2 W sky130_ef_io__disconnect_vdda_slice_5um ;
+SPACE 0 ;
+PAD disconnect_vccd_2 W sky130_ef_io__disconnect_vccd_slice_5um ;
+SPACE 272 ;
+PAD mprj_pads.area2_io_pad\[12\] W sky130_ef_io__gpiov2_pad_wrapped ;
+SPACE 136 ;
+PAD mprj_pads.area2_io_pad\[11\] W sky130_ef_io__gpiov2_pad_wrapped ;
+SPACE 136 ;
+PAD mprj_pads.area2_io_pad\[10\] W sky130_ef_io__gpiov2_pad_wrapped ;
+SPACE 136 ;
+PAD mprj_pads.area2_io_pad\[9\] W sky130_ef_io__gpiov2_pad_wrapped ;
+SPACE 136 ;
+PAD mprj_pads.area2_io_pad\[8\] W sky130_ef_io__gpiov2_pad_wrapped ;
+SPACE 136 ;
+PAD mprj_pads.area2_io_pad\[7\] W sky130_ef_io__gpiov2_pad_wrapped ;
+SPACE 136 ;
+PAD user2_vssd_lvclmap_pad W sky130_ef_io__vssd_lvc_clamped3_pad ;
+SPACE 136 ;
+PAD user2_vdda_hvclamp_pad W sky130_ef_io__vdda_hvc_clamped_pad ;
+SPACE 136 ;
+PAD mprj_pads.area2_io_pad\[6\] W sky130_ef_io__gpiov2_pad_wrapped ;
+SPACE 136 ;
+PAD mprj_pads.area2_io_pad\[5\] W sky130_ef_io__gpiov2_pad_wrapped ;
+SPACE 136 ;
+PAD mprj_pads.area2_io_pad\[4\] W sky130_ef_io__gpiov2_pad_wrapped ;
+SPACE 136 ;
+PAD mprj_pads.area2_io_pad\[3\] W sky130_ef_io__gpiov2_pad_wrapped ;
+SPACE 136 ;
+PAD mprj_pads.area2_io_pad\[2\] W sky130_ef_io__gpiov2_pad_wrapped ;
+SPACE 136 ;
+PAD mprj_pads.area2_io_pad\[1\] W sky130_ef_io__gpiov2_pad_wrapped ;
+SPACE 136 ;
+PAD mprj_pads.area2_io_pad\[0\] W sky130_ef_io__gpiov2_pad_wrapped ;
+SPACE 136 ;
+PAD user2_vssa_hvclamp_pad W sky130_ef_io__vssa_hvc_clamped_pad ;
+SPACE 136 ;
+PAD mgmt_vddio_hvclamp_pad\[1\] W sky130_ef_io__vddio_hvc_clamped_pad ;
+SPACE 136 ;
+PAD user2_vccd_lvclamp_pad W sky130_ef_io__vccd_lvc_clamped3_pad ;
+SPACE 141 ;
+PAD user2_analog_pad\[3\] W sky130_ef_io__analog_pad ;
+SPACE 137 ;
--- a/openlane/user_analog_project_wrapper/config.tcl
+++ b/openlane/user_analog_project_wrapper/config.tcl
@ -0,0 +1,39 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+set script_dir [file dirname [file normalize [info script]]]
+source $script_dir/fixed_wrapper_cfgs.tcl
+
+set ::env(DESIGN_NAME) user_analog_project_wrapper
+
+set ::env(GLB_RT_OBS) "met1 0 0 $::env(DIE_AREA),\
+					   met2 0 0 $::env(DIE_AREA),\
+					   met3 0 0 $::env(DIE_AREA),\
+					   met4 0 0 $::env(DIE_AREA),\
+					   met5 0 0 $::env(DIE_AREA)"
+
+set ::env(CLOCK_PORT) "wb_clk_i"
+set ::env(CLOCK_NET)  "wb_clk_i"
+
+set ::env(CLOCK_PERIOD) "10"
+
+set ::env(DIODE_INSERTION_STRATEGY) 0
+set ::env(SYNTH_DEFINES) "USE_POWER_PINS"
+
+set ::env(MAGIC_WRITE_FULL_LEF) 1
+
+set ::env(VERILOG_FILES) "\
+	$script_dir/../../verilog/rtl/defines.v \
+	$script_dir/../../verilog/rtl/__user_analog_project_wrapper.v"
--- a/openlane/user_analog_project_wrapper/fixed_wrapper_cfgs.tcl
+++ b/openlane/user_analog_project_wrapper/fixed_wrapper_cfgs.tcl
@ -0,0 +1,41 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+# DON'T TOUCH THE FOLLOWING SECTIONS
+
+# This makes sure that the core rings are outside the boundaries
+# of your block.
+set ::env(MAGIC_ZEROIZE_ORIGIN) 0
+
+# Area Configurations. DON'T TOUCH.
+set ::env(FP_SIZING) absolute
+set ::env(DIE_AREA) "0 0 2920 3520"
+
+set ::env(RUN_CVC) 0
+
+# Pin Configurations. DON'T TOUCH
+set ::unit 2.4
+set ::env(FP_IO_VLENGTH) $::unit
+set ::env(FP_IO_HLENGTH) $::unit
+
+set ::env(FP_IO_VTHICKNESS_MULT) 4
+set ::env(FP_IO_HTHICKNESS_MULT) 4
+
+# Power & Pin Configurations. DON'T TOUCH.
+set ::env(FP_PDN_CORE_RING) 0
+
+set ::env(VDD_NETS) [list {vccd1} {vccd2} {vdda1} {vdda2}]
+set ::env(GND_NETS) [list {vssd1} {vssd2} {vssa1} {vssa2}]
+set ::env(SYNTH_USE_PG_PINS_DEFINES) "USE_POWER_PINS"
--- a/openlane/user_analog_project_wrapper/interactive.tcl
+++ b/openlane/user_analog_project_wrapper/interactive.tcl
@ -0,0 +1,65 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+package require openlane
+set script_dir [file dirname [file normalize [info script]]]
+
+prep -design $script_dir -tag user_analog_project_wrapper_empty -overwrite
+set save_path $script_dir/../..
+
+verilog_elaborate
+
+init_floorplan
+
+# making it "empty"
+remove_nets -input $::env(CURRENT_DEF)
+remove_components -input $::env(CURRENT_DEF)
+
+set ::env(SAVE_DEF) [index_file $::env(ioPlacer_tmp_file_tag).def]
+try_catch openroad -exit $script_dir/or_ioplace.tcl |& tee $::env(TERMINAL_OUTPUT) [index_file $::env(ioPlacer_log_file_tag).log 0]
+set_def $::env(SAVE_DEF)
+
+# rename "duplicate" pins
+exec /bin/bash $script_dir/../../utils/rename_pins.sh $::env(SAVE_DEF) "io_analog_1_4,io_analog_1_5,io_analog_1_6,vdda1_1,vdda1_2,vdda1_3,vdda2_1,vssa1_1,vssa1_2,vssa1_3,vssa2_1,vccd1_1,vccd2_1,vssd1_1,vssd2_1" "io_analog\[4\],io_analog\[5\],io_analog\[6\],vdda1,vdda1,vdda1,vdda2,vssa1,vssa1,vssa1,vssa2,vccd1,vccd2,vssd1,vssd2"
+
+run_magic
+
+run_magic_drc
+
+save_views       -lef_path $::env(magic_result_file_tag).lef \
+                 -def_path $::env(CURRENT_DEF) \
+                 -gds_path $::env(magic_result_file_tag).gds \
+                 -mag_path $::env(magic_result_file_tag).mag \
+                 -save_path $save_path \
+                 -tag $::env(RUN_TAG)
+
+# make pin labels visible in the magview
+exec /bin/bash $script_dir/../../utils/export_pin_labels.sh $script_dir/../../mag/$::env(RUN_TAG).mag 0 3498 2920 3520 0 -20 2920 4 >@stdout 2>@stderr
+
+# Draw Boundary in the magview
+exec /bin/bash $script_dir/../../utils/draw_boundary.sh $script_dir/../../mag/$::env(RUN_TAG).mag 0 0 2920 3520  >@stdout 2>@stderr
+
+# produce "obstructed" LEF to be used for routing
+set gap 0.4
+set llx [expr [lindex $::env(DIE_AREA) 0]-$gap]
+set lly [expr [lindex $::env(DIE_AREA) 1]-$gap]
+set urx [expr [lindex $::env(DIE_AREA) 2]+$gap]
+set ury [expr [lindex $::env(DIE_AREA) 3]+$gap]
+exec python3 $::env(OPENLANE_ROOT)/scripts/rectify.py $llx $lly $urx $ury \
+	< $::env(magic_result_file_tag).lef \
+	| python3 $::env(OPENLANE_ROOT)/scripts/obs.py {*}$::env(DIE_AREA) li1 met1 met2 met3 \
+	| python3 $::env(OPENLANE_ROOT)/scripts/obs.py -42.88 -37.53 2962.50 3557.21 met4 met5 \
+	> $::env(magic_result_file_tag).obstructed.lef
+file copy -force $::env(magic_result_file_tag).obstructed.lef $save_path/lef
--- a/openlane/user_analog_project_wrapper/or_ioplace.tcl
+++ b/openlane/user_analog_project_wrapper/or_ioplace.tcl