mirror of https://github.com/efabless/caravel.git
[DATA] Add chip_io views with the fixed clamped3 pad
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manarabdelaty
parent
b5fe87304a
commit
1f55f46596
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# SPDX-FileCopyrightText: 2020 Efabless Corporation
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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# SPDX-License-Identifier: Apache-2.0
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set script_dir [file dirname [file normalize [info script]]]
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set ::env(DESIGN_NAME) chip_io
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set ::env(DESIGN_IS_PADFRAME) 1
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set ::env(STD_CELL_LIBRARY_OPT) $::env(STD_CELL_LIBRARY)
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set ::env(VERILOG_FILES) "\
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$script_dir/../../verilog/rtl/defines.v\
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$script_dir/../../verilog/rtl/pads.v\
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$script_dir/../../verilog/rtl/mprj_io.v\
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$script_dir/../../verilog/rtl/chip_io.v"
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set ::env(USE_GPIO_PADS) 1
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# The removal of this line is pending the IO verilog files being parsable by yosys...
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set ::env(VERILOG_FILES_BLACKBOX) "\
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$script_dir/../../verilog/stubs/sky130_fd_io__top_xres4v2.v\
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$script_dir/../../verilog/stubs/sky130_fd_io__top_ground_lvc_wpad.v\
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$script_dir/../../verilog/stubs/sky130_fd_io__top_power_lvc_wpad.v"
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set ::env(GPIO_PADS_VERILOG) "\
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$::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/verilog/sky130_ef_io.v"
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## Synthesis
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set ::env(SYNTH_FLAT_TOP) 1
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set ::env(SYNTH_READ_BLACKBOX_LIB) 1
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## Floorplan
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set ::env(FP_SIZING) absolute
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set fd [open "$script_dir/../chip_dimensions.txt" "r"]
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set ::env(DIE_AREA) [read $fd]
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close $fd
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## Diode Insertion
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set ::env(DIODE_INSERTION_STRATEGY) 0
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## Routing
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set ::env(GLB_RT_MAXLAYER) 4
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set ::env(GLB_RT_UNIDIRECTIONAL) 0
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set ::env(GLB_RT_ALLOW_CONGESTION) 1
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set ::env(GLB_RT_OVERFLOW_ITERS) 150
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## LVS
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set ::env(LVS_CONNECT_BY_LABEL) 1
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# "There are areas of ntap and ptap and/or low voltage and high voltage that magic can't parse properly from the GDS. \
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Those aren't parts of devices, so they don't affect the extraction, but they may raise overlap errors". Tim E.
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set ::env(QUIT_ON_ILLEGAL_OVERLAPS) 0
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set ::env(MAGIC_WRITE_FULL_LEF) 1
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# SPDX-FileCopyrightText: 2020 Efabless Corporation
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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# SPDX-License-Identifier: Apache-2.0
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package require openlane
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set script_dir [file dirname [file normalize [info script]]]
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set save_path $script_dir/../..
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# FOR LVS AND CREATING PORT LABELS
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set ::env(USE_GPIO_ROUTING_LEF) 0
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prep -design $script_dir -tag chip_io_lvs -overwrite
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set ::env(SYNTH_DEFINES) ""
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verilog_elaborate
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#init_floorplan
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#file copy -force $::env(CURRENT_DEF) $::env(TMP_DIR)/lvs.def
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file copy -force $::env(CURRENT_NETLIST) $::env(TMP_DIR)/lvs.v
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# ACTUAL CHIP INTEGRATION
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set ::env(USE_GPIO_ROUTING_LEF) 1
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prep -design $script_dir -tag chip_io -overwrite
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#file copy $script_dir/runs/chip_io_lvs/tmp/merged_unpadded.lef $::env(TMP_DIR)/lvs.lef
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#file copy $script_dir/runs/chip_io_lvs/tmp/lvs.def $::env(TMP_DIR)/lvs.def
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file copy $script_dir/runs/chip_io_lvs/tmp/lvs.v $::env(TMP_DIR)/lvs.v
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set ::env(SYNTH_DEFINES) "TOP_ROUTING"
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verilog_elaborate
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init_floorplan
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puts_info "Generating pad frame"
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exec python3 $::env(SCRIPTS_DIR)/padringer.py\
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--def-netlist $::env(CURRENT_DEF)\
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--design $::env(DESIGN_NAME)\
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--lefs $::env(TECH_LEF) {*}$::env(GPIO_PADS_LEF)\
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-cfg $script_dir/padframe.cfg\
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--working-dir $::env(TMP_DIR)\
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-o $::env(RESULTS_DIR)/floorplan/padframe.def |& tee $::env(TERMINAL_OUTPUT) $::env(LOG_DIR)/padringer.log
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puts_info "Generated pad frame"
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set_def $::env(RESULTS_DIR)/floorplan/padframe.def
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# modify to a different file
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remove_pins -input $::env(CURRENT_DEF)
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remove_empty_nets -input $::env(CURRENT_DEF)
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set core_obs "
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met1 225 235 3365 4950, \
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met2 225 235 3365 4950, \
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met3 225 235 3365 4950, \
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met4 225 235 3365 4955, \
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met5 225 235 3365 4955
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"
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set gpio_m3_pins_north "met3 469.965 4972.585 3200.4450 4988.785"
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set gpio_m3_pins_west_0 "met3 198.400 1002.125 215.185 2202.125"
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set gpio_m3_pins_west_1 "met3 198.400 2726.820 215.185 4126.82"
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set gpio_m3_pins_west_2 "met3 198.400 4641.655 215.185 4755.305"
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set gpio_m3_pins_east "met3 3370.840 600.050 3387.01 4731.99"
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#set vssa_m3_east "met3 3387.79500 2102.44500 3390.02500 2130.06500"
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#set vssa_m2_east "met2 3387.67500 2128.50000 3388.00500 2152.50000"
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set ::env(GLB_RT_OBS) "$core_obs"
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set ::env(GLB_RT_OBS) "\
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$core_obs, \
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$gpio_m3_pins_north, \
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$gpio_m3_pins_west_0, \
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$gpio_m3_pins_west_1, \
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$gpio_m3_pins_west_2, \
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$gpio_m3_pins_east
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"
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try_catch python3 $::env(SCRIPTS_DIR)/add_def_obstructions.py \
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--input-def $::env(CURRENT_DEF) \
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--lef $::env(MERGED_LEF) \
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--obstructions $::env(GLB_RT_OBS) \
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--output [file rootname $::env(CURRENT_DEF)].obs.def |& tee $::env(TERMINAL_OUTPUT) $::env(LOG_DIR)/obs.log
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set_def [file rootname $::env(CURRENT_DEF)].obs.def
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li1_hack_start
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global_routing
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detailed_routing
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li1_hack_end
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label_macro_pins\
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-lef $::env(TMP_DIR)/lvs.lef\
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-netlist_def $::env(TMP_DIR)/lvs.def\
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-pad_pin_name "PAD"
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run_magic
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# run_magic_drc
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run_magic_spice_export
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save_views -lef_path $::env(magic_result_file_tag).lef \
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-def_path $::env(CURRENT_DEF) \
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-gds_path $::env(magic_result_file_tag).gds \
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-mag_path $::env(magic_result_file_tag).mag \
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-maglef_path $::env(magic_result_file_tag).lef.mag \
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-verilog_path $::env(TMP_DIR)/lvs.v \
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-spice_path $::env(magic_result_file_tag).spice \
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-save_path $save_path \
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-tag $::env(RUN_TAG)
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run_lvs $::env(magic_result_file_tag).spice $::env(TMP_DIR)/lvs.v
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AREA 3588 5188 ;
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CORNER mgmt_corner\[0\] SW sky130_ef_io__corner_pad ;
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CORNER mgmt_corner\[1\] SE sky130_ef_io__corner_pad ;
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CORNER user1_corner NE sky130_ef_io__corner_pad ;
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CORNER user2_corner NW sky130_ef_io__corner_pad ;
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SPACE 176 ;
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PAD mprj_pads.area2_io_pad\[4\] N sky130_ef_io__gpiov2_pad_wrapped ;
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SPACE 177 ;
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PAD mprj_pads.area2_io_pad\[3\] N sky130_ef_io__gpiov2_pad_wrapped ;
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SPACE 177 ;
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PAD mprj_pads.area2_io_pad\[2\] N sky130_ef_io__gpiov2_pad_wrapped ;
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SPACE 177 ;
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PAD mprj_pads.area2_io_pad\[1\] N sky130_ef_io__gpiov2_pad_wrapped ;
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SPACE 178 ;
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PAD mprj_pads.area2_io_pad\[0\] N sky130_ef_io__gpiov2_pad_wrapped ;
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SPACE 177 ;
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PAD mgmt_vssio_hvclamp_pad\[1\] N sky130_ef_io__vssio_hvc_clamped_pad ;
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SPACE 0 ;
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PAD disconnect_vdda_0 N sky130_ef_io__disconnect_vdda_slice_5um ;
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SPACE 0 ;
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PAD disconnect_vccd_0 N sky130_ef_io__disconnect_vccd_slice_5um ;
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SPACE 167 ;
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PAD mprj_pads.area1_io_pad\[18\] N sky130_ef_io__gpiov2_pad_wrapped ;
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SPACE 365 ;
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PAD mprj_pads.area1_io_pad\[17\] N sky130_ef_io__gpiov2_pad_wrapped ;
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PAD mprj_pads.area1_io_pad\[16\] N sky130_ef_io__gpiov2_pad_wrapped ;
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PAD user1_vssa_hvclamp_pad\[0\] N sky130_ef_io__vssa_hvc_clamped_pad ;
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PAD mprj_pads.area1_io_pad\[15\] N sky130_ef_io__gpiov2_pad_wrapped ;
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SPACE 178 ;
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PAD disconnect_vdda_1 E sky130_ef_io__disconnect_vdda_slice_5um ;
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SPACE 0 ;
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PAD disconnect_vccd_1 E sky130_ef_io__disconnect_vccd_slice_5um ;
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PAD mprj_pads.area1_io_pad\[0\] E sky130_ef_io__gpiov2_pad_wrapped ;
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PAD mprj_pads.area1_io_pad\[1\] E sky130_ef_io__gpiov2_pad_wrapped ;
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PAD mprj_pads.area1_io_pad\[2\] E sky130_ef_io__gpiov2_pad_wrapped ;
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PAD mprj_pads.area1_io_pad\[3\] E sky130_ef_io__gpiov2_pad_wrapped ;
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PAD mprj_pads.area1_io_pad\[4\] E sky130_ef_io__gpiov2_pad_wrapped ;
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PAD mprj_pads.area1_io_pad\[5\] E sky130_ef_io__gpiov2_pad_wrapped ;
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PAD mprj_pads.area1_io_pad\[6\] E sky130_ef_io__gpiov2_pad_wrapped ;
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PAD user1_vssa_hvclamp_pad\[1\] E sky130_ef_io__vssa_hvc_clamped_pad ;
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PAD user1_vssd_lvclamp_pad E sky130_ef_io__vssd_lvc_clamped3_pad ;
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PAD user1_vdda_hvclamp_pad\[1\] E sky130_ef_io__vdda_hvc_clamped_pad ;
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PAD mprj_pads.area1_io_pad\[7\] E sky130_ef_io__gpiov2_pad_wrapped ;
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PAD mprj_pads.area1_io_pad\[8\] E sky130_ef_io__gpiov2_pad_wrapped ;
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PAD mprj_pads.area1_io_pad\[9\] E sky130_ef_io__gpiov2_pad_wrapped ;
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PAD mprj_pads.area1_io_pad\[10\] E sky130_ef_io__gpiov2_pad_wrapped ;
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PAD mprj_pads.area1_io_pad\[11\] E sky130_ef_io__gpiov2_pad_wrapped ;
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PAD mprj_pads.area1_io_pad\[12\] E sky130_ef_io__gpiov2_pad_wrapped ;
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PAD user1_vdda_hvclamp_pad\[0\] E sky130_ef_io__vdda_hvc_clamped_pad ;
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PAD mprj_pads.area1_io_pad\[13\] E sky130_ef_io__gpiov2_pad_wrapped ;
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PAD user1_vccd_lvclamp_pad E sky130_ef_io__vccd_lvc_clamped3_pad ;
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PAD mprj_pads.area1_io_pad\[14\] E sky130_ef_io__gpiov2_pad_wrapped ;
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PAD bus_tie_1 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
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SPACE 0 ;
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PAD bus_tie_2 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
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SPACE 0 ;
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PAD bus_tie_3 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
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SPACE 0 ;
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PAD bus_tie_4 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
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SPACE 0 ;
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PAD bus_tie_5 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
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SPACE 0 ;
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PAD bus_tie_6 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
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PAD mgmt_vssa_hvclamp_pad S sky130_ef_io__vssa_hvc_clamped_pad ;
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PAD bus_tie_7 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
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SPACE 0 ;
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PAD bus_tie_8 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
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SPACE 0 ;
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PAD bus_tie_9 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
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SPACE 0 ;
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PAD bus_tie_10 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
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SPACE 0 ;
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PAD bus_tie_11 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
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SPACE 0 ;
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PAD bus_tie_12 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
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PAD resetb_pad S sky130_fd_io__top_xres4v2 ;
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PAD bus_tie_13 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
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SPACE 0 ;
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PAD bus_tie_14 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
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SPACE 0 ;
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PAD bus_tie_15 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
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SPACE 0 ;
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PAD bus_tie_16 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
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SPACE 0 ;
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PAD bus_tie_17 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
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SPACE 0 ;
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PAD bus_tie_18 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
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PAD clock_pad S sky130_ef_io__gpiov2_pad_wrapped ;
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PAD bus_tie_19 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
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SPACE 0 ;
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PAD bus_tie_20 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
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SPACE 0 ;
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PAD bus_tie_21 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
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SPACE 0 ;
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PAD bus_tie_22 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
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SPACE 0 ;
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PAD bus_tie_23 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
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SPACE 0 ;
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PAD bus_tie_24 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
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PAD mgmt_vssd_lvclamp_pad S sky130_ef_io__vssd_lvc_clamped_pad ;
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PAD bus_tie_25 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
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SPACE 0 ;
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PAD bus_tie_26 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
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SPACE 0 ;
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PAD bus_tie_27 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
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SPACE 0 ;
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PAD bus_tie_28 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
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SPACE 0 ;
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PAD bus_tie_29 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
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SPACE 0 ;
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PAD bus_tie_30 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
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PAD flash_csb_pad S sky130_ef_io__gpiov2_pad_wrapped ;
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PAD bus_tie_31 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
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SPACE 0 ;
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PAD bus_tie_32 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
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SPACE 0 ;
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PAD bus_tie_33 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
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SPACE 0 ;
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PAD bus_tie_34 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
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SPACE 0 ;
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PAD bus_tie_35 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
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SPACE 0 ;
|
||||
PAD bus_tie_36 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
|
||||
|
||||
PAD flash_clk_pad S sky130_ef_io__gpiov2_pad_wrapped ;
|
||||
|
||||
PAD bus_tie_37 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
|
||||
SPACE 0 ;
|
||||
PAD bus_tie_38 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
|
||||
SPACE 0 ;
|
||||
PAD bus_tie_39 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
|
||||
SPACE 0 ;
|
||||
PAD bus_tie_40 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
|
||||
SPACE 0 ;
|
||||
PAD bus_tie_41 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
|
||||
SPACE 0 ;
|
||||
PAD bus_tie_42 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
|
||||
|
||||
PAD flash_io0_pad S sky130_ef_io__gpiov2_pad_wrapped ;
|
||||
|
||||
PAD bus_tie_43 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
|
||||
SPACE 0 ;
|
||||
PAD bus_tie_44 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
|
||||
SPACE 0 ;
|
||||
PAD bus_tie_45 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
|
||||
SPACE 0 ;
|
||||
PAD bus_tie_46 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
|
||||
SPACE 0 ;
|
||||
PAD bus_tie_47 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
|
||||
SPACE 0 ;
|
||||
PAD bus_tie_48 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
|
||||
|
||||
PAD flash_io1_pad S sky130_ef_io__gpiov2_pad_wrapped ;
|
||||
|
||||
PAD bus_tie_49 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
|
||||
SPACE 0 ;
|
||||
PAD bus_tie_50 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
|
||||
SPACE 0 ;
|
||||
PAD bus_tie_51 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
|
||||
SPACE 0 ;
|
||||
PAD bus_tie_52 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
|
||||
SPACE 0 ;
|
||||
PAD bus_tie_53 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
|
||||
SPACE 0 ;
|
||||
PAD bus_tie_54 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
|
||||
|
||||
PAD gpio_pad S sky130_ef_io__gpiov2_pad_wrapped ;
|
||||
|
||||
PAD bus_tie_55 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
|
||||
SPACE 0 ;
|
||||
PAD bus_tie_56 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
|
||||
SPACE 0 ;
|
||||
PAD bus_tie_57 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
|
||||
SPACE 0 ;
|
||||
PAD bus_tie_58 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
|
||||
SPACE 0 ;
|
||||
PAD bus_tie_59 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
|
||||
SPACE 0 ;
|
||||
PAD bus_tie_60 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
|
||||
|
||||
PAD mgmt_vssio_hvclamp_pad\[0\] S sky130_ef_io__vssio_hvc_clamped_pad ;
|
||||
|
||||
PAD bus_tie_61 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
|
||||
SPACE 0 ;
|
||||
PAD bus_tie_62 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
|
||||
SPACE 0 ;
|
||||
PAD bus_tie_63 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
|
||||
SPACE 0 ;
|
||||
PAD bus_tie_64 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
|
||||
SPACE 0 ;
|
||||
PAD bus_tie_65 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
|
||||
SPACE 0 ;
|
||||
PAD bus_tie_66 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
|
||||
|
||||
PAD mgmt_vdda_hvclamp_pad S sky130_ef_io__vdda_hvc_clamped_pad ;
|
||||
|
||||
PAD bus_tie_67 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
|
||||
SPACE 0 ;
|
||||
PAD bus_tie_68 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
|
||||
SPACE 0 ;
|
||||
PAD bus_tie_69 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
|
||||
SPACE 0 ;
|
||||
PAD bus_tie_70 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
|
||||
SPACE 0 ;
|
||||
PAD bus_tie_71 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
|
||||
SPACE 0 ;
|
||||
PAD bus_tie_72 S sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um ;
|
||||
|
||||
PAD mgmt_vccd_lvclamp_pad W sky130_ef_io__vccd_lvc_clamped_pad ;
|
||||
PAD mgmt_vddio_hvclamp_pad\[0\] W sky130_ef_io__vddio_hvc_clamped_pad ;
|
||||
PAD disconnect_vdda_2 W sky130_ef_io__disconnect_vdda_slice_5um ;
|
||||
SPACE 0 ;
|
||||
PAD disconnect_vccd_2 W sky130_ef_io__disconnect_vccd_slice_5um ;
|
||||
PAD mprj_pads.area2_io_pad\[18\] W sky130_ef_io__gpiov2_pad_wrapped ;
|
||||
PAD mprj_pads.area2_io_pad\[17\] W sky130_ef_io__gpiov2_pad_wrapped ;
|
||||
PAD mprj_pads.area2_io_pad\[16\] W sky130_ef_io__gpiov2_pad_wrapped ;
|
||||
PAD mprj_pads.area2_io_pad\[15\] W sky130_ef_io__gpiov2_pad_wrapped ;
|
||||
PAD mprj_pads.area2_io_pad\[14\] W sky130_ef_io__gpiov2_pad_wrapped ;
|
||||
PAD mprj_pads.area2_io_pad\[13\] W sky130_ef_io__gpiov2_pad_wrapped ;
|
||||
PAD user2_vssd_lvclamp_pad W sky130_ef_io__vssd_lvc_clamped3_pad ;
|
||||
PAD user2_vdda_hvclamp_pad W sky130_ef_io__vdda_hvc_clamped_pad ;
|
||||
PAD mprj_pads.area2_io_pad\[12\] W sky130_ef_io__gpiov2_pad_wrapped ;
|
||||
PAD mprj_pads.area2_io_pad\[11\] W sky130_ef_io__gpiov2_pad_wrapped ;
|
||||
PAD mprj_pads.area2_io_pad\[10\] W sky130_ef_io__gpiov2_pad_wrapped ;
|
||||
PAD mprj_pads.area2_io_pad\[9\] W sky130_ef_io__gpiov2_pad_wrapped ;
|
||||
PAD mprj_pads.area2_io_pad\[8\] W sky130_ef_io__gpiov2_pad_wrapped ;
|
||||
PAD mprj_pads.area2_io_pad\[7\] W sky130_ef_io__gpiov2_pad_wrapped ;
|
||||
PAD mprj_pads.area2_io_pad\[6\] W sky130_ef_io__gpiov2_pad_wrapped ;
|
||||
PAD user2_vssa_hvclamp_pad W sky130_ef_io__vssa_hvc_clamped_pad ;
|
||||
PAD mgmt_vddio_hvclamp_pad\[1\] W sky130_ef_io__vddio_hvc_clamped_pad ;
|
||||
PAD user2_vccd_lvclamp_pad W sky130_ef_io__vccd_lvc_clamped3_pad ;
|
||||
PAD mprj_pads.area2_io_pad\[5\] W sky130_ef_io__gpiov2_pad_wrapped ;
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -308,18 +308,13 @@ module chip_io(
|
|||
// Management clock input pad
|
||||
`INPUT_PAD(clock, clock_core);
|
||||
|
||||
// Management GPIO pad
|
||||
`INOUT_PAD(
|
||||
gpio, gpio_in_core, gpio_out_core,
|
||||
gpio_inenb_core, gpio_outenb_core, dm_all);
|
||||
// Management GPIO pad
|
||||
`INOUT_PAD(gpio, gpio_in_core, gpio_out_core, gpio_inenb_core, gpio_outenb_core, dm_all);
|
||||
|
||||
// Management Flash SPI pads
|
||||
`INOUT_PAD(
|
||||
flash_io0, flash_io0_di_core, flash_io0_do_core,
|
||||
flash_io0_ieb_core, flash_io0_oeb_core, flash_io0_mode);
|
||||
`INOUT_PAD(
|
||||
flash_io1, flash_io1_di_core, flash_io1_do_core,
|
||||
flash_io1_ieb_core, flash_io1_oeb_core, flash_io1_mode);
|
||||
`INOUT_PAD(flash_io0, flash_io0_di_core, flash_io0_do_core, flash_io0_ieb_core, flash_io0_oeb_core, flash_io0_mode);
|
||||
|
||||
`INOUT_PAD(flash_io1, flash_io1_di_core, flash_io1_do_core, flash_io1_ieb_core, flash_io1_oeb_core, flash_io1_mode);
|
||||
|
||||
`OUTPUT_PAD(flash_csb, flash_csb_core, flash_csb_ieb_core, flash_csb_oeb_core);
|
||||
`OUTPUT_PAD(flash_clk, flash_clk_core, flash_clk_ieb_core, flash_clk_oeb_core);
|
||||
|
|
|
|||
Loading…
Reference in New Issue