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caravel
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[RTL] Fix power connection to HK/digital_pll/caravel clocking, also fix resetb connection

This commit is contained in:
manarabdelaty 2021-11-17 13:17:23 +02:00
parent 1b300d7b59
commit b5fe87304a
1 changed files with 10 additions and 10 deletions
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20
verilog/rtl/caravel.v
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@ -606,14 +606,14 @@ module caravel (
caravel_clocking clocking(
`ifdef USE_POWER_PINS
.VPWR(VPWR),
.VGND(VGND),
.VPWR(vccd_core),
.VGND(vssd_core),
`endif
.ext_clk_sel(ext_clk_sel),
.ext_clk(clock_core),
.pll_clk(pll_clk),
.pll_clk90(pll_clk90),
.resetb(resetb),
.resetb(rstb_h),
.sel(spi_pll_sel),
.sel2(spi_pll90_sel),
.ext_reset(ext_reset), // From housekeeping SPI
@ -625,11 +625,11 @@ module caravel (
// DCO/Digital Locked Loop
digital_pll pll (
`ifdef USE_POWER_PINS
.VPWR(VPWR),
.VGND(VGND),
`endif
.resetb(resetb),
`ifdef USE_POWER_PINS
.VPWR(vccd_core),
.VGND(vssd_core),
`endif
.resetb(rstb_h),
.enable(spi_pll_ena),
.osc(clock_core),
.clockp({pll_clk, pll_clk90}),
@ -642,8 +642,8 @@ module caravel (
housekeeping housekeeping (
`ifdef USE_POWER_PINS
.VPWR(VPWR),
.VGND(VGND),
.VPWR(vccd_core),
.VGND(vssd_core),
`endif
.wb_clk_i(caravel_clk),