mirror of https://github.com/efabless/caravel.git
[DATA] Add digital user project wrapper
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manarabdelaty
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# SPDX-FileCopyrightText: 2020 Efabless Corporation
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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# SPDX-License-Identifier: Apache-2.0
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set script_dir [file dirname [file normalize [info script]]]
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source $script_dir/fixed_wrapper_cfgs.tcl
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source $script_dir/default_wrapper_cfgs.tcl
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set ::env(DESIGN_NAME) user_project_wrapper
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set ::env(FP_PDN_CHECK_NODES) 0
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set ::env(FP_PDN_ENABLE_RAILS) 0
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set ::env(GLB_RT_OBS) "met1 0 0 $::env(DIE_AREA),\
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met2 0 0 $::env(DIE_AREA),\
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met3 0 0 $::env(DIE_AREA),\
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met4 0 0 $::env(DIE_AREA),\
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met5 0 0 $::env(DIE_AREA)"
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set ::env(CLOCK_PORT) "user_clock2"
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set ::env(CLOCK_NET) "mprj.clk"
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set ::env(CLOCK_PERIOD) "10"
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set ::env(PL_OPENPHYSYN_OPTIMIZATIONS) 0
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set ::env(DIODE_INSERTION_STRATEGY) 0
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set ::env(MAGIC_WRITE_FULL_LEF) 0
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set ::env(VERILOG_FILES) "\
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$script_dir/../../verilog/rtl/defines.v \
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$script_dir/../../verilog/rtl/__user_project_wrapper.v"
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# SPDX-FileCopyrightText: 2020 Efabless Corporation
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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# SPDX-License-Identifier: Apache-2.0
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# THE FOLLOWING SECTIONS CAN BE CHANGED IF NEEDED
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# PDN Pitch
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set ::env(FP_PDN_VPITCH) 180
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set ::env(FP_PDN_HPITCH) $::env(FP_PDN_VPITCH)
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# PDN Offset
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set ::env(FP_PDN_VOFFSET) 5
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set ::env(FP_PDN_HOFFSET) $::env(FP_PDN_VOFFSET)
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# SPDX-FileCopyrightText: 2020 Efabless Corporation
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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# SPDX-License-Identifier: Apache-2.0
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# DON'T TOUCH THE FOLLOWING SECTIONS
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set script_dir [file dirname [file normalize [info script]]]
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# This makes sure that the core rings are outside the boundaries
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# of your block.
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set ::env(MAGIC_ZEROIZE_ORIGIN) 0
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# Area Configurations. DON'T TOUCH.
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set ::env(FP_SIZING) absolute
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set ::env(DIE_AREA) "0 0 2920 3520"
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set ::env(RUN_CVC) 0
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# Pin Configurations. DON'T TOUCH
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set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
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set ::unit 2.4
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set ::env(FP_IO_VEXTEND) [expr 2*$::unit]
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set ::env(FP_IO_HEXTEND) [expr 2*$::unit]
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set ::env(FP_IO_VLENGTH) $::unit
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set ::env(FP_IO_HLENGTH) $::unit
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set ::env(FP_IO_VTHICKNESS_MULT) 4
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set ::env(FP_IO_HTHICKNESS_MULT) 4
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# Power & Pin Configurations. DON'T TOUCH.
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set ::env(FP_PDN_CORE_RING) 1
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set ::env(FP_PDN_CORE_RING_VWIDTH) 3.1
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set ::env(FP_PDN_CORE_RING_HWIDTH) 3.1
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set ::env(FP_PDN_CORE_RING_VOFFSET) 14
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set ::env(FP_PDN_CORE_RING_HOFFSET) $::env(FP_PDN_CORE_RING_VOFFSET)
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set ::env(FP_PDN_CORE_RING_VSPACING) 1.7
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set ::env(FP_PDN_CORE_RING_HSPACING) $::env(FP_PDN_CORE_RING_VSPACING)
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set ::env(FP_PDN_VWIDTH) 3.1
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set ::env(FP_PDN_HWIDTH) 3.1
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set ::env(FP_PDN_VSPACING) [expr 5*$::env(FP_PDN_CORE_RING_VWIDTH)]
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set ::env(FP_PDN_HSPACING) [expr 5*$::env(FP_PDN_CORE_RING_HWIDTH)]
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set ::env(VDD_NETS) [list {vccd1} {vccd2} {vdda1} {vdda2}]
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set ::env(GND_NETS) [list {vssd1} {vssd2} {vssa1} {vssa2}]
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set ::env(SYNTH_USE_PG_PINS_DEFINES) "USE_POWER_PINS"
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# SPDX-FileCopyrightText: 2020 Efabless Corporation
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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# SPDX-License-Identifier: Apache-2.0
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package require openlane
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set script_dir [file dirname [file normalize [info script]]]
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prep -design $script_dir -tag user_project_wrapper -overwrite
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set save_path $script_dir/../..
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verilog_elaborate
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set ::env(CURRENT_SDC) $::env(BASE_SDC_FILE)
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init_floorplan
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# making it "empty"
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remove_nets -input $::env(CURRENT_DEF)
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remove_components -input $::env(CURRENT_DEF)
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place_io_ol
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apply_route_obs
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run_power_grid_generation
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run_magic
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run_magic_drc
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save_views -lef_path $::env(magic_result_file_tag).lef \
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-def_path $::env(CURRENT_DEF) \
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-gds_path $::env(magic_result_file_tag).gds \
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-mag_path $::env(magic_result_file_tag).mag \
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-spice_path $::env(magic_result_file_tag).spice \
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-save_path $save_path \
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-tag $::env(RUN_TAG)
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#BUS_SORT
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#NR
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analog_io\[8\]
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io_in\[15\]
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io_out\[15\]
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io_oeb\[15\]
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analog_io\[9\]
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io_in\[16\]
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io_out\[16\]
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io_oeb\[16\]
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analog_io\[10\]
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io_in\[17\]
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io_out\[17\]
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io_oeb\[17\]
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analog_io\[11\]
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io_in\[18\]
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io_out\[18\]
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io_oeb\[18\]
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analog_io\[12\]
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io_in\[19\]
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io_out\[19\]
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io_oeb\[19\]
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analog_io\[13\]
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io_in\[20\]
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io_out\[20\]
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io_oeb\[20\]
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analog_io\[14\]
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io_in\[21\]
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io_out\[21\]
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io_oeb\[21\]
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analog_io\[15\]
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io_in\[22\]
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io_out\[22\]
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io_oeb\[22\]
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analog_io\[16\]
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io_in\[23\]
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io_out\[23\]
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io_oeb\[23\]
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#S
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wb_.*
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wbs_.*
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la_.*
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user_clock2
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user_irq.*
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#E
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io_in\[0\]
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io_out\[0\]
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io_oeb\[0\]
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io_in\[1\]
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io_out\[1\]
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io_oeb\[1\]
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io_in\[2\]
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io_out\[2\]
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io_oeb\[2\]
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io_in\[3\]
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io_out\[3\]
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io_oeb\[3\]
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io_in\[4\]
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io_out\[4\]
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io_oeb\[4\]
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io_in\[5\]
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io_out\[5\]
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io_oeb\[5\]
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io_in\[6\]
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io_out\[6\]
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io_oeb\[6\]
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analog_io\[0\]
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io_in\[7\]
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io_out\[7\]
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io_oeb\[7\]
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analog_io\[1\]
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io_in\[8\]
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io_out\[8\]
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io_oeb\[8\]
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analog_io\[2\]
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io_in\[9\]
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io_out\[9\]
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io_oeb\[9\]
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analog_io\[3\]
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io_in\[10\]
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io_out\[10\]
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io_oeb\[10\]
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analog_io\[4\]
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io_in\[11\]
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io_out\[11\]
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io_oeb\[11\]
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analog_io\[5\]
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io_in\[12\]
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io_out\[12\]
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io_oeb\[12\]
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analog_io\[6\]
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io_in\[13\]
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io_out\[13\]
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io_oeb\[13\]
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analog_io\[7\]
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io_in\[14\]
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io_out\[14\]
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io_oeb\[14\]
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#WR
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analog_io\[17\]
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io_in\[24\]
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io_out\[24\]
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io_oeb\[24\]
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analog_io\[18\]
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io_in\[25\]
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io_out\[25\]
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io_oeb\[25\]
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analog_io\[19\]
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io_in\[26\]
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io_out\[26\]
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io_oeb\[26\]
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analog_io\[20\]
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io_in\[27\]
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io_out\[27\]
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io_oeb\[27\]
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analog_io\[21\]
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io_in\[28\]
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io_out\[28\]
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io_oeb\[28\]
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analog_io\[22\]
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io_in\[29\]
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io_out\[29\]
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io_oeb\[29\]
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analog_io\[23\]
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io_in\[30\]
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io_out\[30\]
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io_oeb\[30\]
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analog_io\[24\]
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io_in\[31\]
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io_out\[31\]
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io_oeb\[31\]
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analog_io\[25\]
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io_in\[32\]
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io_out\[32\]
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io_oeb\[32\]
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analog_io\[26\]
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io_in\[33\]
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io_out\[33\]
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io_oeb\[33\]
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analog_io\[27\]
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io_in\[34\]
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io_out\[34\]
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io_oeb\[34\]
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analog_io\[28\]
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io_in\[35\]
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io_out\[35\]
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io_oeb\[35\]
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io_in\[36\]
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io_out\[36\]
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io_oeb\[36\]
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io_in\[37\]
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io_out\[37\]
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io_oeb\[37\]
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@ -0,0 +1 @@
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openlane 2021.09.09_03.00.48-70-g9ab04e4
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@ -0,0 +1,3 @@
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openlane cbb562bd43c5c410b1b498604803c3dd88a44856
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skywater-pdk c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
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open_pdks c5730b574461889c82858b08d12ba42423d9c2cb
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