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Merge pull request #217 from mo-hosni/buff_flash_clkrst 

Buff flash clkrst
This commit is contained in:
Marwan Abbas 2022-10-13 20:53:18 +02:00 committed by GitHub
parent 14856fea6d c771ef038b
commit f7299933ee
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VERSION 5.8 ;
DIVIDERCHAR "/" ;
BUSBITCHARS "[]" ;
DESIGN buff_flash_clkrst ;
UNITS DISTANCE MICRONS 1000 ;
DIEAREA ( 0 0 ) ( 40000 25000 ) ;
ROW ROW_0 unithd 1840 5440 N DO 78 BY 1 STEP 460 0 ;
ROW ROW_1 unithd 1840 8160 FS DO 78 BY 1 STEP 460 0 ;
ROW ROW_2 unithd 1840 10880 N DO 78 BY 1 STEP 460 0 ;
ROW ROW_3 unithd 1840 13600 FS DO 78 BY 1 STEP 460 0 ;
ROW ROW_4 unithd 1840 16320 N DO 78 BY 1 STEP 460 0 ;
TRACKS X 230 DO 87 STEP 460 LAYER li1 ;
TRACKS Y 170 DO 74 STEP 340 LAYER li1 ;
TRACKS X 170 DO 118 STEP 340 LAYER met1 ;
TRACKS Y 170 DO 74 STEP 340 LAYER met1 ;
TRACKS X 230 DO 87 STEP 460 LAYER met2 ;
TRACKS Y 230 DO 54 STEP 460 LAYER met2 ;
TRACKS X 340 DO 59 STEP 680 LAYER met3 ;
TRACKS Y 340 DO 37 STEP 680 LAYER met3 ;
TRACKS X 460 DO 43 STEP 920 LAYER met4 ;
TRACKS Y 460 DO 27 STEP 920 LAYER met4 ;
TRACKS X 1700 DO 12 STEP 3400 LAYER met5 ;
TRACKS Y 1700 DO 7 STEP 3400 LAYER met5 ;
GCELLGRID X 0 DO 5 STEP 6900 ;
GCELLGRID Y 0 DO 3 STEP 6900 ;
VIAS 3 ;
- via2_3_1600_480_1_5_320_320 + VIARULE M1M2_PR + CUTSIZE 150 150 + LAYERS met1 via met2 + CUTSPACING 170 170 + ENCLOSURE 85 165 55 85 + ROWCOL 1 5 ;
- via3_4_1600_480_1_4_400_400 + VIARULE M2M3_PR + CUTSIZE 200 200 + LAYERS met2 via2 met3 + CUTSPACING 200 200 + ENCLOSURE 40 85 65 65 + ROWCOL 1 4 ;
- via4_5_1600_480_1_4_400_400 + VIARULE M3M4_PR + CUTSIZE 200 200 + LAYERS met3 via3 met4 + CUTSPACING 200 200 + ENCLOSURE 90 60 100 65 + ROWCOL 1 4 ;
END VIAS
COMPONENTS 73 ;
- BUF\[0\] sky130_fd_sc_hd__clkbuf_8 + PLACED ( 5520 5440 ) N ;
- BUF\[10\] sky130_fd_sc_hd__clkbuf_8 + PLACED ( 28980 8160 ) FS ;
- BUF\[11\] sky130_fd_sc_hd__clkbuf_8 + PLACED ( 28980 13600 ) FS ;
- BUF\[12\] sky130_fd_sc_hd__clkbuf_8 + PLACED ( 28980 5440 ) FN ;
- BUF\[13\] sky130_fd_sc_hd__clkbuf_8 + PLACED ( 28980 16320 ) FN ;
- BUF\[14\] sky130_fd_sc_hd__clkbuf_8 + PLACED ( 21620 5440 ) FN ;
- BUF\[1\] sky130_fd_sc_hd__clkbuf_8 + PLACED ( 5520 16320 ) N ;
- BUF\[2\] sky130_fd_sc_hd__clkbuf_8 + PLACED ( 4600 8160 ) S ;
- BUF\[3\] sky130_fd_sc_hd__clkbuf_8 + PLACED ( 9200 13600 ) FS ;
- BUF\[4\] sky130_fd_sc_hd__clkbuf_8 + PLACED ( 8740 10880 ) FN ;
- BUF\[5\] sky130_fd_sc_hd__clkbuf_8 + PLACED ( 11500 8160 ) S ;
- BUF\[6\] sky130_fd_sc_hd__clkbuf_8 + PLACED ( 16100 13600 ) FS ;
- BUF\[7\] sky130_fd_sc_hd__clkbuf_8 + PLACED ( 18400 8160 ) FS ;
- BUF\[8\] sky130_fd_sc_hd__clkbuf_8 + PLACED ( 20700 10880 ) N ;
- BUF\[9\] sky130_fd_sc_hd__clkbuf_8 + PLACED ( 27600 10880 ) N ;
- FILLER_0_19 sky130_fd_sc_hd__decap_8 + SOURCE DIST + PLACED ( 10580 5440 ) N ;
- FILLER_0_27 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 14260 5440 ) N ;
- FILLER_0_29 sky130_ef_sc_hd__decap_12 + SOURCE DIST + PLACED ( 15180 5440 ) N ;
- FILLER_0_3 sky130_fd_sc_hd__decap_4 + SOURCE DIST + PLACED ( 3220 5440 ) N ;
- FILLER_0_41 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 20700 5440 ) N ;
- FILLER_0_54 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 26680 5440 ) N ;
- FILLER_0_57 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 28060 5440 ) N ;
- FILLER_0_7 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 5060 5440 ) N ;
- FILLER_0_70 sky130_fd_sc_hd__decap_4 + SOURCE DIST + PLACED ( 34040 5440 ) N ;
- FILLER_0_74 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 35880 5440 ) N ;
- FILLER_1_17 sky130_fd_sc_hd__decap_4 + SOURCE DIST + PLACED ( 9660 8160 ) FS ;
- FILLER_1_3 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 3220 8160 ) FS ;
- FILLER_1_32 sky130_fd_sc_hd__decap_4 + SOURCE DIST + PLACED ( 16560 8160 ) FS ;
- FILLER_1_47 sky130_fd_sc_hd__decap_8 + SOURCE DIST + PLACED ( 23460 8160 ) FS ;
- FILLER_1_55 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 27140 8160 ) FS ;
- FILLER_1_57 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 28060 8160 ) FS ;
- FILLER_1_70 sky130_fd_sc_hd__decap_4 + SOURCE DIST + PLACED ( 34040 8160 ) FS ;
- FILLER_1_74 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 35880 8160 ) FS ;
- FILLER_2_26 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 13800 10880 ) N ;
- FILLER_2_29 sky130_ef_sc_hd__decap_12 + SOURCE DIST + PLACED ( 15180 10880 ) N ;
- FILLER_2_3 sky130_ef_sc_hd__decap_12 + SOURCE DIST + PLACED ( 3220 10880 ) N ;
- FILLER_2_52 sky130_fd_sc_hd__decap_4 + SOURCE DIST + PLACED ( 25760 10880 ) N ;
- FILLER_2_67 sky130_fd_sc_hd__decap_8 + SOURCE DIST + PLACED ( 32660 10880 ) N ;
- FILLER_3_15 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 8740 13600 ) FS ;
- FILLER_3_27 sky130_fd_sc_hd__decap_4 + SOURCE DIST + PLACED ( 14260 13600 ) FS ;
- FILLER_3_3 sky130_ef_sc_hd__decap_12 + SOURCE DIST + PLACED ( 3220 13600 ) FS ;
- FILLER_3_42 sky130_ef_sc_hd__decap_12 + SOURCE DIST + PLACED ( 21160 13600 ) FS ;
- FILLER_3_54 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 26680 13600 ) FS ;
- FILLER_3_57 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 28060 13600 ) FS ;
- FILLER_3_70 sky130_fd_sc_hd__decap_4 + SOURCE DIST + PLACED ( 34040 13600 ) FS ;
- FILLER_3_74 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 35880 13600 ) FS ;
- FILLER_4_19 sky130_fd_sc_hd__decap_8 + SOURCE DIST + PLACED ( 10580 16320 ) N ;
- FILLER_4_27 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 14260 16320 ) N ;
- FILLER_4_29 sky130_ef_sc_hd__decap_12 + SOURCE DIST + PLACED ( 15180 16320 ) N ;
- FILLER_4_3 sky130_fd_sc_hd__decap_4 + SOURCE DIST + PLACED ( 3220 16320 ) N ;
- FILLER_4_41 sky130_ef_sc_hd__decap_12 + SOURCE DIST + PLACED ( 20700 16320 ) N ;
- FILLER_4_53 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 26220 16320 ) N ;
- FILLER_4_57 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 28060 16320 ) N ;
- FILLER_4_7 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 5060 16320 ) N ;
- FILLER_4_70 sky130_fd_sc_hd__decap_4 + SOURCE DIST + PLACED ( 34040 16320 ) N ;
- FILLER_4_74 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 35880 16320 ) N ;
- PHY_0 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 1840 5440 ) N ;
- PHY_1 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 36340 5440 ) FN ;
- PHY_2 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 1840 8160 ) FS ;
- PHY_3 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 36340 8160 ) S ;
- PHY_4 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 1840 10880 ) N ;
- PHY_5 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 36340 10880 ) FN ;
- PHY_6 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 1840 13600 ) FS ;
- PHY_7 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 36340 13600 ) S ;
- PHY_8 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 1840 16320 ) N ;
- PHY_9 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 36340 16320 ) FN ;
- TAP_10 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 14720 5440 ) N ;
- TAP_11 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 27600 5440 ) N ;
- TAP_12 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 27600 8160 ) FS ;
- TAP_13 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 14720 10880 ) N ;
- TAP_14 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 27600 13600 ) FS ;
- TAP_15 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 14720 16320 ) N ;
- TAP_16 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 27600 16320 ) N ;
END COMPONENTS
PINS 32 ;
- VGND + NET VGND + SPECIAL + DIRECTION INOUT + USE GROUND
+ PORT
+ LAYER met4 ( -800 -7040 ) ( 800 7040 )
+ LAYER met4 ( -9765 -7040 ) ( -8165 7040 )
+ LAYER met4 ( -18730 -7040 ) ( -17130 7040 )
+ LAYER met4 ( -27695 -7040 ) ( -26095 7040 )
+ FIXED ( 37695 12240 ) N ;
- VPWR + NET VPWR + SPECIAL + DIRECTION INOUT + USE POWER
+ PORT
+ LAYER met4 ( -800 -7040 ) ( 800 7040 )
+ LAYER met4 ( -9765 -7040 ) ( -8165 7040 )
+ LAYER met4 ( -18730 -7040 ) ( -17130 7040 )
+ LAYER met4 ( -27695 -7040 ) ( -26095 7040 )
+ FIXED ( 33215 12240 ) N ;
- in_n[0] + NET in_n[0] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER met2 ( -140 -2000 ) ( 140 2000 )
+ PLACED ( 10810 23000 ) N ;
- in_n[10] + NET in_n[10] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER met2 ( -140 -2000 ) ( 140 2000 )
+ PLACED ( 33810 23000 ) N ;
- in_n[11] + NET in_n[11] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER met2 ( -140 -2000 ) ( 140 2000 )
+ PLACED ( 36110 23000 ) N ;
- in_n[1] + NET in_n[1] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER met2 ( -140 -2000 ) ( 140 2000 )
+ PLACED ( 13110 23000 ) N ;
- in_n[2] + NET in_n[2] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER met2 ( -140 -2000 ) ( 140 2000 )
+ PLACED ( 15410 23000 ) N ;
- in_n[3] + NET in_n[3] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER met2 ( -140 -2000 ) ( 140 2000 )
+ PLACED ( 17710 23000 ) N ;
- in_n[4] + NET in_n[4] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER met2 ( -140 -2000 ) ( 140 2000 )
+ PLACED ( 20010 23000 ) N ;
- in_n[5] + NET in_n[5] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER met2 ( -140 -2000 ) ( 140 2000 )
+ PLACED ( 22310 23000 ) N ;
- in_n[6] + NET in_n[6] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER met2 ( -140 -2000 ) ( 140 2000 )
+ PLACED ( 24610 23000 ) N ;
- in_n[7] + NET in_n[7] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER met2 ( -140 -2000 ) ( 140 2000 )
+ PLACED ( 26910 23000 ) N ;
- in_n[8] + NET in_n[8] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER met2 ( -140 -2000 ) ( 140 2000 )
+ PLACED ( 29210 23000 ) N ;
- in_n[9] + NET in_n[9] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER met2 ( -140 -2000 ) ( 140 2000 )
+ PLACED ( 31510 23000 ) N ;
- in_s[0] + NET in_s[0] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER met2 ( -140 -2000 ) ( 140 2000 )
+ PLACED ( 3910 2000 ) N ;
- in_s[1] + NET in_s[1] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER met2 ( -140 -2000 ) ( 140 2000 )
+ PLACED ( 6210 2000 ) N ;
- in_s[2] + NET in_s[2] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER met2 ( -140 -2000 ) ( 140 2000 )
+ PLACED ( 8510 2000 ) N ;
- out_n[0] + NET out_n[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER met2 ( -140 -2000 ) ( 140 2000 )
+ PLACED ( 3910 23000 ) N ;
- out_n[1] + NET out_n[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER met2 ( -140 -2000 ) ( 140 2000 )
+ PLACED ( 6210 23000 ) N ;
- out_n[2] + NET out_n[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER met2 ( -140 -2000 ) ( 140 2000 )
+ PLACED ( 8510 23000 ) N ;
- out_s[0] + NET out_s[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER met2 ( -140 -2000 ) ( 140 2000 )
+ PLACED ( 10810 2000 ) N ;
- out_s[10] + NET out_s[10] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER met2 ( -140 -2000 ) ( 140 2000 )
+ PLACED ( 33810 2000 ) N ;
- out_s[11] + NET out_s[11] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER met2 ( -140 -2000 ) ( 140 2000 )
+ PLACED ( 36110 2000 ) N ;
- out_s[1] + NET out_s[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER met2 ( -140 -2000 ) ( 140 2000 )
+ PLACED ( 13110 2000 ) N ;
- out_s[2] + NET out_s[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER met2 ( -140 -2000 ) ( 140 2000 )
+ PLACED ( 15410 2000 ) N ;
- out_s[3] + NET out_s[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER met2 ( -140 -2000 ) ( 140 2000 )
+ PLACED ( 17710 2000 ) N ;
- out_s[4] + NET out_s[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER met2 ( -140 -2000 ) ( 140 2000 )
+ PLACED ( 20010 2000 ) N ;
- out_s[5] + NET out_s[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER met2 ( -140 -2000 ) ( 140 2000 )
+ PLACED ( 22310 2000 ) N ;
- out_s[6] + NET out_s[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER met2 ( -140 -2000 ) ( 140 2000 )
+ PLACED ( 24610 2000 ) N ;
- out_s[7] + NET out_s[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER met2 ( -140 -2000 ) ( 140 2000 )
+ PLACED ( 26910 2000 ) N ;
- out_s[8] + NET out_s[8] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER met2 ( -140 -2000 ) ( 140 2000 )
+ PLACED ( 29210 2000 ) N ;
- out_s[9] + NET out_s[9] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER met2 ( -140 -2000 ) ( 140 2000 )
+ PLACED ( 31510 2000 ) N ;
END PINS
SPECIALNETS 2 ;
- VGND ( PIN VGND ) ( * VNB ) ( * VGND ) + USE GROUND
+ ROUTED met1 480 + SHAPE FOLLOWPIN ( 1840 16320 ) ( 38495 16320 )
NEW met1 480 + SHAPE FOLLOWPIN ( 1840 10880 ) ( 38495 10880 )
NEW met1 480 + SHAPE FOLLOWPIN ( 1840 5440 ) ( 38495 5440 )
NEW met4 1600 + SHAPE STRIPE ( 37695 5200 ) ( 37695 19280 )
NEW met4 1600 + SHAPE STRIPE ( 28730 5200 ) ( 28730 19280 )
NEW met4 1600 + SHAPE STRIPE ( 19765 5200 ) ( 19765 19280 )
NEW met4 1600 + SHAPE STRIPE ( 10800 5200 ) ( 10800 19280 )
NEW met3 330 + SHAPE STRIPE ( 36905 16320 ) ( 38485 16320 )
NEW met3 0 + SHAPE STRIPE ( 37695 16320 ) via4_5_1600_480_1_4_400_400
NEW met2 370 + SHAPE STRIPE ( 36925 16320 ) ( 38465 16320 )
NEW met2 0 + SHAPE STRIPE ( 37695 16320 ) via3_4_1600_480_1_4_400_400
NEW met1 0 + SHAPE STRIPE ( 37695 16320 ) via2_3_1600_480_1_5_320_320
NEW met3 330 + SHAPE STRIPE ( 36905 10880 ) ( 38485 10880 )
NEW met3 0 + SHAPE STRIPE ( 37695 10880 ) via4_5_1600_480_1_4_400_400
NEW met2 370 + SHAPE STRIPE ( 36925 10880 ) ( 38465 10880 )
NEW met2 0 + SHAPE STRIPE ( 37695 10880 ) via3_4_1600_480_1_4_400_400
NEW met1 0 + SHAPE STRIPE ( 37695 10880 ) via2_3_1600_480_1_5_320_320
NEW met3 330 + SHAPE STRIPE ( 36905 5440 ) ( 38485 5440 )
NEW met3 0 + SHAPE STRIPE ( 37695 5440 ) via4_5_1600_480_1_4_400_400
NEW met2 370 + SHAPE STRIPE ( 36925 5440 ) ( 38465 5440 )
NEW met2 0 + SHAPE STRIPE ( 37695 5440 ) via3_4_1600_480_1_4_400_400
NEW met1 0 + SHAPE STRIPE ( 37695 5440 ) via2_3_1600_480_1_5_320_320
NEW met3 330 + SHAPE STRIPE ( 27940 16320 ) ( 29520 16320 )
NEW met3 0 + SHAPE STRIPE ( 28730 16320 ) via4_5_1600_480_1_4_400_400
NEW met2 370 + SHAPE STRIPE ( 27960 16320 ) ( 29500 16320 )
NEW met2 0 + SHAPE STRIPE ( 28730 16320 ) via3_4_1600_480_1_4_400_400
NEW met1 0 + SHAPE STRIPE ( 28730 16320 ) via2_3_1600_480_1_5_320_320
NEW met3 330 + SHAPE STRIPE ( 27940 10880 ) ( 29520 10880 )
NEW met3 0 + SHAPE STRIPE ( 28730 10880 ) via4_5_1600_480_1_4_400_400
NEW met2 370 + SHAPE STRIPE ( 27960 10880 ) ( 29500 10880 )
NEW met2 0 + SHAPE STRIPE ( 28730 10880 ) via3_4_1600_480_1_4_400_400
NEW met1 0 + SHAPE STRIPE ( 28730 10880 ) via2_3_1600_480_1_5_320_320
NEW met3 330 + SHAPE STRIPE ( 27940 5440 ) ( 29520 5440 )
NEW met3 0 + SHAPE STRIPE ( 28730 5440 ) via4_5_1600_480_1_4_400_400
NEW met2 370 + SHAPE STRIPE ( 27960 5440 ) ( 29500 5440 )
NEW met2 0 + SHAPE STRIPE ( 28730 5440 ) via3_4_1600_480_1_4_400_400
NEW met1 0 + SHAPE STRIPE ( 28730 5440 ) via2_3_1600_480_1_5_320_320
NEW met3 330 + SHAPE STRIPE ( 18975 16320 ) ( 20555 16320 )
NEW met3 0 + SHAPE STRIPE ( 19765 16320 ) via4_5_1600_480_1_4_400_400
NEW met2 370 + SHAPE STRIPE ( 18995 16320 ) ( 20535 16320 )
NEW met2 0 + SHAPE STRIPE ( 19765 16320 ) via3_4_1600_480_1_4_400_400
NEW met1 0 + SHAPE STRIPE ( 19765 16320 ) via2_3_1600_480_1_5_320_320
NEW met3 330 + SHAPE STRIPE ( 18975 10880 ) ( 20555 10880 )
NEW met3 0 + SHAPE STRIPE ( 19765 10880 ) via4_5_1600_480_1_4_400_400
NEW met2 370 + SHAPE STRIPE ( 18995 10880 ) ( 20535 10880 )
NEW met2 0 + SHAPE STRIPE ( 19765 10880 ) via3_4_1600_480_1_4_400_400
NEW met1 0 + SHAPE STRIPE ( 19765 10880 ) via2_3_1600_480_1_5_320_320
NEW met3 330 + SHAPE STRIPE ( 18975 5440 ) ( 20555 5440 )
NEW met3 0 + SHAPE STRIPE ( 19765 5440 ) via4_5_1600_480_1_4_400_400
NEW met2 370 + SHAPE STRIPE ( 18995 5440 ) ( 20535 5440 )
NEW met2 0 + SHAPE STRIPE ( 19765 5440 ) via3_4_1600_480_1_4_400_400
NEW met1 0 + SHAPE STRIPE ( 19765 5440 ) via2_3_1600_480_1_5_320_320
NEW met3 330 + SHAPE STRIPE ( 10010 16320 ) ( 11590 16320 )
NEW met3 0 + SHAPE STRIPE ( 10800 16320 ) via4_5_1600_480_1_4_400_400
NEW met2 370 + SHAPE STRIPE ( 10030 16320 ) ( 11570 16320 )
NEW met2 0 + SHAPE STRIPE ( 10800 16320 ) via3_4_1600_480_1_4_400_400
NEW met1 0 + SHAPE STRIPE ( 10800 16320 ) via2_3_1600_480_1_5_320_320
NEW met3 330 + SHAPE STRIPE ( 10010 10880 ) ( 11590 10880 )
NEW met3 0 + SHAPE STRIPE ( 10800 10880 ) via4_5_1600_480_1_4_400_400
NEW met2 370 + SHAPE STRIPE ( 10030 10880 ) ( 11570 10880 )
NEW met2 0 + SHAPE STRIPE ( 10800 10880 ) via3_4_1600_480_1_4_400_400
NEW met1 0 + SHAPE STRIPE ( 10800 10880 ) via2_3_1600_480_1_5_320_320
NEW met3 330 + SHAPE STRIPE ( 10010 5440 ) ( 11590 5440 )
NEW met3 0 + SHAPE STRIPE ( 10800 5440 ) via4_5_1600_480_1_4_400_400
NEW met2 370 + SHAPE STRIPE ( 10030 5440 ) ( 11570 5440 )
NEW met2 0 + SHAPE STRIPE ( 10800 5440 ) via3_4_1600_480_1_4_400_400
NEW met1 0 + SHAPE STRIPE ( 10800 5440 ) via2_3_1600_480_1_5_320_320 ;
- VPWR ( PIN VPWR ) ( * VPB ) ( * VPWR ) + USE POWER
+ ROUTED met1 480 + SHAPE FOLLOWPIN ( 1840 19040 ) ( 37720 19040 )
NEW met1 480 + SHAPE FOLLOWPIN ( 1840 13600 ) ( 37720 13600 )
NEW met1 480 + SHAPE FOLLOWPIN ( 1840 8160 ) ( 37720 8160 )
NEW met4 1600 + SHAPE STRIPE ( 33215 5200 ) ( 33215 19280 )
NEW met4 1600 + SHAPE STRIPE ( 24250 5200 ) ( 24250 19280 )
NEW met4 1600 + SHAPE STRIPE ( 15285 5200 ) ( 15285 19280 )
NEW met4 1600 + SHAPE STRIPE ( 6320 5200 ) ( 6320 19280 )
NEW met3 330 + SHAPE STRIPE ( 32425 19040 ) ( 34005 19040 )
NEW met3 0 + SHAPE STRIPE ( 33215 19040 ) via4_5_1600_480_1_4_400_400
NEW met2 370 + SHAPE STRIPE ( 32445 19040 ) ( 33985 19040 )
NEW met2 0 + SHAPE STRIPE ( 33215 19040 ) via3_4_1600_480_1_4_400_400
NEW met1 0 + SHAPE STRIPE ( 33215 19040 ) via2_3_1600_480_1_5_320_320
NEW met3 330 + SHAPE STRIPE ( 32425 13600 ) ( 34005 13600 )
NEW met3 0 + SHAPE STRIPE ( 33215 13600 ) via4_5_1600_480_1_4_400_400
NEW met2 370 + SHAPE STRIPE ( 32445 13600 ) ( 33985 13600 )
NEW met2 0 + SHAPE STRIPE ( 33215 13600 ) via3_4_1600_480_1_4_400_400
NEW met1 0 + SHAPE STRIPE ( 33215 13600 ) via2_3_1600_480_1_5_320_320
NEW met3 330 + SHAPE STRIPE ( 32425 8160 ) ( 34005 8160 )
NEW met3 0 + SHAPE STRIPE ( 33215 8160 ) via4_5_1600_480_1_4_400_400
NEW met2 370 + SHAPE STRIPE ( 32445 8160 ) ( 33985 8160 )
NEW met2 0 + SHAPE STRIPE ( 33215 8160 ) via3_4_1600_480_1_4_400_400
NEW met1 0 + SHAPE STRIPE ( 33215 8160 ) via2_3_1600_480_1_5_320_320
NEW met3 330 + SHAPE STRIPE ( 23460 19040 ) ( 25040 19040 )
NEW met3 0 + SHAPE STRIPE ( 24250 19040 ) via4_5_1600_480_1_4_400_400
NEW met2 370 + SHAPE STRIPE ( 23480 19040 ) ( 25020 19040 )
NEW met2 0 + SHAPE STRIPE ( 24250 19040 ) via3_4_1600_480_1_4_400_400
NEW met1 0 + SHAPE STRIPE ( 24250 19040 ) via2_3_1600_480_1_5_320_320
NEW met3 330 + SHAPE STRIPE ( 23460 13600 ) ( 25040 13600 )
NEW met3 0 + SHAPE STRIPE ( 24250 13600 ) via4_5_1600_480_1_4_400_400
NEW met2 370 + SHAPE STRIPE ( 23480 13600 ) ( 25020 13600 )
NEW met2 0 + SHAPE STRIPE ( 24250 13600 ) via3_4_1600_480_1_4_400_400
NEW met1 0 + SHAPE STRIPE ( 24250 13600 ) via2_3_1600_480_1_5_320_320
NEW met3 330 + SHAPE STRIPE ( 23460 8160 ) ( 25040 8160 )
NEW met3 0 + SHAPE STRIPE ( 24250 8160 ) via4_5_1600_480_1_4_400_400
NEW met2 370 + SHAPE STRIPE ( 23480 8160 ) ( 25020 8160 )
NEW met2 0 + SHAPE STRIPE ( 24250 8160 ) via3_4_1600_480_1_4_400_400
NEW met1 0 + SHAPE STRIPE ( 24250 8160 ) via2_3_1600_480_1_5_320_320
NEW met3 330 + SHAPE STRIPE ( 14495 19040 ) ( 16075 19040 )
NEW met3 0 + SHAPE STRIPE ( 15285 19040 ) via4_5_1600_480_1_4_400_400
NEW met2 370 + SHAPE STRIPE ( 14515 19040 ) ( 16055 19040 )
NEW met2 0 + SHAPE STRIPE ( 15285 19040 ) via3_4_1600_480_1_4_400_400
NEW met1 0 + SHAPE STRIPE ( 15285 19040 ) via2_3_1600_480_1_5_320_320
NEW met3 330 + SHAPE STRIPE ( 14495 13600 ) ( 16075 13600 )
NEW met3 0 + SHAPE STRIPE ( 15285 13600 ) via4_5_1600_480_1_4_400_400
NEW met2 370 + SHAPE STRIPE ( 14515 13600 ) ( 16055 13600 )
NEW met2 0 + SHAPE STRIPE ( 15285 13600 ) via3_4_1600_480_1_4_400_400
NEW met1 0 + SHAPE STRIPE ( 15285 13600 ) via2_3_1600_480_1_5_320_320
NEW met3 330 + SHAPE STRIPE ( 14495 8160 ) ( 16075 8160 )
NEW met3 0 + SHAPE STRIPE ( 15285 8160 ) via4_5_1600_480_1_4_400_400
NEW met2 370 + SHAPE STRIPE ( 14515 8160 ) ( 16055 8160 )
NEW met2 0 + SHAPE STRIPE ( 15285 8160 ) via3_4_1600_480_1_4_400_400
NEW met1 0 + SHAPE STRIPE ( 15285 8160 ) via2_3_1600_480_1_5_320_320
NEW met3 330 + SHAPE STRIPE ( 5530 19040 ) ( 7110 19040 )
NEW met3 0 + SHAPE STRIPE ( 6320 19040 ) via4_5_1600_480_1_4_400_400
NEW met2 370 + SHAPE STRIPE ( 5550 19040 ) ( 7090 19040 )
NEW met2 0 + SHAPE STRIPE ( 6320 19040 ) via3_4_1600_480_1_4_400_400
NEW met1 0 + SHAPE STRIPE ( 6320 19040 ) via2_3_1600_480_1_5_320_320
NEW met3 330 + SHAPE STRIPE ( 5530 13600 ) ( 7110 13600 )
NEW met3 0 + SHAPE STRIPE ( 6320 13600 ) via4_5_1600_480_1_4_400_400
NEW met2 370 + SHAPE STRIPE ( 5550 13600 ) ( 7090 13600 )
NEW met2 0 + SHAPE STRIPE ( 6320 13600 ) via3_4_1600_480_1_4_400_400
NEW met1 0 + SHAPE STRIPE ( 6320 13600 ) via2_3_1600_480_1_5_320_320
NEW met3 330 + SHAPE STRIPE ( 5530 8160 ) ( 7110 8160 )
NEW met3 0 + SHAPE STRIPE ( 6320 8160 ) via4_5_1600_480_1_4_400_400
NEW met2 370 + SHAPE STRIPE ( 5550 8160 ) ( 7090 8160 )
NEW met2 0 + SHAPE STRIPE ( 6320 8160 ) via3_4_1600_480_1_4_400_400
NEW met1 0 + SHAPE STRIPE ( 6320 8160 ) via2_3_1600_480_1_5_320_320 ;
END SPECIALNETS
NETS 30 ;
- in_n[0] ( PIN in_n[0] ) ( BUF\[3\] A ) + USE SIGNAL
+ ROUTED met2 ( 9430 15470 ) ( * 21420 )
NEW met2 ( 9430 21420 ) ( 10810 * 0 )
NEW li1 ( 9430 15470 ) L1M1_PR_MR
NEW met1 ( 9430 15470 ) M1M2_PR
NEW met1 ( 9430 15470 ) RECT ( -355 -70 0 70 ) ;
- in_n[10] ( PIN in_n[10] ) ( BUF\[13\] A ) + USE SIGNAL
+ ROUTED met1 ( 33810 17510 ) ( 34270 * )
NEW met2 ( 34270 17510 ) ( * 20060 )
NEW met2 ( 33810 20060 ) ( 34270 * )
NEW met2 ( 33810 20060 ) ( * 21420 0 )
NEW li1 ( 33810 17510 ) L1M1_PR_MR
NEW met1 ( 34270 17510 ) M1M2_PR ;
- in_n[11] ( PIN in_n[11] ) ( BUF\[14\] A ) + USE SIGNAL
+ ROUTED met1 ( 26450 6630 ) ( 31510 * )
NEW met1 ( 31510 6630 ) ( * 6970 )
NEW met1 ( 31510 6970 ) ( 34270 * )
NEW met1 ( 34270 6630 ) ( * 6970 )
NEW met1 ( 34270 6630 ) ( 36110 * )
NEW met2 ( 36110 6630 ) ( * 21420 0 )
NEW li1 ( 26450 6630 ) L1M1_PR_MR
NEW met1 ( 36110 6630 ) M1M2_PR ;
- in_n[1] ( PIN in_n[1] ) ( BUF\[4\] A ) + USE SIGNAL
+ ROUTED met2 ( 13570 12070 ) ( * 21420 )
NEW met2 ( 13110 21420 0 ) ( 13570 * )
NEW li1 ( 13570 12070 ) L1M1_PR_MR
NEW met1 ( 13570 12070 ) M1M2_PR
NEW met1 ( 13570 12070 ) RECT ( -355 -70 0 70 ) ;
- in_n[2] ( PIN in_n[2] ) ( BUF\[5\] A ) + USE SIGNAL
+ ROUTED met1 ( 14030 10030 ) ( 16330 * )
NEW met2 ( 14030 10030 ) ( * 21420 )
NEW met2 ( 14030 21420 ) ( 15410 * 0 )
NEW li1 ( 16330 10030 ) L1M1_PR_MR
NEW met1 ( 14030 10030 ) M1M2_PR ;
- in_n[3] ( PIN in_n[3] ) ( BUF\[6\] A ) + USE SIGNAL
+ ROUTED met2 ( 16330 15470 ) ( * 21420 )
NEW met2 ( 16330 21420 ) ( 17710 * 0 )
NEW li1 ( 16330 15470 ) L1M1_PR_MR
NEW met1 ( 16330 15470 ) M1M2_PR
NEW met1 ( 16330 15470 ) RECT ( -355 -70 0 70 ) ;
- in_n[4] ( PIN in_n[4] ) ( BUF\[7\] A ) + USE SIGNAL
+ ROUTED met2 ( 18630 10030 ) ( * 21420 )
NEW met2 ( 18630 21420 ) ( 20010 * 0 )
NEW li1 ( 18630 10030 ) L1M1_PR_MR
NEW met1 ( 18630 10030 ) M1M2_PR
NEW met1 ( 18630 10030 ) RECT ( -355 -70 0 70 ) ;
- in_n[5] ( PIN in_n[5] ) ( BUF\[8\] A ) + USE SIGNAL
+ ROUTED met2 ( 20930 12070 ) ( * 21420 )
NEW met2 ( 20930 21420 ) ( 22310 * 0 )
NEW li1 ( 20930 12070 ) L1M1_PR_MR
NEW met1 ( 20930 12070 ) M1M2_PR
NEW met1 ( 20930 12070 ) RECT ( -355 -70 0 70 ) ;
- in_n[6] ( PIN in_n[6] ) ( BUF\[9\] A ) + USE SIGNAL
+ ROUTED met1 ( 26450 12070 ) ( 27830 * )
NEW met2 ( 26450 12070 ) ( * 21420 )
NEW met2 ( 24610 21420 0 ) ( 26450 * )
NEW li1 ( 27830 12070 ) L1M1_PR_MR
NEW met1 ( 26450 12070 ) M1M2_PR ;
- in_n[7] ( PIN in_n[7] ) ( BUF\[10\] A ) + USE SIGNAL
+ ROUTED met1 ( 26910 10030 ) ( 29210 * )
NEW met2 ( 26910 10030 ) ( * 21420 0 )
NEW li1 ( 29210 10030 ) L1M1_PR_MR
NEW met1 ( 26910 10030 ) M1M2_PR ;
- in_n[8] ( PIN in_n[8] ) ( BUF\[11\] A ) + USE SIGNAL
+ ROUTED met1 ( 29210 15470 ) ( 30130 * )
NEW met2 ( 30130 15470 ) ( * 18020 )
NEW met2 ( 29210 18020 ) ( 30130 * )
NEW met2 ( 29210 18020 ) ( * 21420 0 )
NEW li1 ( 29210 15470 ) L1M1_PR_MR
NEW met1 ( 30130 15470 ) M1M2_PR ;
- in_n[9] ( PIN in_n[9] ) ( BUF\[12\] A ) + USE SIGNAL
+ ROUTED met1 ( 31970 6630 ) ( 33810 * )
NEW met2 ( 31970 6630 ) ( * 21420 )
NEW met2 ( 31510 21420 0 ) ( 31970 * )
NEW li1 ( 33810 6630 ) L1M1_PR_MR
NEW met1 ( 31970 6630 ) M1M2_PR ;
- in_s[0] ( PIN in_s[0] ) ( BUF\[0\] A ) + USE SIGNAL
+ ROUTED met2 ( 3910 3740 0 ) ( * 6290 )
NEW met1 ( 3910 6290 ) ( 5750 * )
NEW met1 ( 3910 6290 ) M1M2_PR
NEW li1 ( 5750 6290 ) L1M1_PR_MR ;
- in_s[1] ( PIN in_s[1] ) ( BUF\[1\] A ) + USE SIGNAL
+ ROUTED met2 ( 6210 3740 0 ) ( * 7140 )
NEW met2 ( 5290 7140 ) ( 6210 * )
NEW met2 ( 5290 7140 ) ( * 17170 )
NEW met1 ( 5290 17170 ) ( 5750 * )
NEW met1 ( 5290 17170 ) M1M2_PR
NEW li1 ( 5750 17170 ) L1M1_PR_MR ;
- in_s[2] ( PIN in_s[2] ) ( BUF\[2\] A ) + USE SIGNAL
+ ROUTED met2 ( 8510 3740 0 ) ( * 9690 )
NEW met1 ( 8510 9690 ) ( 9430 * )
NEW met1 ( 8510 9690 ) M1M2_PR
NEW li1 ( 9430 9690 ) L1M1_PR_MR ;
- out_n[0] ( PIN out_n[0] ) ( BUF\[0\] X ) + USE SIGNAL
+ ROUTED met1 ( 4830 6630 ) ( 9430 * )
NEW met2 ( 4830 6630 ) ( * 21420 )
NEW met2 ( 3910 21420 0 ) ( 4830 * )
NEW li1 ( 9430 6630 ) L1M1_PR_MR
NEW met1 ( 4830 6630 ) M1M2_PR ;
- out_n[1] ( PIN out_n[1] ) ( BUF\[1\] X ) + USE SIGNAL
+ ROUTED met1 ( 7590 17850 ) ( 9430 * )
NEW met2 ( 7590 17850 ) ( * 21420 )
NEW met2 ( 6210 21420 0 ) ( 7590 * )
NEW li1 ( 9430 17850 ) L1M1_PR_MR
NEW met1 ( 7590 17850 ) M1M2_PR ;
- out_n[2] ( PIN out_n[2] ) ( BUF\[2\] X ) + USE SIGNAL
+ ROUTED met1 ( 5750 10030 ) ( 8050 * )
NEW met2 ( 8050 10030 ) ( * 21420 )
NEW met2 ( 8050 21420 ) ( 8510 * 0 )
NEW li1 ( 5750 10030 ) L1M1_PR_MR
NEW met1 ( 8050 10030 ) M1M2_PR ;
- out_s[0] ( PIN out_s[0] ) ( BUF\[3\] X ) + USE SIGNAL
+ ROUTED met2 ( 10810 3740 0 ) ( * 4420 )
NEW met2 ( 10810 4420 ) ( 11270 * )
NEW met2 ( 11270 3740 ) ( * 4420 )
NEW met2 ( 11270 3740 ) ( 12190 * )
NEW met2 ( 12190 3740 ) ( * 14790 )
NEW met1 ( 12190 14790 ) ( 13110 * )
NEW met1 ( 12190 14790 ) M1M2_PR
NEW li1 ( 13110 14790 ) L1M1_PR_MR ;
- out_s[10] ( PIN out_s[10] ) ( BUF\[13\] X ) + USE SIGNAL
+ ROUTED met2 ( 33810 3740 0 ) ( * 7140 )
NEW met2 ( 33810 7140 ) ( 34270 * )
NEW met2 ( 34270 7140 ) ( * 16830 )
NEW met1 ( 34270 16830 ) ( * 17170 )
NEW met1 ( 30130 17170 ) ( 34270 * )
NEW met1 ( 34270 16830 ) M1M2_PR
NEW li1 ( 30130 17170 ) L1M1_PR_MR ;
- out_s[11] ( PIN out_s[11] ) ( BUF\[14\] X ) + USE SIGNAL
+ ROUTED met2 ( 36110 3740 0 ) ( * 5950 )
NEW met1 ( 22770 5950 ) ( 36110 * )
NEW met1 ( 22770 5950 ) ( * 6290 )
NEW met1 ( 36110 5950 ) M1M2_PR
NEW li1 ( 22770 6290 ) L1M1_PR_MR ;
- out_s[1] ( PIN out_s[1] ) ( BUF\[4\] X ) + USE SIGNAL
+ ROUTED met2 ( 13110 3740 0 ) ( * 11730 )
NEW met1 ( 9890 11730 ) ( 13110 * )
NEW met1 ( 13110 11730 ) M1M2_PR
NEW li1 ( 9890 11730 ) L1M1_PR_MR ;
- out_s[2] ( PIN out_s[2] ) ( BUF\[5\] X ) + USE SIGNAL
+ ROUTED met2 ( 15410 3740 0 ) ( * 4420 )
NEW met2 ( 14950 4420 ) ( 15410 * )
NEW met2 ( 14950 3740 ) ( * 4420 )
NEW met2 ( 14030 3740 ) ( 14950 * )
NEW met2 ( 14030 3740 ) ( * 9350 )
NEW met1 ( 12650 9350 ) ( 14030 * )
NEW met1 ( 14030 9350 ) M1M2_PR
NEW li1 ( 12650 9350 ) L1M1_PR_MR ;
- out_s[3] ( PIN out_s[3] ) ( BUF\[6\] X ) + USE SIGNAL
+ ROUTED met2 ( 17710 3740 0 ) ( * 14790 )
NEW met1 ( 17710 14790 ) ( 20010 * )
NEW met1 ( 17710 14790 ) M1M2_PR
NEW li1 ( 20010 14790 ) L1M1_PR_MR ;
- out_s[4] ( PIN out_s[4] ) ( BUF\[7\] X ) + USE SIGNAL
+ ROUTED met2 ( 20010 3740 0 ) ( * 4420 )
NEW met2 ( 20010 4420 ) ( 20930 * )
NEW met2 ( 20930 4420 ) ( * 9350 )
NEW met1 ( 20930 9350 ) ( 22310 * )
NEW met1 ( 20930 9350 ) M1M2_PR
NEW li1 ( 22310 9350 ) L1M1_PR_MR ;
- out_s[5] ( PIN out_s[5] ) ( BUF\[8\] X ) + USE SIGNAL
+ ROUTED met2 ( 22310 3740 0 ) ( * 11730 )
NEW met1 ( 22310 11730 ) ( 24610 * )
NEW met1 ( 22310 11730 ) M1M2_PR
NEW li1 ( 24610 11730 ) L1M1_PR_MR ;
- out_s[6] ( PIN out_s[6] ) ( BUF\[9\] X ) + USE SIGNAL
+ ROUTED met2 ( 24610 3740 0 ) ( * 5780 )
NEW met2 ( 24610 5780 ) ( 25530 * )
NEW met2 ( 25530 5780 ) ( * 11730 )
NEW met1 ( 25530 11730 ) ( 31510 * )
NEW met1 ( 25530 11730 ) M1M2_PR
NEW li1 ( 31510 11730 ) L1M1_PR_MR ;
- out_s[7] ( PIN out_s[7] ) ( BUF\[10\] X ) + USE SIGNAL
+ ROUTED met2 ( 26910 3740 0 ) ( * 9350 )
NEW met1 ( 26910 9350 ) ( 32890 * )
NEW met1 ( 26910 9350 ) M1M2_PR
NEW li1 ( 32890 9350 ) L1M1_PR_MR ;
- out_s[8] ( PIN out_s[8] ) ( BUF\[11\] X ) + USE SIGNAL
+ ROUTED met2 ( 29210 3740 0 ) ( * 4420 )
NEW met2 ( 29210 4420 ) ( 30130 * )
NEW met2 ( 30130 4420 ) ( * 14790 )
NEW met1 ( 30130 14790 ) ( 32890 * )
NEW met1 ( 30130 14790 ) M1M2_PR
NEW li1 ( 32890 14790 ) L1M1_PR_MR ;
- out_s[9] ( PIN out_s[9] ) ( BUF\[12\] X ) + USE SIGNAL
+ ROUTED met2 ( 31510 3740 0 ) ( * 6290 )
NEW met1 ( 30130 6290 ) ( 31510 * )
NEW met1 ( 31510 6290 ) M1M2_PR
NEW li1 ( 30130 6290 ) L1M1_PR_MR ;
END NETS
END DESIGN

BIN
gds/buff_flash_clkrst.gds.gz Normal file
View File

Binary file not shown.

336
lef/buff_flash_clkrst.lef Normal file
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@ -0,0 +1,336 @@
VERSION 5.7 ;
NOWIREEXTENSIONATPIN ON ;
DIVIDERCHAR "/" ;
BUSBITCHARS "[]" ;
MACRO buff_flash_clkrst
CLASS BLOCK ;
FOREIGN buff_flash_clkrst ;
ORIGIN 0.000 0.000 ;
SIZE 40.000 BY 25.000 ;
PIN VGND
DIRECTION INOUT ;
USE GROUND ;
PORT
LAYER met4 ;
RECT 10.000 5.200 11.600 19.280 ;
END
PORT
LAYER met4 ;
RECT 18.965 5.200 20.565 19.280 ;
END
PORT
LAYER met4 ;
RECT 27.930 5.200 29.530 19.280 ;
END
PORT
LAYER met4 ;
RECT 36.895 5.200 38.495 19.280 ;
END
END VGND
PIN VPWR
DIRECTION INOUT ;
USE POWER ;
PORT
LAYER met4 ;
RECT 5.520 5.200 7.120 19.280 ;
END
PORT
LAYER met4 ;
RECT 14.485 5.200 16.085 19.280 ;
END
PORT
LAYER met4 ;
RECT 23.450 5.200 25.050 19.280 ;
END
PORT
LAYER met4 ;
RECT 32.415 5.200 34.015 19.280 ;
END
END VPWR
PIN in_n[0]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER met2 ;
RECT 10.670 21.000 10.950 25.000 ;
END
END in_n[0]
PIN in_n[10]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER met2 ;
RECT 33.670 21.000 33.950 25.000 ;
END
END in_n[10]
PIN in_n[11]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER met2 ;
RECT 35.970 21.000 36.250 25.000 ;
END
END in_n[11]
PIN in_n[1]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER met2 ;
RECT 12.970 21.000 13.250 25.000 ;
END
END in_n[1]
PIN in_n[2]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER met2 ;
RECT 15.270 21.000 15.550 25.000 ;
END
END in_n[2]
PIN in_n[3]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER met2 ;
RECT 17.570 21.000 17.850 25.000 ;
END
END in_n[3]
PIN in_n[4]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER met2 ;
RECT 19.870 21.000 20.150 25.000 ;
END
END in_n[4]
PIN in_n[5]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER met2 ;
RECT 22.170 21.000 22.450 25.000 ;
END
END in_n[5]
PIN in_n[6]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER met2 ;
RECT 24.470 21.000 24.750 25.000 ;
END
END in_n[6]
PIN in_n[7]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER met2 ;
RECT 26.770 21.000 27.050 25.000 ;
END
END in_n[7]
PIN in_n[8]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER met2 ;
RECT 29.070 21.000 29.350 25.000 ;
END
END in_n[8]
PIN in_n[9]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER met2 ;
RECT 31.370 21.000 31.650 25.000 ;
END
END in_n[9]
PIN in_s[0]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER met2 ;
RECT 3.770 0.000 4.050 4.000 ;
END
END in_s[0]
PIN in_s[1]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER met2 ;
RECT 6.070 0.000 6.350 4.000 ;
END
END in_s[1]
PIN in_s[2]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER met2 ;
RECT 8.370 0.000 8.650 4.000 ;
END
END in_s[2]
PIN out_n[0]
DIRECTION OUTPUT TRISTATE ;
USE SIGNAL ;
PORT
LAYER met2 ;
RECT 3.770 21.000 4.050 25.000 ;
END
END out_n[0]
PIN out_n[1]
DIRECTION OUTPUT TRISTATE ;
USE SIGNAL ;
PORT
LAYER met2 ;
RECT 6.070 21.000 6.350 25.000 ;
END
END out_n[1]
PIN out_n[2]
DIRECTION OUTPUT TRISTATE ;
USE SIGNAL ;
PORT
LAYER met2 ;
RECT 8.370 21.000 8.650 25.000 ;
END
END out_n[2]
PIN out_s[0]
DIRECTION OUTPUT TRISTATE ;
USE SIGNAL ;
PORT
LAYER met2 ;
RECT 10.670 0.000 10.950 4.000 ;
END
END out_s[0]
PIN out_s[10]
DIRECTION OUTPUT TRISTATE ;
USE SIGNAL ;
PORT
LAYER met2 ;
RECT 33.670 0.000 33.950 4.000 ;
END
END out_s[10]
PIN out_s[11]
DIRECTION OUTPUT TRISTATE ;
USE SIGNAL ;
PORT
LAYER met2 ;
RECT 35.970 0.000 36.250 4.000 ;
END
END out_s[11]
PIN out_s[1]
DIRECTION OUTPUT TRISTATE ;
USE SIGNAL ;
PORT
LAYER met2 ;
RECT 12.970 0.000 13.250 4.000 ;
END
END out_s[1]
PIN out_s[2]
DIRECTION OUTPUT TRISTATE ;
USE SIGNAL ;
PORT
LAYER met2 ;
RECT 15.270 0.000 15.550 4.000 ;
END
END out_s[2]
PIN out_s[3]
DIRECTION OUTPUT TRISTATE ;
USE SIGNAL ;
PORT
LAYER met2 ;
RECT 17.570 0.000 17.850 4.000 ;
END
END out_s[3]
PIN out_s[4]
DIRECTION OUTPUT TRISTATE ;
USE SIGNAL ;
PORT
LAYER met2 ;
RECT 19.870 0.000 20.150 4.000 ;
END
END out_s[4]
PIN out_s[5]
DIRECTION OUTPUT TRISTATE ;
USE SIGNAL ;
PORT
LAYER met2 ;
RECT 22.170 0.000 22.450 4.000 ;
END
END out_s[5]
PIN out_s[6]
DIRECTION OUTPUT TRISTATE ;
USE SIGNAL ;
PORT
LAYER met2 ;
RECT 24.470 0.000 24.750 4.000 ;
END
END out_s[6]
PIN out_s[7]
DIRECTION OUTPUT TRISTATE ;
USE SIGNAL ;
PORT
LAYER met2 ;
RECT 26.770 0.000 27.050 4.000 ;
END
END out_s[7]
PIN out_s[8]
DIRECTION OUTPUT TRISTATE ;
USE SIGNAL ;
PORT
LAYER met2 ;
RECT 29.070 0.000 29.350 4.000 ;
END
END out_s[8]
PIN out_s[9]
DIRECTION OUTPUT TRISTATE ;
USE SIGNAL ;
PORT
LAYER met2 ;
RECT 31.370 0.000 31.650 4.000 ;
END
END out_s[9]
OBS
LAYER nwell ;
RECT 1.650 17.625 37.910 19.230 ;
RECT 1.650 12.185 37.910 15.015 ;
RECT 1.650 6.745 37.910 9.575 ;
LAYER li1 ;
RECT 1.840 5.355 37.720 19.125 ;
LAYER met1 ;
RECT 1.840 5.200 38.495 19.280 ;
LAYER met2 ;
RECT 4.330 20.720 5.790 21.490 ;
RECT 6.630 20.720 8.090 21.490 ;
RECT 8.930 20.720 10.390 21.490 ;
RECT 11.230 20.720 12.690 21.490 ;
RECT 13.530 20.720 14.990 21.490 ;
RECT 15.830 20.720 17.290 21.490 ;
RECT 18.130 20.720 19.590 21.490 ;
RECT 20.430 20.720 21.890 21.490 ;
RECT 22.730 20.720 24.190 21.490 ;
RECT 25.030 20.720 26.490 21.490 ;
RECT 27.330 20.720 28.790 21.490 ;
RECT 29.630 20.720 31.090 21.490 ;
RECT 31.930 20.720 33.390 21.490 ;
RECT 34.230 20.720 35.690 21.490 ;
RECT 36.530 20.720 38.465 21.490 ;
RECT 3.780 4.280 38.465 20.720 ;
RECT 4.330 3.670 5.790 4.280 ;
RECT 6.630 3.670 8.090 4.280 ;
RECT 8.930 3.670 10.390 4.280 ;
RECT 11.230 3.670 12.690 4.280 ;
RECT 13.530 3.670 14.990 4.280 ;
RECT 15.830 3.670 17.290 4.280 ;
RECT 18.130 3.670 19.590 4.280 ;
RECT 20.430 3.670 21.890 4.280 ;
RECT 22.730 3.670 24.190 4.280 ;
RECT 25.030 3.670 26.490 4.280 ;
RECT 27.330 3.670 28.790 4.280 ;
RECT 29.630 3.670 31.090 4.280 ;
RECT 31.930 3.670 33.390 4.280 ;
RECT 34.230 3.670 35.690 4.280 ;
RECT 36.530 3.670 38.465 4.280 ;
LAYER met3 ;
RECT 5.530 5.275 38.485 19.205 ;
END
END buff_flash_clkrst
END LIBRARY

583
lib/buff_flash_clkrst.lib Normal file
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@ -0,0 +1,583 @@
library (buff_flash_clkrst) {
comment : "";
delay_model : table_lookup;
simulation : false;
capacitive_load_unit (1,pF);
leakage_power_unit : 1pW;
current_unit : "1A";
pulling_resistance_unit : "1kohm";
time_unit : "1ns";
voltage_unit : "1v";
library_features(report_delay_calculation);
input_threshold_pct_rise : 50;
input_threshold_pct_fall : 50;
output_threshold_pct_rise : 50;
output_threshold_pct_fall : 50;
slew_lower_threshold_pct_rise : 20;
slew_lower_threshold_pct_fall : 20;
slew_upper_threshold_pct_rise : 80;
slew_upper_threshold_pct_fall : 80;
slew_derate_from_library : 1.0;
nom_process : 1.0;
nom_temperature : 25.0;
nom_voltage : 1.80;
lu_table_template(template_1) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00175, 0.00610, 0.02132, 0.07449, 0.26022, 0.90913");
}
lu_table_template(template_10) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00175, 0.00610, 0.02132, 0.07449, 0.26022, 0.90913");
}
lu_table_template(template_11) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00175, 0.00610, 0.02132, 0.07449, 0.26022, 0.90913");
}
lu_table_template(template_12) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00175, 0.00610, 0.02132, 0.07449, 0.26022, 0.90913");
}
lu_table_template(template_13) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00175, 0.00610, 0.02132, 0.07449, 0.26022, 0.90913");
}
lu_table_template(template_14) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00175, 0.00610, 0.02132, 0.07449, 0.26022, 0.90913");
}
lu_table_template(template_15) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00175, 0.00610, 0.02132, 0.07449, 0.26022, 0.90913");
}
lu_table_template(template_16) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00175, 0.00610, 0.02132, 0.07449, 0.26022, 0.90913");
}
lu_table_template(template_17) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00175, 0.00610, 0.02132, 0.07449, 0.26022, 0.90913");
}
lu_table_template(template_18) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00175, 0.00610, 0.02132, 0.07449, 0.26022, 0.90913");
}
lu_table_template(template_19) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00175, 0.00610, 0.02132, 0.07449, 0.26022, 0.90913");
}
lu_table_template(template_2) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00175, 0.00610, 0.02132, 0.07449, 0.26022, 0.90913");
}
lu_table_template(template_20) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00175, 0.00610, 0.02132, 0.07449, 0.26022, 0.90913");
}
lu_table_template(template_21) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00175, 0.00610, 0.02132, 0.07449, 0.26022, 0.90913");
}
lu_table_template(template_22) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00175, 0.00610, 0.02132, 0.07449, 0.26022, 0.90913");
}
lu_table_template(template_23) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00175, 0.00610, 0.02132, 0.07449, 0.26022, 0.90913");
}
lu_table_template(template_24) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00175, 0.00610, 0.02132, 0.07449, 0.26022, 0.90913");
}
lu_table_template(template_25) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00175, 0.00610, 0.02132, 0.07449, 0.26022, 0.90913");
}
lu_table_template(template_26) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00175, 0.00610, 0.02132, 0.07449, 0.26022, 0.90913");
}
lu_table_template(template_27) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00175, 0.00610, 0.02132, 0.07449, 0.26022, 0.90913");
}
lu_table_template(template_28) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00175, 0.00610, 0.02132, 0.07449, 0.26022, 0.90913");
}
lu_table_template(template_29) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00175, 0.00610, 0.02132, 0.07449, 0.26022, 0.90913");
}
lu_table_template(template_3) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00175, 0.00610, 0.02132, 0.07449, 0.26022, 0.90913");
}
lu_table_template(template_30) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00175, 0.00610, 0.02132, 0.07449, 0.26022, 0.90913");
}
lu_table_template(template_4) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00175, 0.00610, 0.02132, 0.07449, 0.26022, 0.90913");
}
lu_table_template(template_5) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00175, 0.00610, 0.02132, 0.07449, 0.26022, 0.90913");
}
lu_table_template(template_6) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00175, 0.00610, 0.02132, 0.07449, 0.26022, 0.90913");
}
lu_table_template(template_7) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00175, 0.00610, 0.02132, 0.07449, 0.26022, 0.90913");
}
lu_table_template(template_8) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00175, 0.00610, 0.02132, 0.07449, 0.26022, 0.90913");
}
lu_table_template(template_9) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00175, 0.00610, 0.02132, 0.07449, 0.26022, 0.90913");
}
type ("in_n") {
base_type : array;
data_type : bit;
bit_width : 12;
bit_from : 11;
bit_to : 0;
}
type ("in_s") {
base_type : array;
data_type : bit;
bit_width : 3;
bit_from : 2;
bit_to : 0;
}
type ("out_n") {
base_type : array;
data_type : bit;
bit_width : 3;
bit_from : 2;
bit_to : 0;
}
type ("out_s") {
base_type : array;
data_type : bit;
bit_width : 12;
bit_from : 11;
bit_to : 0;
}
cell ("buff_flash_clkrst") {
pin("VPWR") {
direction : input;
capacitance : 0.0002;
}
pin("VGND") {
direction : input;
capacitance : 0.0002;
}
bus("in_n") {
bus_type : in_n;
direction : input;
capacitance : 0.0000;
pin("in_n[11]") {
direction : input;
capacitance : 0.0071;
}
pin("in_n[10]") {
direction : input;
capacitance : 0.0047;
}
pin("in_n[9]") {
direction : input;
capacitance : 0.0061;
}
pin("in_n[8]") {
direction : input;
capacitance : 0.0050;
}
pin("in_n[7]") {
direction : input;
capacitance : 0.0060;
}
pin("in_n[6]") {
direction : input;
capacitance : 0.0059;
}
pin("in_n[5]") {
direction : input;
capacitance : 0.0052;
}
pin("in_n[4]") {
direction : input;
capacitance : 0.0055;
}
pin("in_n[3]") {
direction : input;
capacitance : 0.0049;
}
pin("in_n[2]") {
direction : input;
capacitance : 0.0062;
}
pin("in_n[1]") {
direction : input;
capacitance : 0.0055;
}
pin("in_n[0]") {
direction : input;
capacitance : 0.0049;
}
}
bus("in_s") {
bus_type : in_s;
direction : input;
capacitance : 0.0000;
pin("in_s[2]") {
direction : input;
capacitance : 0.0049;
}
pin("in_s[1]") {
direction : input;
capacitance : 0.0061;
}
pin("in_s[0]") {
direction : input;
capacitance : 0.0047;
}
}
bus("out_n") {
bus_type : out_n;
direction : output;
capacitance : 0.0000;
pin("out_n[2]") {
direction : output;
capacitance : 0.0334;
timing() {
related_pin : "in_s[2]";
timing_sense : positive_unate;
timing_type : combinational;
cell_rise(template_29) {
values("0.12205,0.12483,0.13320,0.15618,0.22127,0.43583,1.18473");
}
rise_transition(template_29) {
values("0.02209,0.02435,0.03145,0.05499,0.13876,0.44350,1.51271");
}
cell_fall(template_30) {
values("0.12088,0.12342,0.13084,0.14981,0.19636,0.33046,0.78848");
}
fall_transition(template_30) {
values("0.02101,0.02246,0.02767,0.04268,0.08998,0.26118,0.88479");
}
}
}
pin("out_n[1]") {
direction : output;
capacitance : 0.0334;
timing() {
related_pin : "in_s[1]";
timing_sense : positive_unate;
timing_type : combinational;
cell_rise(template_27) {
values("0.12720,0.12998,0.13836,0.16133,0.22643,0.44114,1.18891");
}
rise_transition(template_27) {
values("0.02209,0.02433,0.03145,0.05498,0.13875,0.44330,1.51127");
}
cell_fall(template_28) {
values("0.12337,0.12590,0.13332,0.15231,0.19882,0.33296,0.79091");
}
fall_transition(template_28) {
values("0.02104,0.02245,0.02769,0.04266,0.08998,0.26119,0.88461");
}
}
}
pin("out_n[0]") {
direction : output;
capacitance : 0.0334;
timing() {
related_pin : "in_s[0]";
timing_sense : positive_unate;
timing_type : combinational;
cell_rise(template_25) {
values("0.12244,0.12522,0.13359,0.15658,0.22167,0.43621,1.18525");
}
rise_transition(template_25) {
values("0.02209,0.02435,0.03146,0.05499,0.13876,0.44352,1.51289");
}
cell_fall(template_26) {
values("0.12131,0.12386,0.13128,0.15024,0.19680,0.33089,0.78892");
}
fall_transition(template_26) {
values("0.02101,0.02246,0.02767,0.04268,0.08997,0.26118,0.88481");
}
}
}
}
bus("out_s") {
bus_type : out_s;
direction : output;
capacitance : 0.0000;
pin("out_s[11]") {
direction : output;
capacitance : 0.0334;
timing() {
related_pin : "in_n[11]";
timing_sense : positive_unate;
timing_type : combinational;
cell_rise(template_5) {
values("0.13459,0.13737,0.14576,0.16871,0.23382,0.44864,1.19553");
}
rise_transition(template_5) {
values("0.02209,0.02432,0.03144,0.05497,0.13874,0.44315,1.51013");
}
cell_fall(template_6) {
values("0.12778,0.13030,0.13772,0.15673,0.20321,0.33738,0.79528");
}
fall_transition(template_6) {
values("0.02106,0.02244,0.02770,0.04264,0.08998,0.26119,0.88446");
}
}
}
pin("out_s[10]") {
direction : output;
capacitance : 0.0334;
timing() {
related_pin : "in_n[10]";
timing_sense : positive_unate;
timing_type : combinational;
cell_rise(template_3) {
values("0.12170,0.12448,0.13285,0.15583,0.22093,0.43546,1.18452");
}
rise_transition(template_3) {
values("0.02209,0.02435,0.03146,0.05499,0.13876,0.44353,1.51292");
}
cell_fall(template_4) {
values("0.12079,0.12334,0.13076,0.14972,0.19628,0.33037,0.78841");
}
fall_transition(template_4) {
values("0.02101,0.02246,0.02767,0.04268,0.08997,0.26118,0.88481");
}
}
}
pin("out_s[9]") {
direction : output;
capacitance : 0.0334;
timing() {
related_pin : "in_n[9]";
timing_sense : positive_unate;
timing_type : combinational;
cell_rise(template_23) {
values("0.12666,0.12945,0.13783,0.16079,0.22589,0.44060,1.18840");
}
rise_transition(template_23) {
values("0.02209,0.02433,0.03145,0.05498,0.13875,0.44331,1.51130");
}
cell_fall(template_24) {
values("0.12300,0.12553,0.13296,0.15194,0.19846,0.33259,0.79055");
}
fall_transition(template_24) {
values("0.02104,0.02245,0.02769,0.04266,0.08998,0.26119,0.88461");
}
}
}
pin("out_s[8]") {
direction : output;
capacitance : 0.0334;
timing() {
related_pin : "in_n[8]";
timing_sense : positive_unate;
timing_type : combinational;
cell_rise(template_21) {
values("0.12260,0.12538,0.13375,0.15673,0.22183,0.43640,1.18519");
}
rise_transition(template_21) {
values("0.02209,0.02435,0.03145,0.05499,0.13876,0.44348,1.51258");
}
cell_fall(template_22) {
values("0.12116,0.12371,0.13113,0.15009,0.19664,0.33074,0.78876");
}
fall_transition(template_22) {
values("0.02102,0.02246,0.02767,0.04268,0.08998,0.26118,0.88477");
}
}
}
pin("out_s[7]") {
direction : output;
capacitance : 0.0334;
timing() {
related_pin : "in_n[7]";
timing_sense : positive_unate;
timing_type : combinational;
cell_rise(template_19) {
values("0.12734,0.13012,0.13850,0.16147,0.22657,0.44127,1.18913");
}
rise_transition(template_19) {
values("0.02209,0.02434,0.03145,0.05498,0.13875,0.44332,1.51139");
}
cell_fall(template_20) {
values("0.12358,0.12611,0.13354,0.15252,0.19904,0.33317,0.79113");
}
fall_transition(template_20) {
values("0.02104,0.02245,0.02769,0.04266,0.08998,0.26118,0.88462");
}
}
}
pin("out_s[6]") {
direction : output;
capacitance : 0.0334;
timing() {
related_pin : "in_n[6]";
timing_sense : positive_unate;
timing_type : combinational;
cell_rise(template_17) {
values("0.12738,0.13016,0.13854,0.16151,0.22661,0.44129,1.18928");
}
rise_transition(template_17) {
values("0.02209,0.02434,0.03145,0.05498,0.13875,0.44334,1.51155");
}
cell_fall(template_18) {
values("0.12376,0.12629,0.13371,0.15269,0.19922,0.33334,0.79131");
}
fall_transition(template_18) {
values("0.02104,0.02245,0.02768,0.04266,0.08998,0.26118,0.88464");
}
}
}
pin("out_s[5]") {
direction : output;
capacitance : 0.0334;
timing() {
related_pin : "in_n[5]";
timing_sense : positive_unate;
timing_type : combinational;
cell_rise(template_15) {
values("0.12304,0.12582,0.13419,0.15717,0.22227,0.43687,1.18545");
}
rise_transition(template_15) {
values("0.02209,0.02434,0.03145,0.05499,0.13876,0.44344,1.51232");
}
cell_fall(template_16) {
values("0.12125,0.12379,0.13122,0.15018,0.19673,0.33084,0.78884");
}
fall_transition(template_16) {
values("0.02102,0.02245,0.02767,0.04267,0.08998,0.26118,0.88474");
}
}
}
pin("out_s[4]") {
direction : output;
capacitance : 0.0334;
timing() {
related_pin : "in_n[4]";
timing_sense : positive_unate;
timing_type : combinational;
cell_rise(template_13) {
values("0.12397,0.12675,0.13513,0.15810,0.22320,0.43783,1.18618");
}
rise_transition(template_13) {
values("0.02209,0.02434,0.03145,0.05498,0.13875,0.44340,1.51201");
}
cell_fall(template_14) {
values("0.12166,0.12420,0.13163,0.15060,0.19714,0.33125,0.78924");
}
fall_transition(template_14) {
values("0.02103,0.02245,0.02768,0.04267,0.08998,0.26118,0.88470");
}
}
}
pin("out_s[3]") {
direction : output;
capacitance : 0.0334;
timing() {
related_pin : "in_n[3]";
timing_sense : positive_unate;
timing_type : combinational;
cell_rise(template_11) {
values("0.12175,0.12453,0.13290,0.15588,0.22098,0.43553,1.18443");
}
rise_transition(template_11) {
values("0.02209,0.02435,0.03145,0.05499,0.13876,0.44350,1.51271");
}
cell_fall(template_12) {
values("0.12066,0.12320,0.13063,0.14959,0.19614,0.33024,0.78826");
}
fall_transition(template_12) {
values("0.02101,0.02246,0.02767,0.04268,0.08998,0.26118,0.88479");
}
}
}
pin("out_s[2]") {
direction : output;
capacitance : 0.0334;
timing() {
related_pin : "in_n[2]";
timing_sense : positive_unate;
timing_type : combinational;
cell_rise(template_9) {
values("0.12766,0.13044,0.13883,0.16179,0.22689,0.44161,1.18933");
}
rise_transition(template_9) {
values("0.02209,0.02433,0.03145,0.05498,0.13875,0.44330,1.51120");
}
cell_fall(template_10) {
values("0.12366,0.12619,0.13361,0.15260,0.19911,0.33325,0.79120");
}
fall_transition(template_10) {
values("0.02104,0.02245,0.02769,0.04266,0.08998,0.26119,0.88460");
}
}
}
pin("out_s[1]") {
direction : output;
capacitance : 0.0334;
timing() {
related_pin : "in_n[1]";
timing_sense : positive_unate;
timing_type : combinational;
cell_rise(template_7) {
values("0.12485,0.12763,0.13601,0.15898,0.22408,0.43872,1.18704");
}
rise_transition(template_7) {
values("0.02209,0.02434,0.03145,0.05498,0.13875,0.44340,1.51198");
}
cell_fall(template_8) {
values("0.12228,0.12482,0.13224,0.15122,0.19775,0.33187,0.78986");
}
fall_transition(template_8) {
values("0.02103,0.02245,0.02768,0.04267,0.08998,0.26118,0.88469");
}
}
}
pin("out_s[0]") {
direction : output;
capacitance : 0.0334;
timing() {
related_pin : "in_n[0]";
timing_sense : positive_unate;
timing_type : combinational;
cell_rise(template_1) {
values("0.12197,0.12475,0.13312,0.15611,0.22120,0.43576,1.18463");
}
rise_transition(template_1) {
values("0.02209,0.02435,0.03145,0.05499,0.13876,0.44349,1.51268");
}
cell_fall(template_2) {
values("0.12080,0.12335,0.13077,0.14973,0.19629,0.33038,0.78841");
}
fall_transition(template_2) {
values("0.02102,0.02246,0.02767,0.04268,0.08998,0.26118,0.88478");
}
}
}
}
}
}

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172
maglef/buff_flash_clkrst.mag Normal file
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@ -0,0 +1,172 @@
magic
tech sky130A
magscale 1 2
timestamp 1665682150
<< nwell >>
rect 330 3525 7582 3846
rect 330 2437 7582 3003
rect 330 1349 7582 1915
<< obsli1 >>
rect 368 1071 7544 3825
<< obsm1 >>
rect 368 1040 7699 3856
<< metal2 >>
rect 754 4200 810 5000
rect 1214 4200 1270 5000
rect 1674 4200 1730 5000
rect 2134 4200 2190 5000
rect 2594 4200 2650 5000
rect 3054 4200 3110 5000
rect 3514 4200 3570 5000
rect 3974 4200 4030 5000
rect 4434 4200 4490 5000
rect 4894 4200 4950 5000
rect 5354 4200 5410 5000
rect 5814 4200 5870 5000
rect 6274 4200 6330 5000
rect 6734 4200 6790 5000
rect 7194 4200 7250 5000
rect 754 0 810 800
rect 1214 0 1270 800
rect 1674 0 1730 800
rect 2134 0 2190 800
rect 2594 0 2650 800
rect 3054 0 3110 800
rect 3514 0 3570 800
rect 3974 0 4030 800
rect 4434 0 4490 800
rect 4894 0 4950 800
rect 5354 0 5410 800
rect 5814 0 5870 800
rect 6274 0 6330 800
rect 6734 0 6790 800
rect 7194 0 7250 800
<< obsm2 >>
rect 866 4144 1158 4298
rect 1326 4144 1618 4298
rect 1786 4144 2078 4298
rect 2246 4144 2538 4298
rect 2706 4144 2998 4298
rect 3166 4144 3458 4298
rect 3626 4144 3918 4298
rect 4086 4144 4378 4298
rect 4546 4144 4838 4298
rect 5006 4144 5298 4298
rect 5466 4144 5758 4298
rect 5926 4144 6218 4298
rect 6386 4144 6678 4298
rect 6846 4144 7138 4298
rect 7306 4144 7693 4298
rect 756 856 7693 4144
rect 866 734 1158 856
rect 1326 734 1618 856
rect 1786 734 2078 856
rect 2246 734 2538 856
rect 2706 734 2998 856
rect 3166 734 3458 856
rect 3626 734 3918 856
rect 4086 734 4378 856
rect 4546 734 4838 856
rect 5006 734 5298 856
rect 5466 734 5758 856
rect 5926 734 6218 856
rect 6386 734 6678 856
rect 6846 734 7138 856
rect 7306 734 7693 856
<< obsm3 >>
rect 1106 1055 7697 3841
<< metal4 >>
rect 1104 1040 1424 3856
rect 2000 1040 2320 3856
rect 2897 1040 3217 3856
rect 3793 1040 4113 3856
rect 4690 1040 5010 3856
rect 5586 1040 5906 3856
rect 6483 1040 6803 3856
rect 7379 1040 7699 3856
<< labels >>
rlabel metal4 s 2000 1040 2320 3856 6 VGND
port 1 nsew ground bidirectional
rlabel metal4 s 3793 1040 4113 3856 6 VGND
port 1 nsew ground bidirectional
rlabel metal4 s 5586 1040 5906 3856 6 VGND
port 1 nsew ground bidirectional
rlabel metal4 s 7379 1040 7699 3856 6 VGND
port 1 nsew ground bidirectional
rlabel metal4 s 1104 1040 1424 3856 6 VPWR
port 2 nsew power bidirectional
rlabel metal4 s 2897 1040 3217 3856 6 VPWR
port 2 nsew power bidirectional
rlabel metal4 s 4690 1040 5010 3856 6 VPWR
port 2 nsew power bidirectional
rlabel metal4 s 6483 1040 6803 3856 6 VPWR
port 2 nsew power bidirectional
rlabel metal2 s 2134 4200 2190 5000 6 in_n[0]
port 3 nsew signal input
rlabel metal2 s 6734 4200 6790 5000 6 in_n[10]
port 4 nsew signal input
rlabel metal2 s 7194 4200 7250 5000 6 in_n[11]
port 5 nsew signal input
rlabel metal2 s 2594 4200 2650 5000 6 in_n[1]
port 6 nsew signal input
rlabel metal2 s 3054 4200 3110 5000 6 in_n[2]
port 7 nsew signal input
rlabel metal2 s 3514 4200 3570 5000 6 in_n[3]
port 8 nsew signal input
rlabel metal2 s 3974 4200 4030 5000 6 in_n[4]
port 9 nsew signal input
rlabel metal2 s 4434 4200 4490 5000 6 in_n[5]
port 10 nsew signal input
rlabel metal2 s 4894 4200 4950 5000 6 in_n[6]
port 11 nsew signal input
rlabel metal2 s 5354 4200 5410 5000 6 in_n[7]
port 12 nsew signal input
rlabel metal2 s 5814 4200 5870 5000 6 in_n[8]
port 13 nsew signal input
rlabel metal2 s 6274 4200 6330 5000 6 in_n[9]
port 14 nsew signal input
rlabel metal2 s 754 0 810 800 6 in_s[0]
port 15 nsew signal input
rlabel metal2 s 1214 0 1270 800 6 in_s[1]
port 16 nsew signal input
rlabel metal2 s 1674 0 1730 800 6 in_s[2]
port 17 nsew signal input
rlabel metal2 s 754 4200 810 5000 6 out_n[0]
port 18 nsew signal output
rlabel metal2 s 1214 4200 1270 5000 6 out_n[1]
port 19 nsew signal output
rlabel metal2 s 1674 4200 1730 5000 6 out_n[2]
port 20 nsew signal output
rlabel metal2 s 2134 0 2190 800 6 out_s[0]
port 21 nsew signal output
rlabel metal2 s 6734 0 6790 800 6 out_s[10]
port 22 nsew signal output
rlabel metal2 s 7194 0 7250 800 6 out_s[11]
port 23 nsew signal output
rlabel metal2 s 2594 0 2650 800 6 out_s[1]
port 24 nsew signal output
rlabel metal2 s 3054 0 3110 800 6 out_s[2]
port 25 nsew signal output
rlabel metal2 s 3514 0 3570 800 6 out_s[3]
port 26 nsew signal output
rlabel metal2 s 3974 0 4030 800 6 out_s[4]
port 27 nsew signal output
rlabel metal2 s 4434 0 4490 800 6 out_s[5]
port 28 nsew signal output
rlabel metal2 s 4894 0 4950 800 6 out_s[6]
port 29 nsew signal output
rlabel metal2 s 5354 0 5410 800 6 out_s[7]
port 30 nsew signal output
rlabel metal2 s 5814 0 5870 800 6 out_s[8]
port 31 nsew signal output
rlabel metal2 s 6274 0 6330 800 6 out_s[9]
port 32 nsew signal output
<< properties >>
string FIXED_BBOX 0 0 8000 5000
string LEFclass BLOCK
string LEFview TRUE
string GDS_END 83666
string GDS_FILE /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/results/signoff/buff_flash_clkrst.magic.gds
string GDS_START 25066
<< end >>

48
openlane/buff_flash_clkrst/config.tcl Normal file
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@ -0,0 +1,48 @@
# SPDX-FileCopyrightText: 2020 Efabless Corporation
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
# SPDX-License-Identifier: Apache-2.0
set script_dir [file dirname [file normalize [info script]]]
# virtual clock
set ::env(CLOCK_PERIOD) 8
set ::env(CLOCK_PORT) ""
set ::env(DESIGN_NAME) buff_flash_clkrst
set ::env(DESIGN_IS_CORE) 0
# set ::env(DESIGN_IS_CORE) 1
set ::env(SYNTH_READ_BLACKBOX_LIB) 1
set ::env(FP_SIZING) "absolute"
set ::env(DIE_AREA) "0 0 40 25"
# set ::env(CORE_AREA) "1 1 19 19"
set ::env(VERILOG_FILES) "$::env(DESIGN_DIR)/../../verilog/rtl/buff_flash_clkrst.v"
set ::env(DRC_EXCLUDE_CELL_LIST) [glob $::env(DESIGN_DIR)/drc_exclude.list]
set ::env(FP_PIN_ORDER_CFG) [glob $::env(DESIGN_DIR)/pin_order.cfg]
set ::env(FP_PDN_VOFFSET) 2
set ::env(FP_PDN_VPITCH) 7
set ::env(FP_PDN_VSPACING) 2
set ::env(PL_TARGET_DENSITY) 0.96
# set ::env(FP_CORE_UTIL) 0.99
set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 0
set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 0
set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) 0
set ::env(SYNTH_BUFFERING) 0
set ::env(SYNTH_SIZING) 0
set ::env(TAP_DECAP_INSERTION) 1
set ::env(CLOCK_TREE_SYNTH) 0
set ::env(RIGHT_MARGIN_MULT) {4}
set ::env(LEFT_MARGIN_MULT) {4}
set ::env(TOP_MARGIN_MULT) {2}
set ::env(BOTTOM_MARGIN_MULT) {2}
set ::env(MAGIC_EXT_USE_GDS) 1

80
openlane/buff_flash_clkrst/drc_exclude.list Normal file
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@ -0,0 +1,80 @@
sky130_fd_sc_hd__a2111oi_0
sky130_fd_sc_hd__a21boi_0
sky130_fd_sc_hd__and2_0
sky130_fd_sc_hd__buf_16
sky130_fd_sc_hd__clkdlybuf4s15_1
sky130_fd_sc_hd__clkdlybuf4s18_1
sky130_fd_sc_hd__fa_4
sky130_fd_sc_hd__lpflow_bleeder_1
sky130_fd_sc_hd__lpflow_clkbufkapwr_1
sky130_fd_sc_hd__lpflow_clkbufkapwr_16
sky130_fd_sc_hd__lpflow_clkbufkapwr_2
sky130_fd_sc_hd__lpflow_clkbufkapwr_4
sky130_fd_sc_hd__lpflow_clkbufkapwr_8
sky130_fd_sc_hd__lpflow_clkinvkapwr_1
sky130_fd_sc_hd__lpflow_clkinvkapwr_16
sky130_fd_sc_hd__lpflow_clkinvkapwr_2
sky130_fd_sc_hd__lpflow_clkinvkapwr_4
sky130_fd_sc_hd__lpflow_clkinvkapwr_8
sky130_fd_sc_hd__lpflow_decapkapwr_12
sky130_fd_sc_hd__lpflow_decapkapwr_3
sky130_fd_sc_hd__lpflow_decapkapwr_4
sky130_fd_sc_hd__lpflow_decapkapwr_6
sky130_fd_sc_hd__lpflow_decapkapwr_8
sky130_fd_sc_hd__lpflow_inputiso0n_1
sky130_fd_sc_hd__lpflow_inputiso0p_1
sky130_fd_sc_hd__lpflow_inputiso1n_1
sky130_fd_sc_hd__lpflow_inputiso1p_1
sky130_fd_sc_hd__lpflow_inputisolatch_1
sky130_fd_sc_hd__lpflow_isobufsrc_1
sky130_fd_sc_hd__lpflow_isobufsrc_16
sky130_fd_sc_hd__lpflow_isobufsrc_2
sky130_fd_sc_hd__lpflow_isobufsrc_4
sky130_fd_sc_hd__lpflow_isobufsrc_8
sky130_fd_sc_hd__lpflow_isobufsrckapwr_16
sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1
sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2
sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4
sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_4
sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1
sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2
sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4
sky130_fd_sc_hd__mux4_4
sky130_fd_sc_hd__o21ai_0
sky130_fd_sc_hd__o311ai_0
sky130_fd_sc_hd__or2_0
sky130_fd_sc_hd__probe_p_8
sky130_fd_sc_hd__probec_p_8
sky130_fd_sc_hd__xor3_1
sky130_fd_sc_hd__xor3_2
sky130_fd_sc_hd__xor3_4
sky130_fd_sc_hd__xnor3_1
sky130_fd_sc_hd__xnor3_2
sky130_fd_sc_hd__xnor3_4
sky130_fd_sc_hd__clkbuf_1
sky130_fd_sc_hd__clkbuf_2
sky130_fd_sc_hd__clkbuf_12
sky130_fd_sc_hd__clkbuf_16
sky130_fd_sc_hd__clkdlybuf4s15_1
sky130_fd_sc_hd__clkdlybuf4s15_2
sky130_fd_sc_hd__clkdlybuf4s18_1
sky130_fd_sc_hd__clkdlybuf4s18_2
sky130_fd_sc_hd__clkdlybuf4s25_1
sky130_fd_sc_hd__clkdlybuf4s25_2
sky130_fd_sc_hd__clkdlybuf4s50_1
sky130_fd_sc_hd__clkdlybuf4s50_2
sky130_fd_sc_hd__dlygate4sd1_1
sky130_fd_sc_hd__dlygate4sd2_1
sky130_fd_sc_hd__dlygate4sd3_1
sky130_fd_sc_hd__dlymetal6s2s_1
sky130_fd_sc_hd__dlymetal6s4s_1
sky130_fd_sc_hd__dlymetal6s6s_1
sky130_fd_sc_hd__buf_1
sky130_fd_sc_hd__buf_2
sky130_fd_sc_hd__buf_12
sky130_fd_sc_hd__decap_3
sky130_ef_sc_hd__decap_12
sky130_fd_sc_hd__decap_4
sky130_fd_sc_hd__decap_8
sky130_fd_sc_hd__decap_3
sky130_fd_sc_hd__decap_6

7
openlane/buff_flash_clkrst/pin_order.cfg Normal file
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@ -0,0 +1,7 @@
#S
in_s.*
out_s.*
#N
out_n.*
in_n.*

79
sdc/buff_flash_clkrst.sdc Normal file
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@ -0,0 +1,79 @@
###############################################################################
# Created by write_sdc
# Thu Oct 13 17:28:51 2022
###############################################################################
current_design buff_flash_clkrst
###############################################################################
# Timing Constraints
###############################################################################
create_clock -name __VIRTUAL_CLK__ -period 8.0000
set_clock_uncertainty 0.2500 __VIRTUAL_CLK__
set_input_delay 1.6000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {in_n[0]}]
set_input_delay 1.6000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {in_n[10]}]
set_input_delay 1.6000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {in_n[11]}]
set_input_delay 1.6000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {in_n[1]}]
set_input_delay 1.6000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {in_n[2]}]
set_input_delay 1.6000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {in_n[3]}]
set_input_delay 1.6000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {in_n[4]}]
set_input_delay 1.6000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {in_n[5]}]
set_input_delay 1.6000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {in_n[6]}]
set_input_delay 1.6000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {in_n[7]}]
set_input_delay 1.6000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {in_n[8]}]
set_input_delay 1.6000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {in_n[9]}]
set_input_delay 1.6000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {in_s[0]}]
set_input_delay 1.6000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {in_s[1]}]
set_input_delay 1.6000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {in_s[2]}]
set_output_delay 1.6000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {out_n[0]}]
set_output_delay 1.6000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {out_n[1]}]
set_output_delay 1.6000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {out_n[2]}]
set_output_delay 1.6000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {out_s[0]}]
set_output_delay 1.6000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {out_s[10]}]
set_output_delay 1.6000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {out_s[11]}]
set_output_delay 1.6000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {out_s[1]}]
set_output_delay 1.6000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {out_s[2]}]
set_output_delay 1.6000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {out_s[3]}]
set_output_delay 1.6000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {out_s[4]}]
set_output_delay 1.6000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {out_s[5]}]
set_output_delay 1.6000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {out_s[6]}]
set_output_delay 1.6000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {out_s[7]}]
set_output_delay 1.6000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {out_s[8]}]
set_output_delay 1.6000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {out_s[9]}]
###############################################################################
# Environment
###############################################################################
set_load -pin_load 0.0334 [get_ports {out_n[2]}]
set_load -pin_load 0.0334 [get_ports {out_n[1]}]
set_load -pin_load 0.0334 [get_ports {out_n[0]}]
set_load -pin_load 0.0334 [get_ports {out_s[11]}]
set_load -pin_load 0.0334 [get_ports {out_s[10]}]
set_load -pin_load 0.0334 [get_ports {out_s[9]}]
set_load -pin_load 0.0334 [get_ports {out_s[8]}]
set_load -pin_load 0.0334 [get_ports {out_s[7]}]
set_load -pin_load 0.0334 [get_ports {out_s[6]}]
set_load -pin_load 0.0334 [get_ports {out_s[5]}]
set_load -pin_load 0.0334 [get_ports {out_s[4]}]
set_load -pin_load 0.0334 [get_ports {out_s[3]}]
set_load -pin_load 0.0334 [get_ports {out_s[2]}]
set_load -pin_load 0.0334 [get_ports {out_s[1]}]
set_load -pin_load 0.0334 [get_ports {out_s[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {in_n[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {in_n[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {in_n[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {in_n[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {in_n[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {in_n[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {in_n[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {in_n[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {in_n[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {in_n[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {in_n[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {in_n[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {in_s[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {in_s[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {in_s[0]}]
set_timing_derate -early 0.9500
set_timing_derate -late 1.0500
###############################################################################
# Design Rules
###############################################################################
set_max_fanout 10.0000 [current_design]

186
sdf/buff_flash_clkrst.sdf Normal file
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(DELAYFILE
(SDFVERSION "3.0")
(DESIGN "buff_flash_clkrst")
(DATE "Thu Oct 13 17:29:08 2022")
(VENDOR "Parallax")
(PROGRAM "STA")
(VERSION "2.3.1")
(DIVIDER .)
(VOLTAGE 1.800::1.800)
(PROCESS "1.000::1.000")
(TEMPERATURE 25.000::25.000)
(TIMESCALE 1ns)
(CELL
(CELLTYPE "buff_flash_clkrst")
(INSTANCE)
(DELAY
(ABSOLUTE
(INTERCONNECT in_n[0] BUF\[3\].A (0.018:0.018:0.018) (0.007:0.007:0.007))
(INTERCONNECT in_n[10] BUF\[13\].A (0.017:0.017:0.017) (0.007:0.007:0.007))
(INTERCONNECT in_n[11] BUF\[14\].A (0.025:0.025:0.025) (0.011:0.011:0.011))
(INTERCONNECT in_n[1] BUF\[4\].A (0.019:0.019:0.019) (0.008:0.008:0.008))
(INTERCONNECT in_n[2] BUF\[5\].A (0.022:0.022:0.022) (0.009:0.009:0.009))
(INTERCONNECT in_n[3] BUF\[6\].A (0.017:0.017:0.017) (0.007:0.007:0.007))
(INTERCONNECT in_n[4] BUF\[7\].A (0.019:0.019:0.019) (0.008:0.008:0.008))
(INTERCONNECT in_n[5] BUF\[8\].A (0.019:0.019:0.019) (0.008:0.008:0.008))
(INTERCONNECT in_n[6] BUF\[9\].A (0.021:0.021:0.021) (0.009:0.009:0.009))
(INTERCONNECT in_n[7] BUF\[10\].A (0.021:0.021:0.021) (0.009:0.009:0.009))
(INTERCONNECT in_n[8] BUF\[11\].A (0.018:0.018:0.018) (0.007:0.007:0.007))
(INTERCONNECT in_n[9] BUF\[12\].A (0.021:0.021:0.021) (0.009:0.009:0.009))
(INTERCONNECT in_s[0] BUF\[0\].A (0.017:0.017:0.017) (0.007:0.007:0.007))
(INTERCONNECT in_s[1] BUF\[1\].A (0.021:0.021:0.021) (0.009:0.009:0.009))
(INTERCONNECT in_s[2] BUF\[2\].A (0.017:0.017:0.017) (0.007:0.007:0.007))
(INTERCONNECT BUF\[0\].X out_n[0] (0.001:0.001:0.001) (0.001:0.001:0.001))
(INTERCONNECT BUF\[10\].X out_s[7] (0.001:0.001:0.001) (0.001:0.001:0.001))
(INTERCONNECT BUF\[11\].X out_s[8] (0.001:0.001:0.001) (0.001:0.001:0.001))
(INTERCONNECT BUF\[12\].X out_s[9] (0.001:0.001:0.001) (0.001:0.001:0.001))
(INTERCONNECT BUF\[13\].X out_s[10] (0.001:0.001:0.001) (0.001:0.001:0.001))
(INTERCONNECT BUF\[14\].X out_s[11] (0.001:0.001:0.001) (0.001:0.001:0.001))
(INTERCONNECT BUF\[1\].X out_n[1] (0.001:0.001:0.001) (0.001:0.001:0.001))
(INTERCONNECT BUF\[2\].X out_n[2] (0.001:0.001:0.001) (0.001:0.001:0.001))
(INTERCONNECT BUF\[3\].X out_s[0] (0.001:0.001:0.001) (0.001:0.001:0.001))
(INTERCONNECT BUF\[4\].X out_s[1] (0.001:0.001:0.001) (0.001:0.001:0.001))
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(DATE "Thu Oct 13 17:29:07 2022")
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(PROGRAM "STA")
(VERSION "2.3.1")
(DIVIDER .)
(VOLTAGE 1.600::1.600)
(PROCESS "1.000::1.000")
(TEMPERATURE 100.000::100.000)
(TIMESCALE 1ns)
(CELL
(CELLTYPE "buff_flash_clkrst")
(INSTANCE)
(DELAY
(ABSOLUTE
(INTERCONNECT in_n[0] BUF\[3\].A (0.018:0.018:0.018) (0.007:0.007:0.007))
(INTERCONNECT in_n[10] BUF\[13\].A (0.017:0.017:0.017) (0.007:0.007:0.007))
(INTERCONNECT in_n[11] BUF\[14\].A (0.025:0.025:0.025) (0.011:0.011:0.011))
(INTERCONNECT in_n[1] BUF\[4\].A (0.019:0.019:0.019) (0.008:0.008:0.008))
(INTERCONNECT in_n[2] BUF\[5\].A (0.022:0.022:0.022) (0.009:0.009:0.009))
(INTERCONNECT in_n[3] BUF\[6\].A (0.017:0.017:0.017) (0.007:0.007:0.007))
(INTERCONNECT in_n[4] BUF\[7\].A (0.019:0.019:0.019) (0.008:0.008:0.008))
(INTERCONNECT in_n[5] BUF\[8\].A (0.019:0.019:0.019) (0.008:0.008:0.008))
(INTERCONNECT in_n[6] BUF\[9\].A (0.021:0.021:0.021) (0.009:0.009:0.009))
(INTERCONNECT in_n[7] BUF\[10\].A (0.021:0.021:0.021) (0.009:0.009:0.009))
(INTERCONNECT in_n[8] BUF\[11\].A (0.018:0.018:0.018) (0.007:0.007:0.007))
(INTERCONNECT in_n[9] BUF\[12\].A (0.021:0.021:0.021) (0.009:0.009:0.009))
(INTERCONNECT in_s[0] BUF\[0\].A (0.017:0.017:0.017) (0.007:0.007:0.007))
(INTERCONNECT in_s[1] BUF\[1\].A (0.021:0.021:0.021) (0.009:0.009:0.009))
(INTERCONNECT in_s[2] BUF\[2\].A (0.017:0.017:0.017) (0.007:0.007:0.007))
(INTERCONNECT BUF\[0\].X out_n[0] (0.001:0.001:0.001) (0.001:0.001:0.001))
(INTERCONNECT BUF\[10\].X out_s[7] (0.001:0.001:0.001) (0.001:0.001:0.001))
(INTERCONNECT BUF\[11\].X out_s[8] (0.001:0.001:0.001) (0.001:0.001:0.001))
(INTERCONNECT BUF\[12\].X out_s[9] (0.001:0.001:0.001) (0.001:0.001:0.001))
(INTERCONNECT BUF\[13\].X out_s[10] (0.001:0.001:0.001) (0.001:0.001:0.001))
(INTERCONNECT BUF\[14\].X out_s[11] (0.001:0.001:0.001) (0.001:0.001:0.001))
(INTERCONNECT BUF\[1\].X out_n[1] (0.001:0.001:0.001) (0.001:0.001:0.001))
(INTERCONNECT BUF\[2\].X out_n[2] (0.001:0.001:0.001) (0.001:0.001:0.001))
(INTERCONNECT BUF\[3\].X out_s[0] (0.001:0.001:0.001) (0.001:0.001:0.001))
(INTERCONNECT BUF\[4\].X out_s[1] (0.001:0.001:0.001) (0.001:0.001:0.001))
(INTERCONNECT BUF\[5\].X out_s[2] (0.001:0.001:0.001) (0.001:0.001:0.001))
(INTERCONNECT BUF\[6\].X out_s[3] (0.001:0.001:0.001) (0.001:0.001:0.001))
(INTERCONNECT BUF\[7\].X out_s[4] (0.001:0.001:0.001) (0.001:0.001:0.001))
(INTERCONNECT BUF\[8\].X out_s[5] (0.001:0.001:0.001) (0.001:0.001:0.001))
(INTERCONNECT BUF\[9\].X out_s[6] (0.001:0.001:0.001) (0.001:0.001:0.001))
)
)
)
(CELL
(CELLTYPE "sky130_fd_sc_hd__clkbuf_8")
(INSTANCE BUF\[0\])
(DELAY
(ABSOLUTE
(IOPATH A X (0.145:0.145:0.145) (0.145:0.145:0.145))
)
)
)
(CELL
(CELLTYPE "sky130_fd_sc_hd__clkbuf_8")
(INSTANCE BUF\[10\])
(DELAY
(ABSOLUTE
(IOPATH A X (0.146:0.146:0.146) (0.146:0.146:0.146))
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)
)
(CELL
(CELLTYPE "sky130_fd_sc_hd__clkbuf_8")
(INSTANCE BUF\[11\])
(DELAY
(ABSOLUTE
(IOPATH A X (0.145:0.145:0.145) (0.145:0.145:0.145))
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)
)
(CELL
(CELLTYPE "sky130_fd_sc_hd__clkbuf_8")
(INSTANCE BUF\[12\])
(DELAY
(ABSOLUTE
(IOPATH A X (0.145:0.145:0.145) (0.145:0.145:0.145))
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(CELL
(CELLTYPE "sky130_fd_sc_hd__clkbuf_8")
(INSTANCE BUF\[13\])
(DELAY
(ABSOLUTE
(IOPATH A X (0.145:0.145:0.145) (0.145:0.145:0.145))
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)
)
(CELL
(CELLTYPE "sky130_fd_sc_hd__clkbuf_8")
(INSTANCE BUF\[14\])
(DELAY
(ABSOLUTE
(IOPATH A X (0.149:0.149:0.149) (0.148:0.148:0.148))
)
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)
(CELL
(CELLTYPE "sky130_fd_sc_hd__clkbuf_8")
(INSTANCE BUF\[1\])
(DELAY
(ABSOLUTE
(IOPATH A X (0.146:0.146:0.146) (0.145:0.145:0.145))
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(CELL
(CELLTYPE "sky130_fd_sc_hd__clkbuf_8")
(INSTANCE BUF\[2\])
(DELAY
(ABSOLUTE
(IOPATH A X (0.144:0.144:0.144) (0.145:0.145:0.145))
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(CELL
(CELLTYPE "sky130_fd_sc_hd__clkbuf_8")
(INSTANCE BUF\[3\])
(DELAY
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(IOPATH A X (0.144:0.144:0.144) (0.145:0.145:0.145))
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(CELL
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(INSTANCE BUF\[4\])
(DELAY
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(CELL
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(INSTANCE BUF\[5\])
(DELAY
(ABSOLUTE
(IOPATH A X (0.146:0.146:0.146) (0.145:0.145:0.145))
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)
(CELL
(CELLTYPE "sky130_fd_sc_hd__clkbuf_8")
(INSTANCE BUF\[6\])
(DELAY
(ABSOLUTE
(IOPATH A X (0.144:0.144:0.144) (0.145:0.145:0.145))
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)
(CELL
(CELLTYPE "sky130_fd_sc_hd__clkbuf_8")
(INSTANCE BUF\[7\])
(DELAY
(ABSOLUTE
(IOPATH A X (0.145:0.145:0.145) (0.145:0.145:0.145))
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)
(CELL
(CELLTYPE "sky130_fd_sc_hd__clkbuf_8")
(INSTANCE BUF\[8\])
(DELAY
(ABSOLUTE
(IOPATH A X (0.144:0.144:0.144) (0.145:0.145:0.145))
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(CELL
(CELLTYPE "sky130_fd_sc_hd__clkbuf_8")
(INSTANCE BUF\[9\])
(DELAY
(ABSOLUTE
(IOPATH A X (0.146:0.146:0.146) (0.146:0.146:0.146))
)
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)
)

1
signoff/buff_flash_clkrst/OPENLANE_VERSION Normal file
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OpenLane e3a5189a1b0fc4290686fcf2ae46cd6d7947cf9f

1
signoff/buff_flash_clkrst/PDK_SOURCES Normal file
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open_pdks de752ec0ba4da0ecb1fbcd309eeec4993d88f5bc

2
signoff/buff_flash_clkrst/metrics.csv Normal file
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design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,CoreArea_um^2,power_slowest_internal_uW,power_slowest_switching_uW,power_slowest_leakage_uW,power_typical_internal_uW,power_typical_switching_uW,power_typical_leakage_uW,power_fastest_internal_uW,power_fastest_switching_uW,power_fastest_leakage_uW,critical_path_ns,suggested_clock_period,suggested_clock_frequency,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GRT_ADJUSTMENT,STD_CELL_LIBRARY,DIODE_INSERTION_STRATEGY
/home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst,buff_flash_clkrst,22_10_13_10_28,flow completed,0h0m29s0ms,0h0m13s0ms,-2.0,0.001,-1,46.74,481.88,-1,0,0,0,0,0,0,0,-1,-1,-1,-1,357,60,0.0,0.0,-1,0.0,0.0,0.0,0.0,-1,0.0,0.0,376761.0,0.0,5.19,13.85,0.0,0.0,0.0,4,30,4,30,0,0,0,15,0,0,0,0,0,0,0,0,-1,-1,-1,10,7,0,17,487.96799999999985,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,8.0,125.0,8,AREA 0,10,50,1,8.965,3.395,0.96,0.3,sky130_fd_sc_hd,3
1 design design_name config flow_status total_runtime routed_runtime (Cell/mm^2)/Core_Util DIEAREA_mm^2 CellPer_mm^2 OpenDP_Util Peak_Memory_Usage_MB cell_count tritonRoute_violations Short_violations MetSpc_violations OffGrid_violations MinHole_violations Other_violations Magic_violations antenna_violations lvs_total_errors cvc_total_errors klayout_violations wire_length vias wns pl_wns optimized_wns fastroute_wns spef_wns tns pl_tns optimized_tns fastroute_tns spef_tns HPWL routing_layer1_pct routing_layer2_pct routing_layer3_pct routing_layer4_pct routing_layer5_pct routing_layer6_pct wires_count wire_bits public_wires_count public_wire_bits memories_count memory_bits processes_count cells_pre_abc AND DFF NAND NOR OR XOR XNOR MUX inputs outputs level EndCaps TapCells Diodes Total_Physical_Cells CoreArea_um^2 power_slowest_internal_uW power_slowest_switching_uW power_slowest_leakage_uW power_typical_internal_uW power_typical_switching_uW power_typical_leakage_uW power_fastest_internal_uW power_fastest_switching_uW power_fastest_leakage_uW critical_path_ns suggested_clock_period suggested_clock_frequency CLOCK_PERIOD SYNTH_STRATEGY SYNTH_MAX_FANOUT FP_CORE_UTIL FP_ASPECT_RATIO FP_PDN_VPITCH FP_PDN_HPITCH PL_TARGET_DENSITY GRT_ADJUSTMENT STD_CELL_LIBRARY DIODE_INSERTION_STRATEGY
2 /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst buff_flash_clkrst 22_10_13_10_28 flow completed 0h0m29s0ms 0h0m13s0ms -2.0 0.001 -1 46.74 481.88 -1 0 0 0 0 0 0 0 -1 -1 -1 -1 357 60 0.0 0.0 -1 0.0 0.0 0.0 0.0 -1 0.0 0.0 376761.0 0.0 5.19 13.85 0.0 0.0 0.0 4 30 4 30 0 0 0 15 0 0 0 0 0 0 0 0 -1 -1 -1 10 7 0 17 487.96799999999985 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 8.0 125.0 8 AREA 0 10 50 1 8.965 3.395 0.96 0.3 sky130_fd_sc_hd 3

40
signoff/buff_flash_clkrst/openlane-signoff/14-parasitics_extraction.min.log Normal file
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OpenROAD 4174c3ad802d2ac1d04d387d2c4b883903f6647e
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO ODB-0222] Reading LEF file: /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/tmp/merged.min.lef
[WARNING ODB-0220] WARNING (LEFPARS-2036): SOURCE statement is obsolete in version 5.6 and later.
The LEF parser will ignore this statement.
To avoid this warning in the future, remove this statement from the LEF file with version 5.6 or later. See file /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/tmp/merged.min.lef at line 930.
[INFO ODB-0223] Created 13 technology layers
[INFO ODB-0224] Created 25 technology vias
[INFO ODB-0225] Created 441 library cells
[INFO ODB-0226] Finished LEF file: /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/tmp/merged.min.lef
[INFO ODB-0127] Reading DEF file: /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/results/routing/buff_flash_clkrst.def
[INFO ODB-0128] Design: buff_flash_clkrst
[INFO ODB-0130] Created 32 pins.
[INFO ODB-0131] Created 73 components and 308 component-terminals.
[INFO ODB-0132] Created 2 special nets and 278 connections.
[INFO ODB-0133] Created 30 nets and 30 connections.
[INFO ODB-0134] Finished DEF file: /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/results/routing/buff_flash_clkrst.def
Using RCX ruleset '/home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.tech/openlane/rules.openrcx.sky130A.min.calibre'...
[INFO RCX-0431] Defined process_corner X with ext_model_index 0
[INFO RCX-0029] Defined extraction corner X
[INFO RCX-0008] extracting parasitics of buff_flash_clkrst ...
[INFO RCX-0435] Reading extraction model file /home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.tech/openlane/rules.openrcx.sky130A.min.calibre ...
[INFO RCX-0436] RC segment generation buff_flash_clkrst (max_merge_res 50.0) ...
[INFO RCX-0040] Final 30 rc segments
[INFO RCX-0439] Coupling Cap extraction buff_flash_clkrst ...
[INFO RCX-0440] Coupling threshhold is 0.1000 fF, coupling capacitance less than 0.1000 fF will be grounded.
[INFO RCX-0043] 156 wires to be extracted
[INFO RCX-0442] 66% completion -- 103 wires have been extracted
[INFO RCX-0442] 100% completion -- 156 wires have been extracted
[INFO RCX-0045] Extract 30 nets, 60 rsegs, 60 caps, 53 ccs
[INFO RCX-0015] Finished extracting buff_flash_clkrst.
Writing result to /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/results/routing/mca/process_corner_min/buff_flash_clkrst.spef...
Setting global connections for newly added cells...
[WARNING] Did not save OpenROAD database!
Writing extracted parasitics to /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/results/routing/mca/process_corner_min/buff_flash_clkrst.spef...
[INFO RCX-0016] Writing SPEF ...
[INFO RCX-0443] 30 nets finished
[INFO RCX-0017] Finished writing SPEF ...

3152
signoff/buff_flash_clkrst/openlane-signoff/15-rcx_mcsta.min.log Normal file
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40
signoff/buff_flash_clkrst/openlane-signoff/16-parasitics_extraction.max.log Normal file
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OpenROAD 4174c3ad802d2ac1d04d387d2c4b883903f6647e
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO ODB-0222] Reading LEF file: /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/tmp/merged.max.lef
[WARNING ODB-0220] WARNING (LEFPARS-2036): SOURCE statement is obsolete in version 5.6 and later.
The LEF parser will ignore this statement.
To avoid this warning in the future, remove this statement from the LEF file with version 5.6 or later. See file /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/tmp/merged.max.lef at line 930.
[INFO ODB-0223] Created 13 technology layers
[INFO ODB-0224] Created 25 technology vias
[INFO ODB-0225] Created 441 library cells
[INFO ODB-0226] Finished LEF file: /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/tmp/merged.max.lef
[INFO ODB-0127] Reading DEF file: /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/results/routing/buff_flash_clkrst.def
[INFO ODB-0128] Design: buff_flash_clkrst
[INFO ODB-0130] Created 32 pins.
[INFO ODB-0131] Created 73 components and 308 component-terminals.
[INFO ODB-0132] Created 2 special nets and 278 connections.
[INFO ODB-0133] Created 30 nets and 30 connections.
[INFO ODB-0134] Finished DEF file: /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/results/routing/buff_flash_clkrst.def
Using RCX ruleset '/home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.tech/openlane/rules.openrcx.sky130A.max.calibre'...
[INFO RCX-0431] Defined process_corner X with ext_model_index 0
[INFO RCX-0029] Defined extraction corner X
[INFO RCX-0008] extracting parasitics of buff_flash_clkrst ...
[INFO RCX-0435] Reading extraction model file /home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.tech/openlane/rules.openrcx.sky130A.max.calibre ...
[INFO RCX-0436] RC segment generation buff_flash_clkrst (max_merge_res 50.0) ...
[INFO RCX-0040] Final 46 rc segments
[INFO RCX-0439] Coupling Cap extraction buff_flash_clkrst ...
[INFO RCX-0440] Coupling threshhold is 0.1000 fF, coupling capacitance less than 0.1000 fF will be grounded.
[INFO RCX-0043] 156 wires to be extracted
[INFO RCX-0442] 66% completion -- 103 wires have been extracted
[INFO RCX-0442] 100% completion -- 156 wires have been extracted
[INFO RCX-0045] Extract 30 nets, 76 rsegs, 76 caps, 53 ccs
[INFO RCX-0015] Finished extracting buff_flash_clkrst.
Writing result to /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/results/routing/mca/process_corner_max/buff_flash_clkrst.spef...
Setting global connections for newly added cells...
[WARNING] Did not save OpenROAD database!
Writing extracted parasitics to /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/results/routing/mca/process_corner_max/buff_flash_clkrst.spef...
[INFO RCX-0016] Writing SPEF ...
[INFO RCX-0443] 30 nets finished
[INFO RCX-0017] Finished writing SPEF ...

3152
signoff/buff_flash_clkrst/openlane-signoff/17-rcx_mcsta.max.log Normal file
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40
signoff/buff_flash_clkrst/openlane-signoff/18-parasitics_extraction.nom.log Normal file
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OpenROAD 4174c3ad802d2ac1d04d387d2c4b883903f6647e
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO ODB-0222] Reading LEF file: /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/tmp/merged.nom.lef
[WARNING ODB-0220] WARNING (LEFPARS-2036): SOURCE statement is obsolete in version 5.6 and later.
The LEF parser will ignore this statement.
To avoid this warning in the future, remove this statement from the LEF file with version 5.6 or later. See file /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/tmp/merged.nom.lef at line 930.
[INFO ODB-0223] Created 13 technology layers
[INFO ODB-0224] Created 25 technology vias
[INFO ODB-0225] Created 441 library cells
[INFO ODB-0226] Finished LEF file: /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/tmp/merged.nom.lef
[INFO ODB-0127] Reading DEF file: /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/results/routing/buff_flash_clkrst.def
[INFO ODB-0128] Design: buff_flash_clkrst
[INFO ODB-0130] Created 32 pins.
[INFO ODB-0131] Created 73 components and 308 component-terminals.
[INFO ODB-0132] Created 2 special nets and 278 connections.
[INFO ODB-0133] Created 30 nets and 30 connections.
[INFO ODB-0134] Finished DEF file: /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/results/routing/buff_flash_clkrst.def
Using RCX ruleset '/home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.tech/openlane/rules.openrcx.sky130A.nom.calibre'...
[INFO RCX-0431] Defined process_corner X with ext_model_index 0
[INFO RCX-0029] Defined extraction corner X
[INFO RCX-0008] extracting parasitics of buff_flash_clkrst ...
[INFO RCX-0435] Reading extraction model file /home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.tech/openlane/rules.openrcx.sky130A.nom.calibre ...
[INFO RCX-0436] RC segment generation buff_flash_clkrst (max_merge_res 50.0) ...
[INFO RCX-0040] Final 30 rc segments
[INFO RCX-0439] Coupling Cap extraction buff_flash_clkrst ...
[INFO RCX-0440] Coupling threshhold is 0.1000 fF, coupling capacitance less than 0.1000 fF will be grounded.
[INFO RCX-0043] 156 wires to be extracted
[INFO RCX-0442] 66% completion -- 103 wires have been extracted
[INFO RCX-0442] 100% completion -- 156 wires have been extracted
[INFO RCX-0045] Extract 30 nets, 60 rsegs, 60 caps, 53 ccs
[INFO RCX-0015] Finished extracting buff_flash_clkrst.
Writing result to /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/results/routing/mca/process_corner_nom/buff_flash_clkrst.spef...
Setting global connections for newly added cells...
[WARNING] Did not save OpenROAD database!
Writing extracted parasitics to /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/results/routing/mca/process_corner_nom/buff_flash_clkrst.spef...
[INFO RCX-0016] Writing SPEF ...
[INFO RCX-0443] 30 nets finished
[INFO RCX-0017] Finished writing SPEF ...

3152
signoff/buff_flash_clkrst/openlane-signoff/19-rcx_mcsta.nom.log Normal file
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433
signoff/buff_flash_clkrst/openlane-signoff/20-rcx_sta.log Normal file
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@ -0,0 +1,433 @@
OpenROAD 4174c3ad802d2ac1d04d387d2c4b883903f6647e
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[WARNING STA-0357] virtual clock __VIRTUAL_CLK__ can not be propagated.
min_report
===========================================================================
report_checks -path_delay min (Hold)
============================================================================
Startpoint: in_n[3] (input port clocked by __VIRTUAL_CLK__)
Endpoint: out_s[3] (output port clocked by __VIRTUAL_CLK__)
Path Group: __VIRTUAL_CLK__
Path Type: min
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 0.00 clock __VIRTUAL_CLK__ (rise edge)
0.00 0.00 clock network delay (ideal)
1.60 1.60 v input external delay
0.01 0.01 1.61 v in_n[3] (in)
1 0.00 in_n[3] (net)
0.01 0.00 1.61 v BUF[6]/A (sky130_fd_sc_hd__clkbuf_8)
0.05 0.14 1.74 v BUF[6]/X (sky130_fd_sc_hd__clkbuf_8)
1 0.03 out_s[3] (net)
0.05 0.00 1.74 v out_s[3] (out)
1.74 data arrival time
0.00 0.00 0.00 clock __VIRTUAL_CLK__ (rise edge)
0.00 0.00 clock network delay (ideal)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-1.60 -1.35 output external delay
-1.35 data required time
-----------------------------------------------------------------------------
-1.35 data required time
-1.74 data arrival time
-----------------------------------------------------------------------------
3.09 slack (MET)
Startpoint: in_n[10] (input port clocked by __VIRTUAL_CLK__)
Endpoint: out_s[10] (output port clocked by __VIRTUAL_CLK__)
Path Group: __VIRTUAL_CLK__
Path Type: min
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 0.00 clock __VIRTUAL_CLK__ (rise edge)
0.00 0.00 clock network delay (ideal)
1.60 1.60 v input external delay
0.01 0.01 1.61 v in_n[10] (in)
1 0.00 in_n[10] (net)
0.01 0.00 1.61 v BUF[13]/A (sky130_fd_sc_hd__clkbuf_8)
0.05 0.14 1.74 v BUF[13]/X (sky130_fd_sc_hd__clkbuf_8)
1 0.03 out_s[10] (net)
0.05 0.00 1.75 v out_s[10] (out)
1.75 data arrival time
0.00 0.00 0.00 clock __VIRTUAL_CLK__ (rise edge)
0.00 0.00 clock network delay (ideal)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-1.60 -1.35 output external delay
-1.35 data required time
-----------------------------------------------------------------------------
-1.35 data required time
-1.75 data arrival time
-----------------------------------------------------------------------------
3.10 slack (MET)
Startpoint: in_n[0] (input port clocked by __VIRTUAL_CLK__)
Endpoint: out_s[0] (output port clocked by __VIRTUAL_CLK__)
Path Group: __VIRTUAL_CLK__
Path Type: min
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 0.00 clock __VIRTUAL_CLK__ (rise edge)
0.00 0.00 clock network delay (ideal)
1.60 1.60 v input external delay
0.01 0.01 1.61 v in_n[0] (in)
1 0.00 in_n[0] (net)
0.01 0.00 1.61 v BUF[3]/A (sky130_fd_sc_hd__clkbuf_8)
0.05 0.14 1.74 v BUF[3]/X (sky130_fd_sc_hd__clkbuf_8)
1 0.03 out_s[0] (net)
0.05 0.00 1.75 v out_s[0] (out)
1.75 data arrival time
0.00 0.00 0.00 clock __VIRTUAL_CLK__ (rise edge)
0.00 0.00 clock network delay (ideal)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-1.60 -1.35 output external delay
-1.35 data required time
-----------------------------------------------------------------------------
-1.35 data required time
-1.75 data arrival time
-----------------------------------------------------------------------------
3.10 slack (MET)
Startpoint: in_s[2] (input port clocked by __VIRTUAL_CLK__)
Endpoint: out_n[2] (output port clocked by __VIRTUAL_CLK__)
Path Group: __VIRTUAL_CLK__
Path Type: min
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 0.00 clock __VIRTUAL_CLK__ (rise edge)
0.00 0.00 clock network delay (ideal)
1.60 1.60 v input external delay
0.01 0.01 1.61 v in_s[2] (in)
1 0.00 in_s[2] (net)
0.01 0.00 1.61 v BUF[2]/A (sky130_fd_sc_hd__clkbuf_8)
0.05 0.14 1.74 v BUF[2]/X (sky130_fd_sc_hd__clkbuf_8)
1 0.03 out_n[2] (net)
0.05 0.00 1.75 v out_n[2] (out)
1.75 data arrival time
0.00 0.00 0.00 clock __VIRTUAL_CLK__ (rise edge)
0.00 0.00 clock network delay (ideal)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-1.60 -1.35 output external delay
-1.35 data required time
-----------------------------------------------------------------------------
-1.35 data required time
-1.75 data arrival time
-----------------------------------------------------------------------------
3.10 slack (MET)
Startpoint: in_n[8] (input port clocked by __VIRTUAL_CLK__)
Endpoint: out_s[8] (output port clocked by __VIRTUAL_CLK__)
Path Group: __VIRTUAL_CLK__
Path Type: min
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 0.00 clock __VIRTUAL_CLK__ (rise edge)
0.00 0.00 clock network delay (ideal)
1.60 1.60 v input external delay
0.01 0.01 1.61 v in_n[8] (in)
1 0.00 in_n[8] (net)
0.01 0.00 1.61 v BUF[11]/A (sky130_fd_sc_hd__clkbuf_8)
0.05 0.14 1.74 v BUF[11]/X (sky130_fd_sc_hd__clkbuf_8)
1 0.03 out_s[8] (net)
0.05 0.00 1.75 v out_s[8] (out)
1.75 data arrival time
0.00 0.00 0.00 clock __VIRTUAL_CLK__ (rise edge)
0.00 0.00 clock network delay (ideal)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-1.60 -1.35 output external delay
-1.35 data required time
-----------------------------------------------------------------------------
-1.35 data required time
-1.75 data arrival time
-----------------------------------------------------------------------------
3.10 slack (MET)
min_report_end
max_report
===========================================================================
report_checks -path_delay max (Setup)
============================================================================
Startpoint: in_n[11] (input port clocked by __VIRTUAL_CLK__)
Endpoint: out_s[11] (output port clocked by __VIRTUAL_CLK__)
Path Group: __VIRTUAL_CLK__
Path Type: max
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 0.00 clock __VIRTUAL_CLK__ (rise edge)
0.00 0.00 clock network delay (ideal)
1.60 1.60 ^ input external delay
0.04 0.03 1.63 ^ in_n[11] (in)
1 0.01 in_n[11] (net)
0.04 0.00 1.63 ^ BUF[14]/A (sky130_fd_sc_hd__clkbuf_8)
0.08 0.16 1.78 ^ BUF[14]/X (sky130_fd_sc_hd__clkbuf_8)
1 0.03 out_s[11] (net)
0.08 0.00 1.78 ^ out_s[11] (out)
1.78 data arrival time
0.00 8.00 8.00 clock __VIRTUAL_CLK__ (rise edge)
0.00 8.00 clock network delay (ideal)
-0.25 7.75 clock uncertainty
0.00 7.75 clock reconvergence pessimism
-1.60 6.15 output external delay
6.15 data required time
-----------------------------------------------------------------------------
6.15 data required time
-1.78 data arrival time
-----------------------------------------------------------------------------
4.37 slack (MET)
Startpoint: in_n[2] (input port clocked by __VIRTUAL_CLK__)
Endpoint: out_s[2] (output port clocked by __VIRTUAL_CLK__)
Path Group: __VIRTUAL_CLK__
Path Type: max
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 0.00 clock __VIRTUAL_CLK__ (rise edge)
0.00 0.00 clock network delay (ideal)
1.60 1.60 ^ input external delay
0.03 0.02 1.62 ^ in_n[2] (in)
1 0.01 in_n[2] (net)
0.03 0.00 1.62 ^ BUF[5]/A (sky130_fd_sc_hd__clkbuf_8)
0.07 0.15 1.78 ^ BUF[5]/X (sky130_fd_sc_hd__clkbuf_8)
1 0.03 out_s[2] (net)
0.07 0.00 1.78 ^ out_s[2] (out)
1.78 data arrival time
0.00 8.00 8.00 clock __VIRTUAL_CLK__ (rise edge)
0.00 8.00 clock network delay (ideal)
-0.25 7.75 clock uncertainty
0.00 7.75 clock reconvergence pessimism
-1.60 6.15 output external delay
6.15 data required time
-----------------------------------------------------------------------------
6.15 data required time
-1.78 data arrival time
-----------------------------------------------------------------------------
4.37 slack (MET)
Startpoint: in_n[6] (input port clocked by __VIRTUAL_CLK__)
Endpoint: out_s[6] (output port clocked by __VIRTUAL_CLK__)
Path Group: __VIRTUAL_CLK__
Path Type: max
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 0.00 clock __VIRTUAL_CLK__ (rise edge)
0.00 0.00 clock network delay (ideal)
1.60 1.60 ^ input external delay
0.03 0.02 1.62 ^ in_n[6] (in)
1 0.01 in_n[6] (net)
0.03 0.00 1.62 ^ BUF[9]/A (sky130_fd_sc_hd__clkbuf_8)
0.07 0.15 1.78 ^ BUF[9]/X (sky130_fd_sc_hd__clkbuf_8)
1 0.03 out_s[6] (net)
0.07 0.00 1.78 ^ out_s[6] (out)
1.78 data arrival time
0.00 8.00 8.00 clock __VIRTUAL_CLK__ (rise edge)
0.00 8.00 clock network delay (ideal)
-0.25 7.75 clock uncertainty
0.00 7.75 clock reconvergence pessimism
-1.60 6.15 output external delay
6.15 data required time
-----------------------------------------------------------------------------
6.15 data required time
-1.78 data arrival time
-----------------------------------------------------------------------------
4.37 slack (MET)
Startpoint: in_n[7] (input port clocked by __VIRTUAL_CLK__)
Endpoint: out_s[7] (output port clocked by __VIRTUAL_CLK__)
Path Group: __VIRTUAL_CLK__
Path Type: max
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 0.00 clock __VIRTUAL_CLK__ (rise edge)
0.00 0.00 clock network delay (ideal)
1.60 1.60 ^ input external delay
0.03 0.02 1.62 ^ in_n[7] (in)
1 0.01 in_n[7] (net)
0.03 0.00 1.62 ^ BUF[10]/A (sky130_fd_sc_hd__clkbuf_8)
0.07 0.15 1.78 ^ BUF[10]/X (sky130_fd_sc_hd__clkbuf_8)
1 0.03 out_s[7] (net)
0.07 0.00 1.78 ^ out_s[7] (out)
1.78 data arrival time
0.00 8.00 8.00 clock __VIRTUAL_CLK__ (rise edge)
0.00 8.00 clock network delay (ideal)
-0.25 7.75 clock uncertainty
0.00 7.75 clock reconvergence pessimism
-1.60 6.15 output external delay
6.15 data required time
-----------------------------------------------------------------------------
6.15 data required time
-1.78 data arrival time
-----------------------------------------------------------------------------
4.37 slack (MET)
Startpoint: in_s[1] (input port clocked by __VIRTUAL_CLK__)
Endpoint: out_n[1] (output port clocked by __VIRTUAL_CLK__)
Path Group: __VIRTUAL_CLK__
Path Type: max
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 0.00 clock __VIRTUAL_CLK__ (rise edge)
0.00 0.00 clock network delay (ideal)
1.60 1.60 ^ input external delay
0.03 0.02 1.62 ^ in_s[1] (in)
1 0.01 in_s[1] (net)
0.03 0.00 1.62 ^ BUF[1]/A (sky130_fd_sc_hd__clkbuf_8)
0.07 0.15 1.78 ^ BUF[1]/X (sky130_fd_sc_hd__clkbuf_8)
1 0.03 out_n[1] (net)
0.07 0.00 1.78 ^ out_n[1] (out)
1.78 data arrival time
0.00 8.00 8.00 clock __VIRTUAL_CLK__ (rise edge)
0.00 8.00 clock network delay (ideal)
-0.25 7.75 clock uncertainty
0.00 7.75 clock reconvergence pessimism
-1.60 6.15 output external delay
6.15 data required time
-----------------------------------------------------------------------------
6.15 data required time
-1.78 data arrival time
-----------------------------------------------------------------------------
4.37 slack (MET)
max_report_end
check_report
===========================================================================
report_checks -unconstrained
============================================================================
Startpoint: in_n[11] (input port clocked by __VIRTUAL_CLK__)
Endpoint: out_s[11] (output port clocked by __VIRTUAL_CLK__)
Path Group: __VIRTUAL_CLK__
Path Type: max
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 0.00 clock __VIRTUAL_CLK__ (rise edge)
0.00 0.00 clock network delay (ideal)
1.60 1.60 ^ input external delay
0.04 0.03 1.63 ^ in_n[11] (in)
1 0.01 in_n[11] (net)
0.04 0.00 1.63 ^ BUF[14]/A (sky130_fd_sc_hd__clkbuf_8)
0.08 0.16 1.78 ^ BUF[14]/X (sky130_fd_sc_hd__clkbuf_8)
1 0.03 out_s[11] (net)
0.08 0.00 1.78 ^ out_s[11] (out)
1.78 data arrival time
0.00 8.00 8.00 clock __VIRTUAL_CLK__ (rise edge)
0.00 8.00 clock network delay (ideal)
-0.25 7.75 clock uncertainty
0.00 7.75 clock reconvergence pessimism
-1.60 6.15 output external delay
6.15 data required time
-----------------------------------------------------------------------------
6.15 data required time
-1.78 data arrival time
-----------------------------------------------------------------------------
4.37 slack (MET)
===========================================================================
report_checks --slack_max -0.01
============================================================================
No paths found.
check_report_end
check_slew
===========================================================================
report_check_types -max_slew -max_cap -max_fanout -violators
============================================================================
===========================================================================
max slew violation count 0
max fanout violation count 0
max cap violation count 0
============================================================================
check_slew_end
tns_report
===========================================================================
report_tns
============================================================================
tns 0.00
tns_report_end
wns_report
===========================================================================
report_wns
============================================================================
wns 0.00
wns_report_end
worst_slack
===========================================================================
report_worst_slack -max (Setup)
============================================================================
worst slack 4.37
===========================================================================
report_worst_slack -min (Hold)
============================================================================
worst slack 3.09
worst_slack_end
power_report
===========================================================================
report_power
============================================================================
Group Internal Switching Leakage Total
Power Power Power Power (Watts)
----------------------------------------------------------------
Sequential 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
Combinational 8.50e-06 1.01e-05 1.92e-10 1.86e-05 100.0%
Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
----------------------------------------------------------------
Total 8.50e-06 1.01e-05 1.92e-10 1.86e-05 100.0%
45.6% 54.4% 0.0%
power_report_end
area_report
===========================================================================
report_design_area
============================================================================
Design area 215 u^2 44% utilization.
area_report_end
Setting global connections for newly added cells...
[WARNING] Did not save OpenROAD database!
Writing SDF to /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/results/routing/mca/process_corner_nom/buff_flash_clkrst.sdf...
Writing timing model to /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/results/routing/mca/process_corner_nom/buff_flash_clkrst.lib...

37
signoff/buff_flash_clkrst/openlane-signoff/21-irdrop.log Normal file
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@ -0,0 +1,37 @@
OpenROAD 4174c3ad802d2ac1d04d387d2c4b883903f6647e
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO ODB-0222] Reading LEF file: /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/tmp/merged.nom.lef
[WARNING ODB-0220] WARNING (LEFPARS-2036): SOURCE statement is obsolete in version 5.6 and later.
The LEF parser will ignore this statement.
To avoid this warning in the future, remove this statement from the LEF file with version 5.6 or later. See file /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/tmp/merged.nom.lef at line 930.
[INFO ODB-0223] Created 13 technology layers
[INFO ODB-0224] Created 25 technology vias
[INFO ODB-0225] Created 441 library cells
[INFO ODB-0226] Finished LEF file: /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/tmp/merged.nom.lef
[INFO ODB-0127] Reading DEF file: /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/results/routing/buff_flash_clkrst.def
[INFO ODB-0128] Design: buff_flash_clkrst
[INFO ODB-0130] Created 32 pins.
[INFO ODB-0131] Created 73 components and 308 component-terminals.
[INFO ODB-0132] Created 2 special nets and 278 connections.
[INFO ODB-0133] Created 30 nets and 30 connections.
[INFO ODB-0134] Finished DEF file: /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/results/routing/buff_flash_clkrst.def
[INFO]: Setting RC values...
[INFO PSM-0002] Output voltage file is specified as: /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/reports/signoff/21-irdrop.rpt.
[WARNING PSM-0016] Voltage pad location (VSRC) file not specified, defaulting pad location to checkerboard pattern on core area.
[WARNING PSM-0017] X direction bump pitch is not specified, defaulting to 140um.
[WARNING PSM-0018] Y direction bump pitch is not specified, defaulting to 140um.
[WARNING PSM-0019] Voltage on net VPWR is not explicitly set.
[WARNING PSM-0022] Using voltage 1.800V for VDD network.
[WARNING PSM-0063] Specified bump pitches of 140.000 and 140.000 are less than core width of 35.880 or core height of 13.600. Changing bump location to the center of the die at (19.780, 12.240).
[WARNING PSM-0065] VSRC location not specified, using default checkerboard pattern with one VDD every size bumps in x-direction and one in two bumps in the y-direction
[INFO PSM-0076] Setting metal node density to be standard cell height times 5.
[INFO PSM-0031] Number of PDN nodes on net VPWR = 110.
[INFO PSM-0064] Number of voltage sources = 1.
[INFO PSM-0040] All PDN stripes on net VPWR are connected.
########## IR report #################
Worstcase voltage: 1.80e+00 V
Average IR drop : 2.19e-10 V
Worstcase IR drop: 3.61e-10 V
######################################

27
signoff/buff_flash_clkrst/openlane-signoff/22-gds_ptrs.log Normal file
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@ -0,0 +1,27 @@
Magic 8.3 revision 324 - Compiled on Thu Sep 15 11:38:02 UTC 2022.
Starting magic under Tcl interpreter
Using the terminal as the console.
Using NULL graphics device.
Processing system .magicrc file
Sourcing design .magicrc for technology sky130A ...
2 Magic internal units = 1 Lambda
Input style sky130(vendor): scaleFactor=2, multiplier=2
The following types are not handled by extraction and will be treated as non-electrical types:
ubm
Scaled tech values by 2 / 1 to match internal grid scaling
Loading sky130A Device Generator Menu ...
Using technology "sky130A", version 1.0.341-2-gde752ec
Warning: Calma reading is not undoable! I hope that's OK.
Library written using GDS-II Release 3.0
Library name: buff_flash_clkrst
Reading "sky130_fd_sc_hd__clkbuf_8".
Reading "sky130_fd_sc_hd__decap_4".
Reading "sky130_fd_sc_hd__fill_1".
Reading "sky130_fd_sc_hd__decap_3".
Reading "sky130_fd_sc_hd__decap_8".
Reading "sky130_ef_sc_hd__decap_12".
Reading "sky130_fd_sc_hd__tapvpwrvgnd_1".
Reading "sky130_fd_sc_hd__fill_2".
Reading "buff_flash_clkrst".
[INFO]: Wrote /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/tmp/signoff/gds_ptrs.mag including GDS pointers.

67
signoff/buff_flash_clkrst/openlane-signoff/22-gdsii.log Normal file
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@ -0,0 +1,67 @@
Magic 8.3 revision 324 - Compiled on Thu Sep 15 11:38:02 UTC 2022.
Starting magic under Tcl interpreter
Using the terminal as the console.
Using NULL graphics device.
Processing system .magicrc file
Sourcing design .magicrc for technology sky130A ...
2 Magic internal units = 1 Lambda
Input style sky130(vendor): scaleFactor=2, multiplier=2
The following types are not handled by extraction and will be treated as non-electrical types:
ubm
Scaled tech values by 2 / 1 to match internal grid scaling
Loading sky130A Device Generator Menu ...
Using technology "sky130A", version 1.0.341-2-gde752ec
Reading LEF data from file /home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd__nom.tlef.
This action cannot be undone.
LEF read, Line 78 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
LEF read, Line 79 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read, Line 112 (Message): Unknown keyword "MINENCLOSEDAREA" in LEF file; ignoring.
LEF read, Line 114 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
LEF read, Line 115 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read, Line 121 (Message): Unknown keyword "MAXIMUMDENSITY" in LEF file; ignoring.
LEF read, Line 122 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
LEF read, Line 123 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
LEF read, Line 156 (Message): Unknown keyword "MINENCLOSEDAREA" in LEF file; ignoring.
LEF read, Line 164 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
LEF read, Line 165 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read, Line 167 (Message): Unknown keyword "MAXIMUMDENSITY" in LEF file; ignoring.
LEF read, Line 168 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
LEF read, Line 169 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
LEF read, Line 206 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
LEF read, Line 207 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read, Line 209 (Message): Unknown keyword "MAXIMUMDENSITY" in LEF file; ignoring.
LEF read, Line 210 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
LEF read, Line 211 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
LEF read, Line 248 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
LEF read, Line 249 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read, Line 251 (Message): Unknown keyword "MAXIMUMDENSITY" in LEF file; ignoring.
LEF read, Line 252 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
LEF read, Line 253 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
LEF read, Line 290 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
LEF read, Line 291 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read: Processed 797 lines.
Reading DEF data from file /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/results/routing/buff_flash_clkrst.def.
This action cannot be undone.
Processed 3 vias total.
Processed 73 subcell instances total.
Processed 32 pins total.
Processed 2 special nets total.
Processed 30 nets total.
DEF read: Processed 571 lines.
Root cell box:
width x height ( llx, lly ), ( urx, ury ) area (units^2)
microns: 40.000 x 25.000 ( 0.000, 0.000), ( 40.000, 25.000) 1000.000
lambda: 4000.00 x 2500.00 ( 0.00, 0.00 ), ( 4000.00, 2500.00) 10000000.00
internal: 8000 x 5000 ( 0, 0 ), ( 8000, 5000 ) 40000000
Generating output for cell sky130_fd_sc_hd__clkbuf_8
Generating output for cell sky130_fd_sc_hd__decap_4
Generating output for cell sky130_fd_sc_hd__fill_1
Generating output for cell sky130_fd_sc_hd__decap_3
Generating output for cell sky130_fd_sc_hd__decap_8
Generating output for cell sky130_ef_sc_hd__decap_12
Generating output for cell sky130_fd_sc_hd__tapvpwrvgnd_1
Generating output for cell sky130_fd_sc_hd__fill_2
Generating output for cell buff_flash_clkrst
[INFO]: GDS Write Complete

73
signoff/buff_flash_clkrst/openlane-signoff/22-lef.log Normal file
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@ -0,0 +1,73 @@
Magic 8.3 revision 324 - Compiled on Thu Sep 15 11:38:02 UTC 2022.
Starting magic under Tcl interpreter
Using the terminal as the console.
Using NULL graphics device.
Processing system .magicrc file
Sourcing design .magicrc for technology sky130A ...
2 Magic internal units = 1 Lambda
Input style sky130(vendor): scaleFactor=2, multiplier=2
The following types are not handled by extraction and will be treated as non-electrical types:
ubm
Scaled tech values by 2 / 1 to match internal grid scaling
Loading sky130A Device Generator Menu ...
Using technology "sky130A", version 1.0.341-2-gde752ec
Reading LEF data from file /home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd__nom.tlef.
This action cannot be undone.
LEF read, Line 78 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
LEF read, Line 79 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read, Line 112 (Message): Unknown keyword "MINENCLOSEDAREA" in LEF file; ignoring.
LEF read, Line 114 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
LEF read, Line 115 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read, Line 121 (Message): Unknown keyword "MAXIMUMDENSITY" in LEF file; ignoring.
LEF read, Line 122 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
LEF read, Line 123 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
LEF read, Line 156 (Message): Unknown keyword "MINENCLOSEDAREA" in LEF file; ignoring.
LEF read, Line 164 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
LEF read, Line 165 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read, Line 167 (Message): Unknown keyword "MAXIMUMDENSITY" in LEF file; ignoring.
LEF read, Line 168 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
LEF read, Line 169 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
LEF read, Line 206 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
LEF read, Line 207 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read, Line 209 (Message): Unknown keyword "MAXIMUMDENSITY" in LEF file; ignoring.
LEF read, Line 210 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
LEF read, Line 211 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
LEF read, Line 248 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
LEF read, Line 249 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read, Line 251 (Message): Unknown keyword "MAXIMUMDENSITY" in LEF file; ignoring.
LEF read, Line 252 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
LEF read, Line 253 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
LEF read, Line 290 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
LEF read, Line 291 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read: Processed 797 lines.
[INFO]: Writing abstract LEF
Generating LEF output /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/results/signoff/buff_flash_clkrst.lef for cell buff_flash_clkrst:
Diagnostic: Write LEF header for cell buff_flash_clkrst
Diagnostic: Writing LEF output for cell buff_flash_clkrst
Warning: Parent cell lists instance of "sky130_fd_sc_hd__clkbuf_8" at bad file path /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/results/signoff/sky130_fd_sc_hd__clkbuf_8.mag.
The cell exists in the search paths at /home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__clkbuf_8.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__decap_4" at bad file path /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/results/signoff/sky130_fd_sc_hd__decap_4.mag.
The cell exists in the search paths at /home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__decap_4.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__fill_1" at bad file path /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/results/signoff/sky130_fd_sc_hd__fill_1.mag.
The cell exists in the search paths at /home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__fill_1.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__decap_3" at bad file path /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/results/signoff/sky130_fd_sc_hd__decap_3.mag.
The cell exists in the search paths at /home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__decap_3.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__decap_8" at bad file path /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/results/signoff/sky130_fd_sc_hd__decap_8.mag.
The cell exists in the search paths at /home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__decap_8.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_ef_sc_hd__decap_12" at bad file path /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/results/signoff/sky130_ef_sc_hd__decap_12.mag.
The cell exists in the search paths at /home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_ef_sc_hd__decap_12.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__tapvpwrvgnd_1" at bad file path /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/results/signoff/sky130_fd_sc_hd__tapvpwrvgnd_1.mag.
The cell exists in the search paths at /home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__tapvpwrvgnd_1.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__fill_2" at bad file path /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/results/signoff/sky130_fd_sc_hd__fill_2.mag.
The cell exists in the search paths at /home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__fill_2.mag.
The discovered version will be used.
Diagnostic: Scale value is 0.005000
[INFO]: LEF Write Complete

18
signoff/buff_flash_clkrst/openlane-signoff/22-maglef.log Normal file
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@ -0,0 +1,18 @@
Magic 8.3 revision 324 - Compiled on Thu Sep 15 11:38:02 UTC 2022.
Starting magic under Tcl interpreter
Using the terminal as the console.
Using NULL graphics device.
Processing system .magicrc file
Sourcing design .magicrc for technology sky130A ...
2 Magic internal units = 1 Lambda
Input style sky130(vendor): scaleFactor=2, multiplier=2
The following types are not handled by extraction and will be treated as non-electrical types:
ubm
Scaled tech values by 2 / 1 to match internal grid scaling
Loading sky130A Device Generator Menu ...
Using technology "sky130A", version 1.0.341-2-gde752ec
Reading LEF data from file /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/results/signoff/buff_flash_clkrst.lef.
This action cannot be undone.
LEF read: Processed 335 lines.
[INFO]: DONE GENERATING MAGLEF VIEW

17
signoff/buff_flash_clkrst/openlane-signoff/23-gdsii-klayout.log Normal file
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@ -0,0 +1,17 @@
Input: /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/results/routing/buff_flash_clkrst.def
Output: /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/results/signoff/buff_flash_clkrst.klayout.gds
Design: buff_flash_clkrst
Technology File: /home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.tech/klayout/tech/sky130A.lyt
GDS File List: ['/home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds']
LEF File: /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/tmp/merged.nom.lef
[INFO] Clearing cells...
[INFO] Merging GDS files...
/home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds
[INFO] Copying toplevel cell 'buff_flash_clkrst'
WARNING: no fill config file specified
[INFO] Checking for missing GDS...
[INFO] All LEF cells have matching GDS cells
[INFO] Writing out GDS '/home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/results/signoff/buff_flash_clkrst.klayout.gds'
[INFO] Done.

652
signoff/buff_flash_clkrst/openlane-signoff/24-xor.log Normal file
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@ -0,0 +1,652 @@
First Layout: /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/results/signoff/buff_flash_clkrst.gds
Second Layout: /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/results/signoff/buff_flash_clkrst.klayout.gds
Design Name: buff_flash_clkrst
Output GDS will be: /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/reports/signoff/buff_flash_clkrst.xor.xml
Reading /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/results/signoff/buff_flash_clkrst.gds ..
Reading /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/results/signoff/buff_flash_clkrst.klayout.gds ..
--- Running XOR for 10/0 ---
"input" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
"input" in: xor.drc:38
Polygons (raw): 96 (flat) 4 (hierarchical)
Elapsed: 0.010s Memory: 345.00M
"^" in: xor.drc:38
Polygons (raw): 96 (flat) 4 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
XOR differences: 96
"output" in: xor.drc:40
Polygons (raw): 96 (flat) 4 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
--- Running XOR for 11/0 ---
"input" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
"input" in: xor.drc:38
Polygons (raw): 32 (flat) 9 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
"^" in: xor.drc:38
Polygons (raw): 32 (flat) 9 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
XOR differences: 32
"output" in: xor.drc:40
Polygons (raw): 32 (flat) 9 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
--- Running XOR for 11/1 ---
"input" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
"input" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
"^" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.010s Memory: 345.00M
XOR differences: 0
"output" in: xor.drc:40
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
--- Running XOR for 11/2 ---
"input" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
"input" in: xor.drc:38
Polygons (raw): 8 (flat) 8 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
"^" in: xor.drc:38
Polygons (raw): 8 (flat) 8 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
XOR differences: 8
"output" in: xor.drc:40
Polygons (raw): 8 (flat) 8 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
--- Running XOR for 122/16 ---
"input" in: xor.drc:38
Polygons (raw): 66 (flat) 7 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
"input" in: xor.drc:38
Polygons (raw): 66 (flat) 7 (hierarchical)
Elapsed: 0.010s Memory: 345.00M
"^" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
XOR differences: 0
"output" in: xor.drc:40
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
--- Running XOR for 14/0 ---
"input" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
"input" in: xor.drc:38
Polygons (raw): 1 (flat) 1 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
"^" in: xor.drc:38
Polygons (raw): 1 (flat) 1 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
XOR differences: 1
"output" in: xor.drc:40
Polygons (raw): 1 (flat) 1 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
--- Running XOR for 235/4 ---
"input" in: xor.drc:38
Polygons (raw): 1 (flat) 1 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
"input" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
"^" in: xor.drc:38
Polygons (raw): 1 (flat) 1 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
XOR differences: 1
"output" in: xor.drc:40
Polygons (raw): 1 (flat) 1 (hierarchical)
Elapsed: 0.010s Memory: 345.00M
--- Running XOR for 236/0 ---
"input" in: xor.drc:38
Polygons (raw): 48 (flat) 5 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
"input" in: xor.drc:38
Polygons (raw): 48 (flat) 5 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
"^" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
XOR differences: 0
"output" in: xor.drc:40
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
--- Running XOR for 3/0 ---
"input" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
"input" in: xor.drc:38
Polygons (raw): 30 (flat) 1 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
"^" in: xor.drc:38
Polygons (raw): 30 (flat) 1 (hierarchical)
Elapsed: 0.010s Memory: 345.00M
XOR differences: 30
"output" in: xor.drc:40
Polygons (raw): 30 (flat) 1 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
--- Running XOR for 4/0 ---
"input" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
"input" in: xor.drc:38
Polygons (raw): 30 (flat) 1 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
"^" in: xor.drc:38
Polygons (raw): 30 (flat) 1 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
XOR differences: 30
"output" in: xor.drc:40
Polygons (raw): 30 (flat) 1 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
--- Running XOR for 5/0 ---
"input" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
"input" in: xor.drc:38
Polygons (raw): 126 (flat) 45 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
"^" in: xor.drc:38
Polygons (raw): 126 (flat) 45 (hierarchical)
Elapsed: 0.010s Memory: 345.00M
XOR differences: 126
"output" in: xor.drc:40
Polygons (raw): 126 (flat) 45 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
--- Running XOR for 6/0 ---
"input" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
"input" in: xor.drc:38
Polygons (raw): 150 (flat) 6 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
"^" in: xor.drc:38
Polygons (raw): 150 (flat) 6 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
XOR differences: 150
"output" in: xor.drc:40
Polygons (raw): 150 (flat) 6 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
--- Running XOR for 64/16 ---
"input" in: xor.drc:38
Polygons (raw): 66 (flat) 7 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
"input" in: xor.drc:38
Polygons (raw): 66 (flat) 7 (hierarchical)
Elapsed: 0.010s Memory: 345.00M
"^" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
XOR differences: 0
"output" in: xor.drc:40
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
--- Running XOR for 64/20 ---
"input" in: xor.drc:38
Polygons (raw): 73 (flat) 8 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
"input" in: xor.drc:38
Polygons (raw): 73 (flat) 8 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
"^" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
XOR differences: 0
"output" in: xor.drc:40
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
--- Running XOR for 64/5 ---
"input" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.010s Memory: 345.00M
"input" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
"^" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
XOR differences: 0
"output" in: xor.drc:40
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
--- Running XOR for 64/59 ---
"input" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
"input" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
"^" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
XOR differences: 0
"output" in: xor.drc:40
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.010s Memory: 345.00M
--- Running XOR for 65/20 ---
"input" in: xor.drc:38
Polygons (raw): 96 (flat) 10 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
"input" in: xor.drc:38
Polygons (raw): 96 (flat) 10 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
"^" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
XOR differences: 0
"output" in: xor.drc:40
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
--- Running XOR for 65/44 ---
"input" in: xor.drc:38
Polygons (raw): 14 (flat) 2 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
"input" in: xor.drc:38
Polygons (raw): 14 (flat) 2 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
"^" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.010s Memory: 345.00M
XOR differences: 0
"output" in: xor.drc:40
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
--- Running XOR for 66/20 ---
"input" in: xor.drc:38
Polygons (raw): 96 (flat) 10 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
"input" in: xor.drc:38
Polygons (raw): 96 (flat) 10 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
"^" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
XOR differences: 0
"output" in: xor.drc:40
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
--- Running XOR for 66/44 ---
"input" in: xor.drc:38
Polygons (raw): 827 (flat) 73 (hierarchical)
Elapsed: 0.010s Memory: 345.00M
"input" in: xor.drc:38
Polygons (raw): 827 (flat) 73 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
"^" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
XOR differences: 0
"output" in: xor.drc:40
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
--- Running XOR for 67/16 ---
"input" in: xor.drc:38
Polygons (raw): 120 (flat) 8 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
"input" in: xor.drc:38
Polygons (raw): 120 (flat) 8 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
"^" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
XOR differences: 0
"output" in: xor.drc:40
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
--- Running XOR for 67/20 ---
"input" in: xor.drc:38
Polygons (raw): 293 (flat) 57 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
"input" in: xor.drc:38
Polygons (raw): 263 (flat) 27 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
"^" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.010s Memory: 345.00M
XOR differences: 0
"output" in: xor.drc:40
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
--- Running XOR for 67/44 ---
"input" in: xor.drc:38
Polygons (raw): 810 (flat) 114 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
"input" in: xor.drc:38
Polygons (raw): 780 (flat) 84 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
"^" in: xor.drc:38
Polygons (raw): 30 (flat) 30 (hierarchical)
Elapsed: 0.010s Memory: 345.00M
XOR differences: 30
"output" in: xor.drc:40
Polygons (raw): 30 (flat) 30 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
--- Running XOR for 67/5 ---
"input" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
"input" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
"^" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
XOR differences: 0
"output" in: xor.drc:40
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
--- Running XOR for 68/16 ---
"input" in: xor.drc:38
Polygons (raw): 146 (flat) 16 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
"input" in: xor.drc:38
Polygons (raw): 146 (flat) 16 (hierarchical)
Elapsed: 0.010s Memory: 345.00M
"^" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
XOR differences: 0
"output" in: xor.drc:40
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
--- Running XOR for 68/20 ---
"input" in: xor.drc:38
Polygons (raw): 296 (flat) 166 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
"input" in: xor.drc:38
Polygons (raw): 146 (flat) 16 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
"^" in: xor.drc:38
Polygons (raw): 33 (flat) 33 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
XOR differences: 33
"output" in: xor.drc:40
Polygons (raw): 33 (flat) 33 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
--- Running XOR for 68/44 ---
"input" in: xor.drc:38
Polygons (raw): 150 (flat) 150 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
"input" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
"^" in: xor.drc:38
Polygons (raw): 150 (flat) 150 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
XOR differences: 150
"output" in: xor.drc:40
Polygons (raw): 150 (flat) 150 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
--- Running XOR for 68/5 ---
"input" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
"input" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
"^" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.010s Memory: 345.00M
XOR differences: 0
"output" in: xor.drc:40
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
--- Running XOR for 69/16 ---
"input" in: xor.drc:38
Polygons (raw): 30 (flat) 30 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
"input" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
"^" in: xor.drc:38
Polygons (raw): 30 (flat) 30 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
XOR differences: 30
"output" in: xor.drc:40
Polygons (raw): 30 (flat) 30 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
--- Running XOR for 69/20 ---
"input" in: xor.drc:38
Polygons (raw): 158 (flat) 158 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
"input" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.010s Memory: 345.00M
"^" in: xor.drc:38
Polygons (raw): 158 (flat) 158 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
XOR differences: 158
"output" in: xor.drc:40
Polygons (raw): 158 (flat) 158 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
--- Running XOR for 69/44 ---
"input" in: xor.drc:38
Polygons (raw): 96 (flat) 96 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
"input" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
"^" in: xor.drc:38
Polygons (raw): 96 (flat) 96 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
XOR differences: 96
"output" in: xor.drc:40
Polygons (raw): 96 (flat) 96 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
--- Running XOR for 7/0 ---
"input" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
"input" in: xor.drc:38
Polygons (raw): 165 (flat) 90 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
"^" in: xor.drc:38
Polygons (raw): 165 (flat) 90 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
XOR differences: 165
"output" in: xor.drc:40
Polygons (raw): 165 (flat) 90 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
--- Running XOR for 7/1 ---
"input" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
"input" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
"^" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
XOR differences: 0
"output" in: xor.drc:40
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
--- Running XOR for 7/2 ---
"input" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.010s Memory: 345.00M
"input" in: xor.drc:38
Polygons (raw): 30 (flat) 30 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
"^" in: xor.drc:38
Polygons (raw): 30 (flat) 30 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
XOR differences: 30
"output" in: xor.drc:40
Polygons (raw): 30 (flat) 30 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
--- Running XOR for 70/20 ---
"input" in: xor.drc:38
Polygons (raw): 24 (flat) 24 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
"input" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
"^" in: xor.drc:38
Polygons (raw): 24 (flat) 24 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
XOR differences: 24
"output" in: xor.drc:40
Polygons (raw): 24 (flat) 24 (hierarchical)
Elapsed: 0.010s Memory: 345.00M
--- Running XOR for 70/44 ---
"input" in: xor.drc:38
Polygons (raw): 96 (flat) 96 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
"input" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
"^" in: xor.drc:38
Polygons (raw): 96 (flat) 96 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
XOR differences: 96
"output" in: xor.drc:40
Polygons (raw): 96 (flat) 96 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
--- Running XOR for 71/16 ---
"input" in: xor.drc:38
Polygons (raw): 8 (flat) 8 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
"input" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
"^" in: xor.drc:38
Polygons (raw): 8 (flat) 8 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
XOR differences: 8
"output" in: xor.drc:40
Polygons (raw): 8 (flat) 8 (hierarchical)
Elapsed: 0.010s Memory: 345.00M
--- Running XOR for 71/20 ---
"input" in: xor.drc:38
Polygons (raw): 8 (flat) 8 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
"input" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
"^" in: xor.drc:38
Polygons (raw): 8 (flat) 8 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
XOR differences: 8
"output" in: xor.drc:40
Polygons (raw): 8 (flat) 8 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
--- Running XOR for 78/44 ---
"input" in: xor.drc:38
Polygons (raw): 73 (flat) 8 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
"input" in: xor.drc:38
Polygons (raw): 73 (flat) 8 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
"^" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.010s Memory: 345.00M
XOR differences: 0
"output" in: xor.drc:40
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
--- Running XOR for 8/0 ---
"input" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
"input" in: xor.drc:38
Polygons (raw): 96 (flat) 4 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
"^" in: xor.drc:38
Polygons (raw): 96 (flat) 4 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
XOR differences: 96
"output" in: xor.drc:40
Polygons (raw): 96 (flat) 4 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
--- Running XOR for 81/4 ---
"input" in: xor.drc:38
Polygons (raw): 73 (flat) 8 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
"input" in: xor.drc:38
Polygons (raw): 73 (flat) 8 (hierarchical)
Elapsed: 0.010s Memory: 345.00M
"^" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
XOR differences: 0
"output" in: xor.drc:40
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
--- Running XOR for 83/44 ---
"input" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
"input" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
"^" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
XOR differences: 0
"output" in: xor.drc:40
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
--- Running XOR for 9/0 ---
"input" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.010s Memory: 345.00M
"input" in: xor.drc:38
Polygons (raw): 72 (flat) 26 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
"^" in: xor.drc:38
Polygons (raw): 72 (flat) 26 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
XOR differences: 72
"output" in: xor.drc:40
Polygons (raw): 72 (flat) 26 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
--- Running XOR for 93/44 ---
"input" in: xor.drc:38
Polygons (raw): 80 (flat) 9 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
"input" in: xor.drc:38
Polygons (raw): 80 (flat) 9 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
"^" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
XOR differences: 0
"output" in: xor.drc:40
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.010s Memory: 345.00M
--- Running XOR for 94/20 ---
"input" in: xor.drc:38
Polygons (raw): 80 (flat) 9 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
"input" in: xor.drc:38
Polygons (raw): 80 (flat) 9 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
"^" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
XOR differences: 0
"output" in: xor.drc:40
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
--- Running XOR for 95/20 ---
"input" in: xor.drc:38
Polygons (raw): 48 (flat) 5 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
"input" in: xor.drc:38
Polygons (raw): 48 (flat) 5 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
"^" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
XOR differences: 0
"output" in: xor.drc:40
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 345.00M
Writing report database: /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/reports/signoff/buff_flash_clkrst.xor.xml ..
Total elapsed: 0.290s Memory: 345.00M

50
signoff/buff_flash_clkrst/openlane-signoff/25-gds.spice.log Normal file
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Magic 8.3 revision 324 - Compiled on Thu Sep 15 11:38:02 UTC 2022.
Starting magic under Tcl interpreter
Using the terminal as the console.
Using NULL graphics device.
Processing system .magicrc file
Sourcing design .magicrc for technology sky130A ...
2 Magic internal units = 1 Lambda
Input style sky130(vendor): scaleFactor=2, multiplier=2
The following types are not handled by extraction and will be treated as non-electrical types:
ubm
Scaled tech values by 2 / 1 to match internal grid scaling
Loading sky130A Device Generator Menu ...
Using technology "sky130A", version 1.0.341-2-gde752ec
Warning: Calma reading is not undoable! I hope that's OK.
Library written using GDS-II Release 3.0
Library name: buff_flash_clkrst
Reading "sky130_fd_sc_hd__clkbuf_8".
Reading "sky130_fd_sc_hd__decap_4".
Reading "sky130_fd_sc_hd__fill_1".
Reading "sky130_fd_sc_hd__decap_3".
Reading "sky130_fd_sc_hd__decap_8".
Reading "sky130_ef_sc_hd__decap_12".
Reading "sky130_fd_sc_hd__tapvpwrvgnd_1".
Reading "sky130_fd_sc_hd__fill_2".
Reading "buff_flash_clkrst".
Processing sky130_fd_sc_hd__clkbuf_8
Processing sky130_fd_sc_hd__decap_4
Processing sky130_fd_sc_hd__fill_1
Processing sky130_fd_sc_hd__decap_3
Processing sky130_fd_sc_hd__decap_8
Processing sky130_ef_sc_hd__decap_12
Processing sky130_fd_sc_hd__tapvpwrvgnd_1
Processing sky130_fd_sc_hd__fill_2
Processing buff_flash_clkrst
Extracting sky130_fd_sc_hd__clkbuf_8 into sky130_fd_sc_hd__clkbuf_8.ext:
Extracting sky130_fd_sc_hd__decap_4 into sky130_fd_sc_hd__decap_4.ext:
sky130_fd_sc_hd__decap_4: 2 warnings
Extracting sky130_fd_sc_hd__fill_1 into sky130_fd_sc_hd__fill_1.ext:
Extracting sky130_fd_sc_hd__decap_3 into sky130_fd_sc_hd__decap_3.ext:
sky130_fd_sc_hd__decap_3: 2 warnings
Extracting sky130_fd_sc_hd__decap_8 into sky130_fd_sc_hd__decap_8.ext:
sky130_fd_sc_hd__decap_8: 2 warnings
Extracting sky130_ef_sc_hd__decap_12 into sky130_ef_sc_hd__decap_12.ext:
sky130_ef_sc_hd__decap_12: 2 warnings
Extracting sky130_fd_sc_hd__tapvpwrvgnd_1 into sky130_fd_sc_hd__tapvpwrvgnd_1.ext:
Extracting sky130_fd_sc_hd__fill_2 into sky130_fd_sc_hd__fill_2.ext:
Extracting buff_flash_clkrst into buff_flash_clkrst.ext:
Total of 8 warnings.
exttospice finished.

25
signoff/buff_flash_clkrst/openlane-signoff/26-write_powered_def.log Normal file
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OpenROAD 4174c3ad802d2ac1d04d387d2c4b883903f6647e
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO ODB-0222] Reading LEF file: /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/tmp/merged.nom.lef
[WARNING ODB-0220] WARNING (LEFPARS-2036): SOURCE statement is obsolete in version 5.6 and later.
The LEF parser will ignore this statement.
To avoid this warning in the future, remove this statement from the LEF file with version 5.6 or later. See file /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/tmp/merged.nom.lef at line 930.
[INFO ODB-0223] Created 13 technology layers
[INFO ODB-0224] Created 25 technology vias
[INFO ODB-0225] Created 441 library cells
[INFO ODB-0226] Finished LEF file: /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/tmp/merged.nom.lef
[INFO ODB-0127] Reading DEF file: /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/results/routing/buff_flash_clkrst.def
[INFO ODB-0128] Design: buff_flash_clkrst
[INFO ODB-0130] Created 32 pins.
[INFO ODB-0131] Created 73 components and 308 component-terminals.
[INFO ODB-0132] Created 2 special nets and 278 connections.
[INFO ODB-0133] Created 30 nets and 30 connections.
[INFO ODB-0134] Finished DEF file: /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/results/routing/buff_flash_clkrst.def
Top-level design name: buff_flash_clkrst
Found default power net 'VPWR'
Found default ground net 'VGND'
Found 1 power ports.
Found 1 ground ports.
Modified power connections of 73/73 cells.

7
signoff/buff_flash_clkrst/openlane-signoff/26-write_powered_verilog.log Normal file
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OpenROAD 4174c3ad802d2ac1d04d387d2c4b883903f6647e
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
Setting global connections for newly added cells...
[WARNING] Did not save OpenROAD database!
Writing netlist to /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/tmp/signoff/25-buff_flash_clkrst.nl.v...
Writing powered netlist to /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/tmp/signoff/25-buff_flash_clkrst.pnl.v...

293
signoff/buff_flash_clkrst/openlane-signoff/28-buff_flash_clkrst.gds.json Normal file
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[
{
"pins": [
[
"1",
"2",
"3",
"4"
], [
"1",
"2",
"3",
"4"
]
]
},
{
"pins": [
[
"1",
"2",
"3",
"4"
], [
"1",
"2",
"3",
"4"
]
]
},
{
"name": [
"sky130_fd_sc_hd__clkbuf_8",
"sky130_fd_sc_hd__clkbuf_8"
],
"devices": [
[
["sky130_fd_pr__pfet_01v8_hvt", 2],
["sky130_fd_pr__nfet_01v8", 2 ]
], [
["sky130_fd_pr__pfet_01v8_hvt", 2 ],
["sky130_fd_pr__nfet_01v8", 2 ]
]
],
"nets": [
7,
7
],
"badnets": [
],
"badelements": [
],
"pins": [
[
"X",
"VGND",
"VNB",
"A",
"VPWR",
"VPB"
], [
"X",
"VGND",
"VNB",
"A",
"VPWR",
"VPB"
]
]
},
{
"pins": [
[
"VGND",
"VPWR",
"VNB",
"VPB"
], [
"VGND",
"VPWR",
"VNB",
"VPB"
]
]
},
{
"name": [
"sky130_fd_sc_hd__decap_4",
"sky130_fd_sc_hd__decap_4"
],
"devices": [
[
["sky130_fd_pr__pfet_01v8_hvt", 1],
["sky130_fd_pr__nfet_01v8", 1 ]
], [
["sky130_fd_pr__pfet_01v8_hvt", 1 ],
["sky130_fd_pr__nfet_01v8", 1 ]
]
],
"nets": [
4,
4
],
"badnets": [
],
"badelements": [
],
"pins": [
[
"VPB",
"VNB",
"VPWR",
"VGND"
], [
"VPB",
"VNB",
"VPWR",
"VGND"
]
]
},
{
"name": [
"sky130_fd_sc_hd__decap_3",
"sky130_fd_sc_hd__decap_3"
],
"devices": [
[
["sky130_fd_pr__pfet_01v8_hvt", 1],
["sky130_fd_pr__nfet_01v8", 1 ]
], [
["sky130_fd_pr__pfet_01v8_hvt", 1 ],
["sky130_fd_pr__nfet_01v8", 1 ]
]
],
"nets": [
4,
4
],
"badnets": [
],
"badelements": [
],
"pins": [
[
"VPB",
"VNB",
"VPWR",
"VGND"
], [
"VPB",
"VNB",
"VPWR",
"VGND"
]
]
},
{
"name": [
"sky130_fd_sc_hd__decap_8",
"sky130_fd_sc_hd__decap_8"
],
"devices": [
[
["sky130_fd_pr__pfet_01v8_hvt", 1],
["sky130_fd_pr__nfet_01v8", 1 ]
], [
["sky130_fd_pr__pfet_01v8_hvt", 1 ],
["sky130_fd_pr__nfet_01v8", 1 ]
]
],
"nets": [
4,
4
],
"badnets": [
],
"badelements": [
],
"pins": [
[
"VPB",
"VNB",
"VPWR",
"VGND"
], [
"VPB",
"VNB",
"VPWR",
"VGND"
]
]
},
{
"name": [
"buff_flash_clkrst",
"buff_flash_clkrst"
],
"devices": [
[
["sky130_fd_sc_hd__clkbuf_8", 15],
["sky130_ef_sc_hd__decap_12", 1],
["sky130_fd_sc_hd__decap_4", 1],
["sky130_fd_sc_hd__decap_3", 1],
["sky130_fd_sc_hd__decap_8", 1 ]
], [
["sky130_fd_sc_hd__clkbuf_8", 15 ],
["sky130_ef_sc_hd__decap_12", 1 ],
["sky130_fd_sc_hd__decap_4", 1 ],
["sky130_fd_sc_hd__decap_3", 1 ],
["sky130_fd_sc_hd__decap_8", 1 ]
]
],
"nets": [
32,
32
],
"badnets": [
],
"badelements": [
],
"pins": [
[
"VGND",
"VPWR",
"in_n[4]",
"in_n[9]",
"in_n[11]",
"in_n[6]",
"in_s[0]",
"in_s[2]",
"in_n[1]",
"in_n[8]",
"in_n[3]",
"in_n[5]",
"in_n[10]",
"in_s[1]",
"in_n[0]",
"in_n[2]",
"in_n[7]",
"out_s[4]",
"out_s[9]",
"out_s[11]",
"out_s[6]",
"out_n[0]",
"out_n[2]",
"out_s[1]",
"out_s[8]",
"out_s[3]",
"out_s[5]",
"out_s[10]",
"out_n[1]",
"out_s[0]",
"out_s[2]",
"out_s[7]"
], [
"VGND",
"VPWR",
"in_n[4]",
"in_n[9]",
"in_n[11]",
"in_n[6]",
"in_s[0]",
"in_s[2]",
"in_n[1]",
"in_n[8]",
"in_n[3]",
"in_n[5]",
"in_n[10]",
"in_s[1]",
"in_n[0]",
"in_n[2]",
"in_n[7]",
"out_s[4]",
"out_s[9]",
"out_s[11]",
"out_s[6]",
"out_n[0]",
"out_n[2]",
"out_s[1]",
"out_s[8]",
"out_s[3]",
"out_s[5]",
"out_s[10]",
"out_n[1]",
"out_s[0]",
"out_s[2]",
"out_s[7]"
]
]
}
]

3
signoff/buff_flash_clkrst/openlane-signoff/28-buff_flash_clkrst.gds.log Normal file
View File

@ -0,0 +1,3 @@
LVS reports no net, device, pin, or property mismatches.
Total errors = 0

205
signoff/buff_flash_clkrst/openlane-signoff/28-lvs.gds.log Normal file
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@ -0,0 +1,205 @@
Netgen 1.5.234 compiled on Sun Oct 9 10:24:01 UTC 2022
Warning: netgen command 'format' use fully-qualified name '::netgen::format'
Warning: netgen command 'global' use fully-qualified name '::netgen::global'
Reading spice netlist file /home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice
Call to undefined subcircuit sky130_fd_pr__pfet_01v8_hvt
Creating placeholder cell definition.
Call to undefined subcircuit sky130_fd_pr__nfet_01v8
Creating placeholder cell definition.
Call to undefined subcircuit sky130_fd_sc_hd__nand2_2
Creating placeholder cell definition.
Call to undefined subcircuit sky130_fd_sc_hd__nor2_2
Creating placeholder cell definition.
Generating JSON file result
Reading netlist file /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/results/signoff/buff_flash_clkrst.gds.spice
Call to undefined subcircuit sky130_fd_pr__pfet_01v8_hvt
Creating placeholder cell definition.
Call to undefined subcircuit sky130_fd_pr__nfet_01v8
Creating placeholder cell definition.
Reading netlist file /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/tmp/signoff/25-buff_flash_clkrst.pnl.v
Warning: A case-insensitive file has been read and so the verilog file must be treated case-insensitive to match.
Creating placeholder cell definition for module sky130_ef_sc_hd__decap_12.
Reading setup file /home/hosni/OL_LATEST/OpenLane/pdks/sky130A/libs.tech/netgen/sky130A_setup.tcl
Model sky130_fd_pr__res_generic_po pin end_a == end_b
No property mult found for device sky130_fd_pr__res_generic_po
Model sky130_fd_pr__nfet_01v8 pin 1 == 3
No property mult found for device sky130_fd_pr__nfet_01v8
No property sa found for device sky130_fd_pr__nfet_01v8
No property sb found for device sky130_fd_pr__nfet_01v8
No property sd found for device sky130_fd_pr__nfet_01v8
No property nf found for device sky130_fd_pr__nfet_01v8
No property nrd found for device sky130_fd_pr__nfet_01v8
No property nrs found for device sky130_fd_pr__nfet_01v8
No property area found for device sky130_fd_pr__nfet_01v8
No property perim found for device sky130_fd_pr__nfet_01v8
No property topography found for device sky130_fd_pr__nfet_01v8
Model sky130_fd_pr__nfet_01v8 pin 1 == 3
No property as found for device sky130_fd_pr__nfet_01v8
No property ad found for device sky130_fd_pr__nfet_01v8
No property ps found for device sky130_fd_pr__nfet_01v8
No property pd found for device sky130_fd_pr__nfet_01v8
No property mult found for device sky130_fd_pr__nfet_01v8
No property sa found for device sky130_fd_pr__nfet_01v8
No property sb found for device sky130_fd_pr__nfet_01v8
No property sd found for device sky130_fd_pr__nfet_01v8
No property nf found for device sky130_fd_pr__nfet_01v8
No property nrd found for device sky130_fd_pr__nfet_01v8
No property nrs found for device sky130_fd_pr__nfet_01v8
No property area found for device sky130_fd_pr__nfet_01v8
No property perim found for device sky130_fd_pr__nfet_01v8
No property topography found for device sky130_fd_pr__nfet_01v8
Model sky130_fd_pr__pfet_01v8_hvt pin 1 == 3
No property mult found for device sky130_fd_pr__pfet_01v8_hvt
No property sa found for device sky130_fd_pr__pfet_01v8_hvt
No property sb found for device sky130_fd_pr__pfet_01v8_hvt
No property sd found for device sky130_fd_pr__pfet_01v8_hvt
No property nf found for device sky130_fd_pr__pfet_01v8_hvt
No property nrd found for device sky130_fd_pr__pfet_01v8_hvt
No property nrs found for device sky130_fd_pr__pfet_01v8_hvt
No property area found for device sky130_fd_pr__pfet_01v8_hvt
No property perim found for device sky130_fd_pr__pfet_01v8_hvt
No property topography found for device sky130_fd_pr__pfet_01v8_hvt
Model sky130_fd_pr__pfet_01v8_hvt pin 1 == 3
No property as found for device sky130_fd_pr__pfet_01v8_hvt
No property ad found for device sky130_fd_pr__pfet_01v8_hvt
No property ps found for device sky130_fd_pr__pfet_01v8_hvt
No property pd found for device sky130_fd_pr__pfet_01v8_hvt
No property mult found for device sky130_fd_pr__pfet_01v8_hvt
No property sa found for device sky130_fd_pr__pfet_01v8_hvt
No property sb found for device sky130_fd_pr__pfet_01v8_hvt
No property sd found for device sky130_fd_pr__pfet_01v8_hvt
No property nf found for device sky130_fd_pr__pfet_01v8_hvt
No property nrd found for device sky130_fd_pr__pfet_01v8_hvt
No property nrs found for device sky130_fd_pr__pfet_01v8_hvt
No property area found for device sky130_fd_pr__pfet_01v8_hvt
No property perim found for device sky130_fd_pr__pfet_01v8_hvt
No property topography found for device sky130_fd_pr__pfet_01v8_hvt
No property value found for device sky130_fd_pr__diode_pw2nd_05v5
No property mult found for device sky130_fd_pr__diode_pw2nd_05v5
No property perim found for device sky130_fd_pr__diode_pw2nd_05v5
Comparison output logged to file /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/logs/signoff/28-buff_flash_clkrst.gds.log
Logging to file "/home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/logs/signoff/28-buff_flash_clkrst.gds.log" enabled
Circuit sky130_fd_pr__pfet_01v8_hvt contains no devices.
Circuit sky130_fd_pr__nfet_01v8 contains no devices.
Contents of circuit 1: Circuit: 'sky130_fd_sc_hd__clkbuf_8'
Circuit sky130_fd_sc_hd__clkbuf_8 contains 20 device instances.
Class: sky130_fd_pr__nfet_01v8 instances: 10
Class: sky130_fd_pr__pfet_01v8_hvt instances: 10
Circuit contains 7 nets.
Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__clkbuf_8'
Circuit sky130_fd_sc_hd__clkbuf_8 contains 20 device instances.
Class: sky130_fd_pr__nfet_01v8 instances: 10
Class: sky130_fd_pr__pfet_01v8_hvt instances: 10
Circuit contains 7 nets.
Circuit was modified by parallel/series device merging.
New circuit summary:
Contents of circuit 1: Circuit: 'sky130_fd_sc_hd__clkbuf_8'
Circuit sky130_fd_sc_hd__clkbuf_8 contains 4 device instances.
Class: sky130_fd_pr__nfet_01v8 instances: 2
Class: sky130_fd_pr__pfet_01v8_hvt instances: 2
Circuit contains 7 nets.
Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__clkbuf_8'
Circuit sky130_fd_sc_hd__clkbuf_8 contains 4 device instances.
Class: sky130_fd_pr__nfet_01v8 instances: 2
Class: sky130_fd_pr__pfet_01v8_hvt instances: 2
Circuit contains 7 nets.
Circuit 1 contains 4 devices, Circuit 2 contains 4 devices.
Circuit 1 contains 7 nets, Circuit 2 contains 7 nets.
Circuit sky130_ef_sc_hd__decap_12 contains no devices.
Contents of circuit 1: Circuit: 'sky130_fd_sc_hd__decap_4'
Circuit sky130_fd_sc_hd__decap_4 contains 2 device instances.
Class: sky130_fd_pr__nfet_01v8 instances: 1
Class: sky130_fd_pr__pfet_01v8_hvt instances: 1
Circuit contains 4 nets.
Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__decap_4'
Circuit sky130_fd_sc_hd__decap_4 contains 2 device instances.
Class: sky130_fd_pr__nfet_01v8 instances: 1
Class: sky130_fd_pr__pfet_01v8_hvt instances: 1
Circuit contains 4 nets.
Circuit 1 contains 2 devices, Circuit 2 contains 2 devices.
Circuit 1 contains 4 nets, Circuit 2 contains 4 nets.
Contents of circuit 1: Circuit: 'sky130_fd_sc_hd__decap_3'
Circuit sky130_fd_sc_hd__decap_3 contains 2 device instances.
Class: sky130_fd_pr__nfet_01v8 instances: 1
Class: sky130_fd_pr__pfet_01v8_hvt instances: 1
Circuit contains 4 nets.
Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__decap_3'
Circuit sky130_fd_sc_hd__decap_3 contains 2 device instances.
Class: sky130_fd_pr__nfet_01v8 instances: 1
Class: sky130_fd_pr__pfet_01v8_hvt instances: 1
Circuit contains 4 nets.
Circuit 1 contains 2 devices, Circuit 2 contains 2 devices.
Circuit 1 contains 4 nets, Circuit 2 contains 4 nets.
Contents of circuit 1: Circuit: 'sky130_fd_sc_hd__decap_8'
Circuit sky130_fd_sc_hd__decap_8 contains 2 device instances.
Class: sky130_fd_pr__nfet_01v8 instances: 1
Class: sky130_fd_pr__pfet_01v8_hvt instances: 1
Circuit contains 4 nets.
Contents of circuit 2: Circuit: 'sky130_fd_sc_hd__decap_8'
Circuit sky130_fd_sc_hd__decap_8 contains 2 device instances.
Class: sky130_fd_pr__nfet_01v8 instances: 1
Class: sky130_fd_pr__pfet_01v8_hvt instances: 1
Circuit contains 4 nets.
Circuit 1 contains 2 devices, Circuit 2 contains 2 devices.
Circuit 1 contains 4 nets, Circuit 2 contains 4 nets.
Contents of circuit 1: Circuit: 'buff_flash_clkrst'
Circuit buff_flash_clkrst contains 48 device instances.
Class: sky130_ef_sc_hd__decap_12 instances: 7
Class: sky130_fd_sc_hd__clkbuf_8 instances: 15
Class: sky130_fd_sc_hd__decap_3 instances: 12
Class: sky130_fd_sc_hd__decap_4 instances: 10
Class: sky130_fd_sc_hd__decap_8 instances: 4
Circuit contains 32 nets.
Contents of circuit 2: Circuit: 'buff_flash_clkrst'
Circuit buff_flash_clkrst contains 48 device instances.
Class: sky130_ef_sc_hd__decap_12 instances: 7
Class: sky130_fd_sc_hd__clkbuf_8 instances: 15
Class: sky130_fd_sc_hd__decap_3 instances: 12
Class: sky130_fd_sc_hd__decap_4 instances: 10
Class: sky130_fd_sc_hd__decap_8 instances: 4
Circuit contains 32 nets.
Circuit was modified by parallel/series device merging.
New circuit summary:
Contents of circuit 1: Circuit: 'buff_flash_clkrst'
Circuit buff_flash_clkrst contains 19 device instances.
Class: sky130_ef_sc_hd__decap_12 instances: 1
Class: sky130_fd_sc_hd__clkbuf_8 instances: 15
Class: sky130_fd_sc_hd__decap_3 instances: 1
Class: sky130_fd_sc_hd__decap_4 instances: 1
Class: sky130_fd_sc_hd__decap_8 instances: 1
Circuit contains 32 nets.
Contents of circuit 2: Circuit: 'buff_flash_clkrst'
Circuit buff_flash_clkrst contains 19 device instances.
Class: sky130_ef_sc_hd__decap_12 instances: 1
Class: sky130_fd_sc_hd__clkbuf_8 instances: 15
Class: sky130_fd_sc_hd__decap_3 instances: 1
Class: sky130_fd_sc_hd__decap_4 instances: 1
Class: sky130_fd_sc_hd__decap_8 instances: 1
Circuit contains 32 nets.
Circuit 1 contains 19 devices, Circuit 2 contains 19 devices.
Circuit 1 contains 32 nets, Circuit 2 contains 32 nets.
Final result:
Circuits match uniquely.
.
Logging to file "/home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/logs/signoff/28-buff_flash_clkrst.gds.log" disabled
LVS Done.

36
signoff/buff_flash_clkrst/openlane-signoff/29-drc.log Normal file
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@ -0,0 +1,36 @@
Magic 8.3 revision 324 - Compiled on Thu Sep 15 11:38:02 UTC 2022.
Starting magic under Tcl interpreter
Using the terminal as the console.
Using NULL graphics device.
Processing system .magicrc file
Sourcing design .magicrc for technology sky130A ...
2 Magic internal units = 1 Lambda
Input style sky130(vendor): scaleFactor=2, multiplier=2
The following types are not handled by extraction and will be treated as non-electrical types:
ubm
Scaled tech values by 2 / 1 to match internal grid scaling
Loading sky130A Device Generator Menu ...
Using technology "sky130A", version 1.0.341-2-gde752ec
Warning: Calma reading is not undoable! I hope that's OK.
Library written using GDS-II Release 3.0
Library name: buff_flash_clkrst
Reading "sky130_fd_sc_hd__clkbuf_8".
Reading "sky130_fd_sc_hd__decap_4".
Reading "sky130_fd_sc_hd__fill_1".
Reading "sky130_fd_sc_hd__decap_3".
Reading "sky130_fd_sc_hd__decap_8".
Reading "sky130_ef_sc_hd__decap_12".
Reading "sky130_fd_sc_hd__tapvpwrvgnd_1".
Reading "sky130_fd_sc_hd__fill_2".
Reading "buff_flash_clkrst".
[INFO]: Loading buff_flash_clkrst
DRC style is now "drc(full)"
Loading DRC CIF style.
No errors found.
[INFO]: COUNT: 0
[INFO]: Should be divided by 3 or 4
[INFO]: DRC Checking DONE (/home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/reports/signoff/drc.rpt)
[INFO]: Saving mag view with DRC errors (/home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/results/signoff/buff_flash_clkrst.drc.mag)
[INFO]: Saved

5
signoff/buff_flash_clkrst/openlane-signoff/30-antenna.log Normal file
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@ -0,0 +1,5 @@
OpenROAD 4174c3ad802d2ac1d04d387d2c4b883903f6647e
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO ANT-0002] Found 0 net violations.
[INFO ANT-0001] Found 0 pin violations.

186
signoff/buff_flash_clkrst/openlane-signoff/sdf/max/buff_flash_clkrst.ff.sdf Normal file
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@ -0,0 +1,186 @@
(DELAYFILE
(SDFVERSION "3.0")
(DESIGN "buff_flash_clkrst")
(DATE "Thu Oct 13 17:29:04 2022")
(VENDOR "Parallax")
(PROGRAM "STA")
(VERSION "2.3.1")
(DIVIDER .)
(VOLTAGE 1.600::1.600)
(PROCESS "1.000::1.000")
(TEMPERATURE 100.000::100.000)
(TIMESCALE 1ns)
(CELL
(CELLTYPE "buff_flash_clkrst")
(INSTANCE)
(DELAY
(ABSOLUTE
(INTERCONNECT in_n[0] BUF\[3\].A (0.013:0.013:0.013) (0.004:0.004:0.004))
(INTERCONNECT in_n[10] BUF\[13\].A (0.012:0.012:0.012) (0.004:0.004:0.004))
(INTERCONNECT in_n[11] BUF\[14\].A (0.019:0.019:0.019) (0.006:0.006:0.006))
(INTERCONNECT in_n[1] BUF\[4\].A (0.015:0.015:0.015) (0.005:0.005:0.005))
(INTERCONNECT in_n[2] BUF\[5\].A (0.017:0.017:0.017) (0.005:0.005:0.005))
(INTERCONNECT in_n[3] BUF\[6\].A (0.013:0.013:0.013) (0.004:0.004:0.004))
(INTERCONNECT in_n[4] BUF\[7\].A (0.015:0.015:0.015) (0.004:0.004:0.004))
(INTERCONNECT in_n[5] BUF\[8\].A (0.014:0.014:0.014) (0.004:0.004:0.004))
(INTERCONNECT in_n[6] BUF\[9\].A (0.016:0.016:0.016) (0.005:0.005:0.005))
(INTERCONNECT in_n[7] BUF\[10\].A (0.016:0.016:0.016) (0.005:0.005:0.005))
(INTERCONNECT in_n[8] BUF\[11\].A (0.013:0.013:0.013) (0.004:0.004:0.004))
(INTERCONNECT in_n[9] BUF\[12\].A (0.016:0.016:0.016) (0.005:0.005:0.005))
(INTERCONNECT in_s[0] BUF\[0\].A (0.013:0.013:0.013) (0.004:0.004:0.004))
(INTERCONNECT in_s[1] BUF\[1\].A (0.016:0.016:0.016) (0.005:0.005:0.005))
(INTERCONNECT in_s[2] BUF\[2\].A (0.013:0.013:0.013) (0.004:0.004:0.004))
(INTERCONNECT BUF\[0\].X out_n[0] (0.002:0.002:0.002) (0.002:0.002:0.002))
(INTERCONNECT BUF\[10\].X out_s[7] (0.002:0.002:0.002) (0.002:0.002:0.002))
(INTERCONNECT BUF\[11\].X out_s[8] (0.002:0.002:0.002) (0.002:0.002:0.002))
(INTERCONNECT BUF\[12\].X out_s[9] (0.001:0.001:0.001) (0.001:0.001:0.001))
(INTERCONNECT BUF\[13\].X out_s[10] (0.002:0.002:0.002) (0.002:0.002:0.002))
(INTERCONNECT BUF\[14\].X out_s[11] (0.002:0.002:0.002) (0.002:0.002:0.002))
(INTERCONNECT BUF\[1\].X out_n[1] (0.002:0.002:0.002) (0.002:0.002:0.002))
(INTERCONNECT BUF\[2\].X out_n[2] (0.002:0.002:0.002) (0.002:0.002:0.002))
(INTERCONNECT BUF\[3\].X out_s[0] (0.002:0.002:0.002) (0.002:0.002:0.002))
(INTERCONNECT BUF\[4\].X out_s[1] (0.002:0.002:0.002) (0.002:0.002:0.002))
(INTERCONNECT BUF\[5\].X out_s[2] (0.002:0.002:0.002) (0.002:0.002:0.002))
(INTERCONNECT BUF\[6\].X out_s[3] (0.002:0.002:0.002) (0.002:0.002:0.002))
(INTERCONNECT BUF\[7\].X out_s[4] (0.002:0.002:0.002) (0.002:0.002:0.002))
(INTERCONNECT BUF\[8\].X out_s[5] (0.002:0.002:0.002) (0.002:0.002:0.002))
(INTERCONNECT BUF\[9\].X out_s[6] (0.002:0.002:0.002) (0.002:0.002:0.002))
)
)
)
(CELL
(CELLTYPE "sky130_fd_sc_hd__clkbuf_8")
(INSTANCE BUF\[0\])
(DELAY
(ABSOLUTE
(IOPATH A X (0.099:0.099:0.099) (0.098:0.098:0.098))
)
)
)
(CELL
(CELLTYPE "sky130_fd_sc_hd__clkbuf_8")
(INSTANCE BUF\[10\])
(DELAY
(ABSOLUTE
(IOPATH A X (0.100:0.100:0.100) (0.098:0.098:0.098))
)
)
)
(CELL
(CELLTYPE "sky130_fd_sc_hd__clkbuf_8")
(INSTANCE BUF\[11\])
(DELAY
(ABSOLUTE
(IOPATH A X (0.099:0.099:0.099) (0.097:0.097:0.097))
)
)
)
(CELL
(CELLTYPE "sky130_fd_sc_hd__clkbuf_8")
(INSTANCE BUF\[12\])
(DELAY
(ABSOLUTE
(IOPATH A X (0.099:0.099:0.099) (0.098:0.098:0.098))
)
)
)
(CELL
(CELLTYPE "sky130_fd_sc_hd__clkbuf_8")
(INSTANCE BUF\[13\])
(DELAY
(ABSOLUTE
(IOPATH A X (0.099:0.099:0.099) (0.097:0.097:0.097))
)
)
)
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186
signoff/buff_flash_clkrst/openlane-signoff/sdf/max/buff_flash_clkrst.ss.sdf Normal file
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186
signoff/buff_flash_clkrst/openlane-signoff/sdf/max/buff_flash_clkrst.tt.sdf Normal file
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186
signoff/buff_flash_clkrst/openlane-signoff/sdf/min/buff_flash_clkrst.ff.sdf Normal file
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@ -0,0 +1,186 @@
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186
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186
signoff/buff_flash_clkrst/openlane-signoff/sdf/nom/buff_flash_clkrst.ff.sdf Normal file
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186
signoff/buff_flash_clkrst/openlane-signoff/sdf/nom/buff_flash_clkrst.tt.sdf Normal file
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619
signoff/buff_flash_clkrst/openlane-signoff/spef/buff_flash_clkrst.max.spef Normal file
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*SPEF "ieee 1481-1999"
*DESIGN "buff_flash_clkrst"
*DATE "11:11:11 Fri 11 11, 1111"
*VENDOR "OpenRCX"
*PROGRAM "Parallel Extraction"
*VERSION "1.0"
*DESIGN_FLOW "NAME_SCOPE LOCAL" "PIN_CAP NONE"
*DIVIDER /
*DELIMITER :
*BUS_DELIMITER []
*T_UNIT 1 NS
*C_UNIT 1 PF
*R_UNIT 1 OHM
*L_UNIT 1 HENRY
*NAME_MAP
*3 in_n[0]
*4 in_n[10]
*5 in_n[11]
*6 in_n[1]
*7 in_n[2]
*8 in_n[3]
*9 in_n[4]
*10 in_n[5]
*11 in_n[6]
*12 in_n[7]
*13 in_n[8]
*14 in_n[9]
*15 in_s[0]
*16 in_s[1]
*17 in_s[2]
*18 out_n[0]
*19 out_n[1]
*20 out_n[2]
*21 out_s[0]
*22 out_s[10]
*23 out_s[11]
*24 out_s[1]
*25 out_s[2]
*26 out_s[3]
*27 out_s[4]
*28 out_s[5]
*29 out_s[6]
*30 out_s[7]
*31 out_s[8]
*32 out_s[9]
*33 BUF\[0\]
*34 BUF\[10\]
*35 BUF\[11\]
*36 BUF\[12\]
*37 BUF\[13\]
*38 BUF\[14\]
*39 BUF\[1\]
*40 BUF\[2\]
*41 BUF\[3\]
*42 BUF\[4\]
*43 BUF\[5\]
*44 BUF\[6\]
*45 BUF\[7\]
*46 BUF\[8\]
*47 BUF\[9\]
*48 FILLER_0_19
*49 FILLER_0_27
*50 FILLER_0_29
*51 FILLER_0_3
*52 FILLER_0_41
*53 FILLER_0_54
*54 FILLER_0_57
*55 FILLER_0_7
*56 FILLER_0_70
*57 FILLER_0_74
*58 FILLER_1_17
*59 FILLER_1_3
*60 FILLER_1_32
*61 FILLER_1_47
*62 FILLER_1_55
*63 FILLER_1_57
*64 FILLER_1_70
*65 FILLER_1_74
*66 FILLER_2_26
*67 FILLER_2_29
*68 FILLER_2_3
*69 FILLER_2_52
*70 FILLER_2_67
*71 FILLER_3_15
*72 FILLER_3_27
*73 FILLER_3_3
*74 FILLER_3_42
*75 FILLER_3_54
*76 FILLER_3_57
*77 FILLER_3_70
*78 FILLER_3_74
*79 FILLER_4_19
*80 FILLER_4_27
*81 FILLER_4_29
*82 FILLER_4_3
*83 FILLER_4_41
*84 FILLER_4_53
*85 FILLER_4_57
*86 FILLER_4_7
*87 FILLER_4_70
*88 FILLER_4_74
*89 PHY_0
*90 PHY_1
*91 PHY_2
*92 PHY_3
*93 PHY_4
*94 PHY_5
*95 PHY_6
*96 PHY_7
*97 PHY_8
*98 PHY_9
*99 TAP_10
*100 TAP_11
*101 TAP_12
*102 TAP_13
*103 TAP_14
*104 TAP_15
*105 TAP_16
*PORTS
in_n[0] I
in_n[10] I
in_n[11] I
in_n[1] I
in_n[2] I
in_n[3] I
in_n[4] I
in_n[5] I
in_n[6] I
in_n[7] I
in_n[8] I
in_n[9] I
in_s[0] I
in_s[1] I
in_s[2] I
out_n[0] O
out_n[1] O
out_n[2] O
out_s[0] O
out_s[10] O
out_s[11] O
out_s[1] O
out_s[2] O
out_s[3] O
out_s[4] O
out_s[5] O
out_s[6] O
out_s[7] O
out_s[8] O
out_s[9] O
*D_NET *3 0.000809487
*CONN
*P in_n[0] I
*I *41:A I *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 in_n[0] 0.000321834
2 *41:A 0.000321834
3 *41:A out_n[2] 0.000165819
4 *41:A *42:A 0
*RES
1 in_n[0] *41:A 45.8093
*END
*D_NET *4 0.00058245
*CONN
*P in_n[10] I
*I *37:A I *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 in_n[10] 0.000262561
2 *37:A 0.000262561
3 *37:A *5:16 0
4 *37:A *14:10 0
5 *37:A *22:9 5.73288e-05
*RES
1 in_n[10] *37:A 43.51
*END
*D_NET *5 0.00314715
*CONN
*P in_n[11] I
*I *38:A I *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 in_n[11] 0.00125418
2 *38:A 0
3 *5:16 0.00125418
4 *5:16 out_s[10] 0
5 *5:16 out_s[9] 0.000140259
6 *5:16 *14:10 0.000186606
7 *5:16 *23:7 0.000311915
8 *37:A *5:16 0
*RES
1 in_n[11] *5:16 41.825
2 *5:16 *38:A 23
*END
*D_NET *6 0.00149003
*CONN
*P in_n[1] I
*I *42:A I *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 in_n[1] 0.00032827
2 *42:A 0.00032827
3 *42:A out_s[0] 7.66085e-05
4 *42:A *7:10 0.000756884
5 *41:A *42:A 0
*RES
1 in_n[1] *42:A 48.3779
*END
*D_NET *7 0.00223276
*CONN
*P in_n[2] I
*I *43:A I *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 in_n[2] 0.00069966
2 *43:A 0
3 *7:10 0.00069966
4 *7:10 out_s[0] 0
5 *7:10 out_s[1] 7.03766e-05
6 *7:10 out_s[2] 6.17437e-06
7 *7:10 *44:A 0
8 *42:A *7:10 0.000756884
*RES
1 in_n[2] *7:10 30.9707
2 *7:10 *43:A 23
*END
*D_NET *8 0.000770166
*CONN
*P in_n[3] I
*I *44:A I *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 in_n[3] 0.000385083
2 *44:A 0.000385083
3 *44:A *9:9 0
4 *7:10 *44:A 0
*RES
1 in_n[3] *44:A 45.8093
*END
*D_NET *9 0.00142628
*CONN
*P in_n[4] I
*I *45:A I *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 in_n[4] 0.000615049
2 *45:A 0
3 *9:9 0.000615049
4 *9:9 out_s[3] 0.000196178
5 *9:9 *46:A 0
6 *44:A *9:9 0
*RES
1 in_n[4] *9:9 28.4436
2 *9:9 *45:A 23
*END
*D_NET *10 0.00113314
*CONN
*P in_n[5] I
*I *46:A I *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 in_n[5] 0.000566572
2 *46:A 0.000566572
3 *9:9 *46:A 0
*RES
1 in_n[5] *46:A 49.3307
*END
*D_NET *11 0.00188726
*CONN
*P in_n[6] I
*I *47:A I *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 in_n[6] 0.00049832
2 *47:A 0
3 *11:10 0.00049832
4 *11:10 *12:8 0.000748939
5 *11:10 *29:7 0.000141677
*RES
1 in_n[6] *11:10 28.3814
2 *11:10 *47:A 23
*END
*D_NET *12 0.00204954
*CONN
*P in_n[7] I
*I *34:A I *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 in_n[7] 0.000567827
2 *34:A 0
3 *12:8 0.000567827
4 *12:8 out_s[6] 3.67805e-05
5 *12:8 out_s[8] 0
6 *12:8 *35:A 0
7 *12:8 *30:7 0.000128169
8 *11:10 *12:8 0.000748939
*RES
1 in_n[7] *12:8 29.3964
2 *12:8 *34:A 23
*END
*D_NET *13 0.000912246
*CONN
*P in_n[8] I
*I *35:A I *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 in_n[8] 0.000453036
2 *35:A 0.000453036
3 *35:A *14:10 0
4 *35:A *31:7 6.17437e-06
5 *12:8 *35:A 0
*RES
1 in_n[8] *35:A 46.5757
*END
*D_NET *14 0.00209477
*CONN
*P in_n[9] I
*I *36:A I *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 in_n[9] 0.000902356
2 *36:A 0
3 *14:10 0.000902356
4 *14:10 out_s[10] 0
5 *14:10 *23:7 0.000103447
6 *35:A *14:10 0
7 *37:A *14:10 0
8 *5:16 *14:10 0.000186606
*RES
1 in_n[9] *14:10 33.0629
2 *14:10 *36:A 23
*END
*D_NET *15 0.000609775
*CONN
*P in_s[0] I
*I *33:A I *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 in_s[0] 0.000254485
2 *33:A 0.000254485
3 *33:A *16:12 0
4 *33:A *18:7 0.000100805
*RES
1 in_s[0] *33:A 42.7643
*END
*D_NET *16 0.00215843
*CONN
*P in_s[1] I
*I *39:A I *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 in_s[1] 0.000669693
2 *39:A 0
3 *16:12 0.000669693
4 *16:12 out_n[0] 0.000819045
5 *16:12 out_n[2] 0
6 *16:12 *40:A 0
7 *33:A *16:12 0
*RES
1 in_s[1] *16:12 30.8464
2 *16:12 *39:A 23
*END
*D_NET *17 0.000791768
*CONN
*P in_s[2] I
*I *40:A I *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 in_s[2] 0.000395884
2 *40:A 0.000395884
3 *40:A out_s[0] 0
4 *16:12 *40:A 0
*RES
1 in_s[2] *40:A 45.3329
*END
*D_NET *18 0.00275982
*CONN
*P out_n[0] O
*I *33:X O *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 out_n[0] 0.000649033
2 *33:X 0.000270953
3 *18:7 0.000919986
4 out_n[0] out_n[1] 0
5 out_n[0] out_n[2] 0
6 *33:A *18:7 0.000100805
7 *16:12 out_n[0] 0.000819045
*RES
1 *33:X *18:7 42.9093
2 *18:7 out_n[0] 16.4886
*END
*D_NET *19 0.000996874
*CONN
*P out_n[1] O
*I *39:X O *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 out_n[1] 0.000351055
2 *39:X 0.000351055
3 out_n[1] out_n[2] 0.000294763
4 out_n[0] out_n[1] 0
*RES
1 *39:X out_n[1] 45.395
*END
*D_NET *20 0.00183616
*CONN
*P out_n[2] O
*I *40:X O *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 out_n[2] 0.000507504
2 *40:X 0.000180283
3 *20:7 0.000687787
4 out_n[2] out_s[0] 0
5 out_n[0] out_n[2] 0
6 out_n[1] out_n[2] 0.000294763
7 *41:A out_n[2] 0.000165819
8 *16:12 out_n[2] 0
*RES
1 *40:X *20:7 40.5271
2 *20:7 out_n[2] 12.4907
*END
*D_NET *21 0.00163663
*CONN
*P out_s[0] O
*I *41:X O *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 out_s[0] 0.000548786
2 *41:X 6.80678e-05
3 *21:7 0.000616853
4 out_s[0] out_s[1] 0.00032632
5 out_s[0] out_s[2] 0
6 out_n[2] out_s[0] 0
7 *40:A out_s[0] 0
8 *42:A out_s[0] 7.66085e-05
9 *7:10 out_s[0] 0
*RES
1 *41:X *21:7 39.0979
2 *21:7 out_s[0] 14.935
*END
*D_NET *22 0.0022753
*CONN
*P out_s[10] O
*I *37:X O *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 out_s[10] 0.000810796
2 *37:X 0.000298189
3 *22:9 0.00110899
4 out_s[10] out_s[11] 0
5 out_s[10] out_s[9] 0
6 *37:A *22:9 5.73288e-05
7 *5:16 out_s[10] 0
8 *14:10 out_s[10] 0
*RES
1 *37:X *22:9 42.93
2 *22:9 out_s[10] 14.3964
*END
*D_NET *23 0.00285697
*CONN
*P out_s[11] O
*I *38:X O *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 out_s[11] 0.000131317
2 *38:X 0.00101936
3 *23:7 0.00115068
4 *23:7 out_s[9] 0.000140259
5 out_s[10] out_s[11] 0
6 *5:16 *23:7 0.000311915
7 *14:10 *23:7 0.000103447
*RES
1 *38:X *23:7 37.4586
2 *23:7 out_s[11] 17.3614
*END
*D_NET *24 0.00157731
*CONN
*P out_s[1] O
*I *42:X O *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 out_s[1] 0.00047529
2 *42:X 0.00047529
3 out_s[1] out_s[2] 0.000230031
4 out_s[1] out_s[3] 0
5 out_s[0] out_s[1] 0.00032632
6 *7:10 out_s[1] 7.03766e-05
*RES
1 *42:X out_s[1] 49.8279
*END
*D_NET *25 0.00106966
*CONN
*P out_s[2] O
*I *43:X O *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 out_s[2] 0.000416727
2 *43:X 0.000416727
3 out_s[2] out_s[3] 0
4 out_s[0] out_s[2] 0
5 out_s[1] out_s[2] 0.000230031
6 *7:10 out_s[2] 6.17437e-06
*RES
1 *43:X out_s[2] 48.875
*END
*D_NET *26 0.00157855
*CONN
*P out_s[3] O
*I *44:X O *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 out_s[3] 0.000532775
2 *44:X 0.000158411
3 *26:7 0.000691186
4 out_s[3] out_s[4] 0
5 out_s[3] out_s[5] 0
6 out_s[1] out_s[3] 0
7 out_s[2] out_s[3] 0
8 *9:9 out_s[3] 0.000196178
*RES
1 *44:X *26:7 40.5271
2 *26:7 out_s[3] 11.5171
*END
*D_NET *27 0.000935888
*CONN
*P out_s[4] O
*I *45:X O *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 out_s[4] 0.0004112
2 *45:X 0.0004112
3 out_s[4] out_s[5] 0.000113488
4 out_s[3] out_s[4] 0
*RES
1 *45:X out_s[4] 46.7
*END
*D_NET *28 0.00124869
*CONN
*P out_s[5] O
*I *46:X O *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 out_s[5] 0.000567599
2 *46:X 0.000567599
3 out_s[5] out_s[6] 0
4 out_s[3] out_s[5] 0
5 out_s[4] out_s[5] 0.000113488
*RES
1 *46:X out_s[5] 48.875
*END
*D_NET *29 0.00207606
*CONN
*P out_s[6] O
*I *47:X O *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 out_s[6] 0.000503989
2 *47:X 0.000404635
3 *29:7 0.000908623
4 out_s[6] out_s[7] 8.03508e-05
5 out_s[5] out_s[6] 0
6 *11:10 *29:7 0.000141677
7 *12:8 out_s[6] 3.67805e-05
*RES
1 *47:X *29:7 44.3386
2 *29:7 out_s[6] 9.59071
*END
*D_NET *30 0.0014735
*CONN
*P out_s[7] O
*I *34:X O *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 out_s[7] 0.00028451
2 *34:X 0.00034798
3 *30:7 0.00063249
4 out_s[7] out_s[8] 0
5 out_s[6] out_s[7] 8.03508e-05
6 *12:8 *30:7 0.000128169
*RES
1 *34:X *30:7 44.3386
2 *30:7 out_s[7] 5.88286
*END
*D_NET *31 0.00179676
*CONN
*P out_s[8] O
*I *35:X O *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 out_s[8] 0.000680814
2 *35:X 0.000193091
3 *31:7 0.000873905
4 out_s[8] out_s[9] 4.27783e-05
5 out_s[7] out_s[8] 0
6 *35:A *31:7 6.17437e-06
7 *12:8 out_s[8] 0
*RES
1 *35:X *31:7 41.0036
2 *31:7 out_s[8] 12.76
*END
*D_NET *32 0.000667532
*CONN
*P out_s[9] O
*I *36:X O *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 out_s[9] 0.000172118
2 *36:X 0.000172118
3 out_s[10] out_s[9] 0
4 out_s[8] out_s[9] 4.27783e-05
5 *5:16 out_s[9] 0.000140259
6 *23:7 out_s[9] 0.000140259
*RES
1 *36:X out_s[9] 42.2879
*END

587
signoff/buff_flash_clkrst/openlane-signoff/spef/buff_flash_clkrst.min.spef Normal file
View File

@ -0,0 +1,587 @@
*SPEF "ieee 1481-1999"
*DESIGN "buff_flash_clkrst"
*DATE "11:11:11 Fri 11 11, 1111"
*VENDOR "OpenRCX"
*PROGRAM "Parallel Extraction"
*VERSION "1.0"
*DESIGN_FLOW "NAME_SCOPE LOCAL" "PIN_CAP NONE"
*DIVIDER /
*DELIMITER :
*BUS_DELIMITER []
*T_UNIT 1 NS
*C_UNIT 1 PF
*R_UNIT 1 OHM
*L_UNIT 1 HENRY
*NAME_MAP
*3 in_n[0]
*4 in_n[10]
*5 in_n[11]
*6 in_n[1]
*7 in_n[2]
*8 in_n[3]
*9 in_n[4]
*10 in_n[5]
*11 in_n[6]
*12 in_n[7]
*13 in_n[8]
*14 in_n[9]
*15 in_s[0]
*16 in_s[1]
*17 in_s[2]
*18 out_n[0]
*19 out_n[1]
*20 out_n[2]
*21 out_s[0]
*22 out_s[10]
*23 out_s[11]
*24 out_s[1]
*25 out_s[2]
*26 out_s[3]
*27 out_s[4]
*28 out_s[5]
*29 out_s[6]
*30 out_s[7]
*31 out_s[8]
*32 out_s[9]
*33 BUF\[0\]
*34 BUF\[10\]
*35 BUF\[11\]
*36 BUF\[12\]
*37 BUF\[13\]
*38 BUF\[14\]
*39 BUF\[1\]
*40 BUF\[2\]
*41 BUF\[3\]
*42 BUF\[4\]
*43 BUF\[5\]
*44 BUF\[6\]
*45 BUF\[7\]
*46 BUF\[8\]
*47 BUF\[9\]
*48 FILLER_0_19
*49 FILLER_0_27
*50 FILLER_0_29
*51 FILLER_0_3
*52 FILLER_0_41
*53 FILLER_0_54
*54 FILLER_0_57
*55 FILLER_0_7
*56 FILLER_0_70
*57 FILLER_0_74
*58 FILLER_1_17
*59 FILLER_1_3
*60 FILLER_1_32
*61 FILLER_1_47
*62 FILLER_1_55
*63 FILLER_1_57
*64 FILLER_1_70
*65 FILLER_1_74
*66 FILLER_2_26
*67 FILLER_2_29
*68 FILLER_2_3
*69 FILLER_2_52
*70 FILLER_2_67
*71 FILLER_3_15
*72 FILLER_3_27
*73 FILLER_3_3
*74 FILLER_3_42
*75 FILLER_3_54
*76 FILLER_3_57
*77 FILLER_3_70
*78 FILLER_3_74
*79 FILLER_4_19
*80 FILLER_4_27
*81 FILLER_4_29
*82 FILLER_4_3
*83 FILLER_4_41
*84 FILLER_4_53
*85 FILLER_4_57
*86 FILLER_4_7
*87 FILLER_4_70
*88 FILLER_4_74
*89 PHY_0
*90 PHY_1
*91 PHY_2
*92 PHY_3
*93 PHY_4
*94 PHY_5
*95 PHY_6
*96 PHY_7
*97 PHY_8
*98 PHY_9
*99 TAP_10
*100 TAP_11
*101 TAP_12
*102 TAP_13
*103 TAP_14
*104 TAP_15
*105 TAP_16
*PORTS
in_n[0] I
in_n[10] I
in_n[11] I
in_n[1] I
in_n[2] I
in_n[3] I
in_n[4] I
in_n[5] I
in_n[6] I
in_n[7] I
in_n[8] I
in_n[9] I
in_s[0] I
in_s[1] I
in_s[2] I
out_n[0] O
out_n[1] O
out_n[2] O
out_s[0] O
out_s[10] O
out_s[11] O
out_s[1] O
out_s[2] O
out_s[3] O
out_s[4] O
out_s[5] O
out_s[6] O
out_s[7] O
out_s[8] O
out_s[9] O
*D_NET *3 0.000698578
*CONN
*P in_n[0] I
*I *41:A I *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 in_n[0] 0.000265612
2 *41:A 0.000265612
3 *41:A out_n[2] 0.000167353
4 *41:A *42:A 0
*RES
1 in_n[0] *41:A 9.255
*END
*D_NET *4 0.000496833
*CONN
*P in_n[10] I
*I *37:A I *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 in_n[10] 0.000223693
2 *37:A 0.000223693
3 *37:A out_s[10] 4.94474e-05
4 *37:A *36:A 0
5 *37:A *38:A 0
*RES
1 in_n[10] *37:A 7.59
*END
*D_NET *5 0.00265835
*CONN
*P in_n[11] I
*I *38:A I *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 in_n[11] 0.0010441
2 *38:A 0.0010441
3 *38:A out_s[10] 0
4 *38:A out_s[11] 0.000287765
5 *38:A out_s[9] 0.000123225
6 *38:A *36:A 0.000159156
7 *37:A *38:A 0
*RES
1 in_n[11] *38:A 23.025
*END
*D_NET *6 0.00123947
*CONN
*P in_n[1] I
*I *42:A I *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 in_n[1] 0.000265945
2 *42:A 0.000265945
3 *42:A out_s[0] 7.75325e-05
4 *42:A *43:A 0.000630049
5 *41:A *42:A 0
*RES
1 in_n[1] *42:A 11.115
*END
*D_NET *7 0.00183936
*CONN
*P in_n[2] I
*I *43:A I *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 in_n[2] 0.000568975
2 *43:A 0.000568975
3 *43:A out_s[0] 0
4 *43:A out_s[1] 6.55328e-05
5 *43:A out_s[2] 5.83121e-06
6 *43:A *44:A 0
7 *42:A *43:A 0.000630049
*RES
1 in_n[2] *43:A 15.165
*END
*D_NET *8 0.000671935
*CONN
*P in_n[3] I
*I *44:A I *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 in_n[3] 0.000335968
2 *44:A 0.000335968
3 *44:A *45:A 0
4 *43:A *44:A 0
*RES
1 in_n[3] *44:A 9.255
*END
*D_NET *9 0.00122617
*CONN
*P in_n[4] I
*I *45:A I *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 in_n[4] 0.00052251
2 *45:A 0.00052251
3 *45:A out_s[3] 0.000181152
4 *45:A *46:A 0
5 *44:A *45:A 0
*RES
1 in_n[4] *45:A 13.335
*END
*D_NET *10 0.000985911
*CONN
*P in_n[5] I
*I *46:A I *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 in_n[5] 0.000492956
2 *46:A 0.000492956
3 *45:A *46:A 0
*RES
1 in_n[5] *46:A 11.805
*END
*D_NET *11 0.00156745
*CONN
*P in_n[6] I
*I *47:A I *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 in_n[6] 0.000410161
2 *47:A 0.000410161
3 *47:A out_s[6] 0.00012349
4 *47:A *34:A 0.000623638
*RES
1 in_n[6] *47:A 13.29
*END
*D_NET *12 0.00169542
*CONN
*P in_n[7] I
*I *34:A I *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 in_n[7] 0.000457718
2 *34:A 0.000457718
3 *34:A out_s[6] 4.04613e-05
4 *34:A out_s[7] 0.000115886
5 *34:A out_s[8] 0
6 *34:A *35:A 0
7 *47:A *34:A 0.000623638
*RES
1 in_n[7] *34:A 14.025
*END
*D_NET *13 0.000773264
*CONN
*P in_n[8] I
*I *35:A I *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 in_n[8] 0.000383717
2 *35:A 0.000383717
3 *35:A out_s[8] 5.83121e-06
4 *35:A *36:A 0
5 *34:A *35:A 0
*RES
1 in_n[8] *35:A 9.81
*END
*D_NET *14 0.00175178
*CONN
*P in_n[9] I
*I *36:A I *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 in_n[9] 0.00074955
2 *36:A 0.00074955
3 *36:A out_s[10] 0
4 *36:A out_s[11] 9.3521e-05
5 *35:A *36:A 0
6 *37:A *36:A 0
7 *38:A *36:A 0.000159156
*RES
1 in_n[9] *36:A 16.68
*END
*D_NET *15 0.000514326
*CONN
*P in_s[0] I
*I *33:A I *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 in_s[0] 0.000213288
2 *33:A 0.000213288
3 *33:A out_n[0] 8.77498e-05
4 *33:A *39:A 0
*RES
1 in_s[0] *33:A 7.05
*END
*D_NET *16 0.00178446
*CONN
*P in_s[1] I
*I *39:A I *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 in_s[1] 0.000549895
2 *39:A 0.000549895
3 *39:A out_n[0] 0.000684666
4 *39:A out_n[2] 0
5 *39:A *40:A 0
6 *33:A *39:A 0
*RES
1 in_s[1] *39:A 15.075
*END
*D_NET *17 0.000663109
*CONN
*P in_s[2] I
*I *40:A I *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 in_s[2] 0.000331555
2 *40:A 0.000331555
3 *40:A out_s[0] 0
4 *39:A *40:A 0
*RES
1 in_s[2] *40:A 8.91
*END
*D_NET *18 0.00231172
*CONN
*P out_n[0] O
*I *33:X O *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 out_n[0] 0.000769652
2 *33:X 0.000769652
3 out_n[0] out_n[1] 0
4 out_n[0] out_n[2] 0
5 *33:A out_n[0] 8.77498e-05
6 *39:A out_n[0] 0.000684666
*RES
1 *33:X out_n[0] 19.095
*END
*D_NET *19 0.000816795
*CONN
*P out_n[1] O
*I *39:X O *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 out_n[1] 0.000285665
2 *39:X 0.000285665
3 out_n[1] out_n[2] 0.000245465
4 out_n[0] out_n[1] 0
*RES
1 *39:X out_n[1] 8.955
*END
*D_NET *20 0.00152863
*CONN
*P out_n[2] O
*I *40:X O *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 out_n[2] 0.000557907
2 *40:X 0.000557907
3 out_n[2] out_s[0] 0
4 out_n[0] out_n[2] 0
5 out_n[1] out_n[2] 0.000245465
6 *39:A out_n[2] 0
7 *41:A out_n[2] 0.000167353
*RES
1 *40:X out_n[2] 14.475
*END
*D_NET *21 0.00137998
*CONN
*P out_s[0] O
*I *41:X O *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 out_s[0] 0.000500863
2 *41:X 0.000500863
3 out_s[0] out_s[1] 0.000300724
4 out_s[0] out_s[2] 0
5 out_n[2] out_s[0] 0
6 *40:A out_s[0] 0
7 *42:A out_s[0] 7.75325e-05
8 *43:A out_s[0] 0
*RES
1 *41:X out_s[0] 15.21
*END
*D_NET *22 0.00187612
*CONN
*P out_s[10] O
*I *37:X O *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 out_s[10] 0.000913335
2 *37:X 0.000913335
3 out_s[10] out_s[11] 0
4 out_s[10] out_s[9] 0
5 *36:A out_s[10] 0
6 *37:A out_s[10] 4.94474e-05
7 *38:A out_s[10] 0
*RES
1 *37:X out_s[10] 17.595
*END
*D_NET *23 0.00239933
*CONN
*P out_s[11] O
*I *38:X O *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 out_s[11] 0.000947411
2 *38:X 0.000947411
3 out_s[11] out_s[9] 0.000123225
4 out_s[10] out_s[11] 0
5 *36:A out_s[11] 9.3521e-05
6 *38:A out_s[11] 0.000287765
*RES
1 *38:X out_s[11] 15.78
*END
*D_NET *24 0.00130092
*CONN
*P out_s[1] O
*I *42:X O *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 out_s[1] 0.000361344
2 *42:X 0.000361344
3 out_s[1] out_s[2] 0.000211976
4 out_s[1] out_s[3] 0
5 out_s[0] out_s[1] 0.000300724
6 *43:A out_s[1] 6.55328e-05
*RES
1 *42:X out_s[1] 12.165
*END
*D_NET *25 0.000903705
*CONN
*P out_s[2] O
*I *43:X O *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 out_s[2] 0.000342949
2 *43:X 0.000342949
3 out_s[2] out_s[3] 0
4 out_s[0] out_s[2] 0
5 out_s[1] out_s[2] 0.000211976
6 *43:A out_s[2] 5.83121e-06
*RES
1 *43:X out_s[2] 11.475
*END
*D_NET *26 0.00133229
*CONN
*P out_s[3] O
*I *44:X O *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 out_s[3] 0.000575568
2 *44:X 0.000575568
3 out_s[3] out_s[4] 0
4 out_s[3] out_s[5] 0
5 out_s[1] out_s[3] 0
6 out_s[2] out_s[3] 0
7 *45:A out_s[3] 0.000181152
*RES
1 *44:X out_s[3] 13.77
*END
*D_NET *27 0.00079736
*CONN
*P out_s[4] O
*I *45:X O *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 out_s[4] 0.000337866
2 *45:X 0.000337866
3 out_s[4] out_s[5] 0.000121628
4 out_s[3] out_s[4] 0
*RES
1 *45:X out_s[4] 9.9
*END
*D_NET *28 0.00105662
*CONN
*P out_s[5] O
*I *46:X O *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 out_s[5] 0.000467496
2 *46:X 0.000467496
3 out_s[5] out_s[6] 0
4 out_s[3] out_s[5] 0
5 out_s[4] out_s[5] 0.000121628
*RES
1 *46:X out_s[5] 11.475
*END
*D_NET *29 0.00170008
*CONN
*P out_s[6] O
*I *47:X O *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 out_s[6] 0.000724414
2 *47:X 0.000724414
3 out_s[6] out_s[7] 8.73036e-05
4 out_s[5] out_s[6] 0
5 *34:A out_s[6] 4.04613e-05
6 *47:A out_s[6] 0.00012349
*RES
1 *47:X out_s[6] 15.135
*END
*D_NET *30 0.00123387
*CONN
*P out_s[7] O
*I *34:X O *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 out_s[7] 0.000515339
2 *34:X 0.000515339
3 out_s[7] out_s[8] 0
4 out_s[6] out_s[7] 8.73036e-05
5 *34:A out_s[7] 0.000115886
*RES
1 *34:X out_s[7] 12.45
*END
*D_NET *31 0.00148373
*CONN
*P out_s[8] O
*I *35:X O *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 out_s[8] 0.000716184
2 *35:X 0.000716184
3 out_s[8] out_s[9] 4.55329e-05
4 out_s[7] out_s[8] 0
5 *34:A out_s[8] 0
6 *35:A out_s[8] 5.83121e-06
*RES
1 *35:X out_s[8] 15.015
*END
*D_NET *32 0.000550203
*CONN
*P out_s[9] O
*I *36:X O *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 out_s[9] 0.000129111
2 *36:X 0.000129111
3 out_s[10] out_s[9] 0
4 out_s[11] out_s[9] 0.000123225
5 out_s[8] out_s[9] 4.55329e-05
6 *38:A out_s[9] 0.000123225
*RES
1 *36:X out_s[9] 6.705
*END

587
signoff/buff_flash_clkrst/openlane-signoff/spef/buff_flash_clkrst.nom.spef Normal file
View File

@ -0,0 +1,587 @@
*SPEF "ieee 1481-1999"
*DESIGN "buff_flash_clkrst"
*DATE "11:11:11 Fri 11 11, 1111"
*VENDOR "OpenRCX"
*PROGRAM "Parallel Extraction"
*VERSION "1.0"
*DESIGN_FLOW "NAME_SCOPE LOCAL" "PIN_CAP NONE"
*DIVIDER /
*DELIMITER :
*BUS_DELIMITER []
*T_UNIT 1 NS
*C_UNIT 1 PF
*R_UNIT 1 OHM
*L_UNIT 1 HENRY
*NAME_MAP
*3 in_n[0]
*4 in_n[10]
*5 in_n[11]
*6 in_n[1]
*7 in_n[2]
*8 in_n[3]
*9 in_n[4]
*10 in_n[5]
*11 in_n[6]
*12 in_n[7]
*13 in_n[8]
*14 in_n[9]
*15 in_s[0]
*16 in_s[1]
*17 in_s[2]
*18 out_n[0]
*19 out_n[1]
*20 out_n[2]
*21 out_s[0]
*22 out_s[10]
*23 out_s[11]
*24 out_s[1]
*25 out_s[2]
*26 out_s[3]
*27 out_s[4]
*28 out_s[5]
*29 out_s[6]
*30 out_s[7]
*31 out_s[8]
*32 out_s[9]
*33 BUF\[0\]
*34 BUF\[10\]
*35 BUF\[11\]
*36 BUF\[12\]
*37 BUF\[13\]
*38 BUF\[14\]
*39 BUF\[1\]
*40 BUF\[2\]
*41 BUF\[3\]
*42 BUF\[4\]
*43 BUF\[5\]
*44 BUF\[6\]
*45 BUF\[7\]
*46 BUF\[8\]
*47 BUF\[9\]
*48 FILLER_0_19
*49 FILLER_0_27
*50 FILLER_0_29
*51 FILLER_0_3
*52 FILLER_0_41
*53 FILLER_0_54
*54 FILLER_0_57
*55 FILLER_0_7
*56 FILLER_0_70
*57 FILLER_0_74
*58 FILLER_1_17
*59 FILLER_1_3
*60 FILLER_1_32
*61 FILLER_1_47
*62 FILLER_1_55
*63 FILLER_1_57
*64 FILLER_1_70
*65 FILLER_1_74
*66 FILLER_2_26
*67 FILLER_2_29
*68 FILLER_2_3
*69 FILLER_2_52
*70 FILLER_2_67
*71 FILLER_3_15
*72 FILLER_3_27
*73 FILLER_3_3
*74 FILLER_3_42
*75 FILLER_3_54
*76 FILLER_3_57
*77 FILLER_3_70
*78 FILLER_3_74
*79 FILLER_4_19
*80 FILLER_4_27
*81 FILLER_4_29
*82 FILLER_4_3
*83 FILLER_4_41
*84 FILLER_4_53
*85 FILLER_4_57
*86 FILLER_4_7
*87 FILLER_4_70
*88 FILLER_4_74
*89 PHY_0
*90 PHY_1
*91 PHY_2
*92 PHY_3
*93 PHY_4
*94 PHY_5
*95 PHY_6
*96 PHY_7
*97 PHY_8
*98 PHY_9
*99 TAP_10
*100 TAP_11
*101 TAP_12
*102 TAP_13
*103 TAP_14
*104 TAP_15
*105 TAP_16
*PORTS
in_n[0] I
in_n[10] I
in_n[11] I
in_n[1] I
in_n[2] I
in_n[3] I
in_n[4] I
in_n[5] I
in_n[6] I
in_n[7] I
in_n[8] I
in_n[9] I
in_s[0] I
in_s[1] I
in_s[2] I
out_n[0] O
out_n[1] O
out_n[2] O
out_s[0] O
out_s[10] O
out_s[11] O
out_s[1] O
out_s[2] O
out_s[3] O
out_s[4] O
out_s[5] O
out_s[6] O
out_s[7] O
out_s[8] O
out_s[9] O
*D_NET *3 0.000746189
*CONN
*P in_n[0] I
*I *41:A I *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 in_n[0] 0.000291118
2 *41:A 0.000291118
3 *41:A out_n[2] 0.000163953
4 *41:A *42:A 0
*RES
1 in_n[0] *41:A 20.5321
*END
*D_NET *4 0.000540091
*CONN
*P in_n[10] I
*I *37:A I *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 in_n[10] 0.00024161
2 *37:A 0.00024161
3 *37:A out_s[10] 5.68722e-05
4 *37:A *36:A 0
5 *37:A *38:A 0
*RES
1 in_n[10] *37:A 18.55
*END
*D_NET *5 0.00290352
*CONN
*P in_n[11] I
*I *38:A I *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 in_n[11] 0.00113707
2 *38:A 0.00113707
3 *38:A out_s[10] 0
4 *38:A out_s[11] 0.000304969
5 *38:A out_s[9] 0.000140933
6 *38:A *36:A 0.000183477
7 *37:A *38:A 0
*RES
1 in_n[11] *38:A 36.925
*END
*D_NET *6 0.00134243
*CONN
*P in_n[1] I
*I *42:A I *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 in_n[1] 0.000293149
2 *42:A 0.000293149
3 *42:A out_s[0] 7.58571e-05
4 *42:A *43:A 0.000680277
5 *41:A *42:A 0
*RES
1 in_n[1] *42:A 22.7464
*END
*D_NET *7 0.00200548
*CONN
*P in_n[2] I
*I *43:A I *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 in_n[2] 0.000625829
2 *43:A 0.000625829
3 *43:A out_s[0] 0
4 *43:A out_s[1] 6.74911e-05
5 *43:A out_s[2] 6.05161e-06
6 *43:A *44:A 0
7 *42:A *43:A 0.000680277
*RES
1 in_n[2] *43:A 27.5679
*END
*D_NET *8 0.000719992
*CONN
*P in_n[3] I
*I *44:A I *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 in_n[3] 0.000359996
2 *44:A 0.000359996
3 *44:A *45:A 0
4 *43:A *44:A 0
*RES
1 in_n[3] *44:A 20.5321
*END
*D_NET *9 0.00131838
*CONN
*P in_n[4] I
*I *45:A I *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 in_n[4] 0.000565243
2 *45:A 0.000565243
3 *45:A out_s[3] 0.000187893
4 *45:A *46:A 0
5 *44:A *45:A 0
*RES
1 in_n[4] *45:A 25.3893
*END
*D_NET *10 0.00105711
*CONN
*P in_n[5] I
*I *46:A I *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 in_n[5] 0.000528554
2 *46:A 0.000528554
3 *45:A *46:A 0
*RES
1 in_n[5] *46:A 23.5679
*END
*D_NET *11 0.00171215
*CONN
*P in_n[6] I
*I *47:A I *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 in_n[6] 0.000448575
2 *47:A 0.000448575
3 *47:A out_s[6] 0.000141554
4 *47:A *34:A 0.000673444
*RES
1 in_n[6] *47:A 25.3357
*END
*D_NET *12 0.00184731
*CONN
*P in_n[7] I
*I *34:A I *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 in_n[7] 0.000505756
2 *34:A 0.000505756
3 *34:A out_s[6] 3.85148e-05
4 *34:A out_s[7] 0.000123836
5 *34:A out_s[8] 0
6 *34:A *35:A 0
7 *47:A *34:A 0.000673444
*RES
1 in_n[7] *34:A 26.2107
*END
*D_NET *13 0.00083737
*CONN
*P in_n[8] I
*I *35:A I *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 in_n[8] 0.000415659
2 *35:A 0.000415659
3 *35:A out_s[8] 6.05161e-06
4 *35:A *36:A 0
5 *34:A *35:A 0
*RES
1 in_n[8] *35:A 21.1929
*END
*D_NET *14 0.00191759
*CONN
*P in_n[9] I
*I *36:A I *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 in_n[9] 0.000817106
2 *36:A 0.000817106
3 *36:A out_s[10] 0
4 *36:A out_s[11] 9.98961e-05
5 *35:A *36:A 0
6 *37:A *36:A 0
7 *38:A *36:A 0.000183477
*RES
1 in_n[9] *36:A 29.3714
*END
*D_NET *15 0.000565776
*CONN
*P in_s[0] I
*I *33:A I *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 in_s[0] 0.000232546
2 *33:A 0.000232546
3 *33:A out_n[0] 0.000100684
4 *33:A *39:A 0
*RES
1 in_s[0] *33:A 17.9071
*END
*D_NET *16 0.00194543
*CONN
*P in_s[1] I
*I *39:A I *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 in_s[1] 0.000603696
2 *39:A 0.000603696
3 *39:A out_n[0] 0.000738039
4 *39:A out_n[2] 0
5 *39:A *40:A 0
6 *33:A *39:A 0
*RES
1 in_s[1] *39:A 27.4607
*END
*D_NET *17 0.000720944
*CONN
*P in_s[2] I
*I *40:A I *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 in_s[2] 0.000360472
2 *40:A 0.000360472
3 *40:A out_s[0] 0
4 *39:A *40:A 0
*RES
1 in_s[2] *40:A 20.1214
*END
*D_NET *18 0.00251314
*CONN
*P out_n[0] O
*I *33:X O *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 out_n[0] 0.00083721
2 *33:X 0.00083721
3 out_n[0] out_n[1] 0
4 out_n[0] out_n[2] 0
5 *33:A out_n[0] 0.000100684
6 *39:A out_n[0] 0.000738039
*RES
1 *33:X out_n[0] 32.2464
*END
*D_NET *19 0.0008921
*CONN
*P out_n[1] O
*I *39:X O *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 out_n[1] 0.000313512
2 *39:X 0.000313512
3 out_n[1] out_n[2] 0.000265077
4 out_n[0] out_n[1] 0
*RES
1 *39:X out_n[1] 20.175
*END
*D_NET *20 0.00165991
*CONN
*P out_n[2] O
*I *40:X O *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 out_n[2] 0.000615442
2 *40:X 0.000615442
3 out_n[2] out_s[0] 0
4 out_n[0] out_n[2] 0
5 out_n[1] out_n[2] 0.000265077
6 *39:A out_n[2] 0
7 *41:A out_n[2] 0.000163953
*RES
1 *40:X out_n[2] 26.7464
*END
*D_NET *21 0.00149166
*CONN
*P out_s[0] O
*I *41:X O *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 out_s[0] 0.000551682
2 *41:X 0.000551682
3 out_s[0] out_s[1] 0.000312442
4 out_s[0] out_s[2] 0
5 out_n[2] out_s[0] 0
6 *40:A out_s[0] 0
7 *42:A out_s[0] 7.58571e-05
8 *43:A out_s[0] 0
*RES
1 *41:X out_s[0] 27.6214
*END
*D_NET *22 0.00205685
*CONN
*P out_s[10] O
*I *37:X O *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 out_s[10] 0.000999988
2 *37:X 0.000999988
3 out_s[10] out_s[11] 0
4 out_s[10] out_s[9] 0
5 *36:A out_s[10] 0
6 *37:A out_s[10] 5.68722e-05
7 *38:A out_s[10] 0
*RES
1 *37:X out_s[10] 30.4607
*END
*D_NET *23 0.00269979
*CONN
*P out_s[11] O
*I *38:X O *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 out_s[11] 0.001077
2 *38:X 0.001077
3 out_s[11] out_s[9] 0.000140933
4 out_s[10] out_s[11] 0
5 *36:A out_s[11] 9.98961e-05
6 *38:A out_s[11] 0.000304969
*RES
1 *38:X out_s[11] 28.3
*END
*D_NET *24 0.00141598
*CONN
*P out_s[1] O
*I *42:X O *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 out_s[1] 0.000407902
2 *42:X 0.000407902
3 out_s[1] out_s[2] 0.000220246
4 out_s[1] out_s[3] 0
5 out_s[0] out_s[1] 0.000312442
6 *43:A out_s[1] 6.74911e-05
*RES
1 *42:X out_s[1] 23.9964
*END
*D_NET *25 0.000977116
*CONN
*P out_s[2] O
*I *43:X O *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 out_s[2] 0.000375409
2 *43:X 0.000375409
3 out_s[2] out_s[3] 0
4 out_s[0] out_s[2] 0
5 out_s[1] out_s[2] 0.000220246
6 *43:A out_s[2] 6.05161e-06
*RES
1 *43:X out_s[2] 23.175
*END
*D_NET *26 0.00144163
*CONN
*P out_s[3] O
*I *44:X O *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 out_s[3] 0.000626868
2 *44:X 0.000626868
3 out_s[3] out_s[4] 0
4 out_s[3] out_s[5] 0
5 out_s[1] out_s[3] 0
6 out_s[2] out_s[3] 0
7 *45:A out_s[3] 0.000187893
*RES
1 *44:X out_s[3] 25.9071
*END
*D_NET *27 0.000857812
*CONN
*P out_s[4] O
*I *45:X O *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 out_s[4] 0.00037039
2 *45:X 0.00037039
3 out_s[4] out_s[5] 0.000117033
4 out_s[3] out_s[4] 0
*RES
1 *45:X out_s[4] 21.3
*END
*D_NET *28 0.0011436
*CONN
*P out_s[5] O
*I *46:X O *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 out_s[5] 0.000513285
2 *46:X 0.000513285
3 out_s[5] out_s[6] 0
4 out_s[3] out_s[5] 0
5 out_s[4] out_s[5] 0.000117033
*RES
1 *46:X out_s[5] 23.175
*END
*D_NET *29 0.00186776
*CONN
*P out_s[6] O
*I *47:X O *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 out_s[6] 0.000801981
2 *47:X 0.000801981
3 out_s[6] out_s[7] 8.37335e-05
4 out_s[5] out_s[6] 0
5 *34:A out_s[6] 3.85148e-05
6 *47:A out_s[6] 0.000141554
*RES
1 *47:X out_s[6] 27.5321
*END
*D_NET *30 0.00134038
*CONN
*P out_s[7] O
*I *34:X O *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 out_s[7] 0.000566407
2 *34:X 0.000566407
3 out_s[7] out_s[8] 0
4 out_s[6] out_s[7] 8.37335e-05
5 *34:A out_s[7] 0.000123836
*RES
1 *34:X out_s[7] 24.3357
*END
*D_NET *31 0.00161835
*CONN
*P out_s[8] O
*I *35:X O *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 out_s[8] 0.000784339
2 *35:X 0.000784339
3 out_s[8] out_s[9] 4.36202e-05
4 out_s[7] out_s[8] 0
5 *34:A out_s[8] 0
6 *35:A out_s[8] 6.05161e-06
*RES
1 *35:X out_s[8] 27.3893
*END
*D_NET *32 0.000618171
*CONN
*P out_s[9] O
*I *36:X O *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 out_s[9] 0.000146343
2 *36:X 0.000146343
3 out_s[10] out_s[9] 0
4 out_s[11] out_s[9] 0.000140933
5 out_s[8] out_s[9] 4.36202e-05
6 *38:A out_s[9] 0.000140933
*RES
1 *36:X out_s[9] 17.4964
*END

587
spef/buff_flash_clkrst.spef Normal file
View File

@ -0,0 +1,587 @@
*SPEF "ieee 1481-1999"
*DESIGN "buff_flash_clkrst"
*DATE "11:11:11 Fri 11 11, 1111"
*VENDOR "OpenRCX"
*PROGRAM "Parallel Extraction"
*VERSION "1.0"
*DESIGN_FLOW "NAME_SCOPE LOCAL" "PIN_CAP NONE"
*DIVIDER /
*DELIMITER :
*BUS_DELIMITER []
*T_UNIT 1 NS
*C_UNIT 1 PF
*R_UNIT 1 OHM
*L_UNIT 1 HENRY
*NAME_MAP
*3 in_n[0]
*4 in_n[10]
*5 in_n[11]
*6 in_n[1]
*7 in_n[2]
*8 in_n[3]
*9 in_n[4]
*10 in_n[5]
*11 in_n[6]
*12 in_n[7]
*13 in_n[8]
*14 in_n[9]
*15 in_s[0]
*16 in_s[1]
*17 in_s[2]
*18 out_n[0]
*19 out_n[1]
*20 out_n[2]
*21 out_s[0]
*22 out_s[10]
*23 out_s[11]
*24 out_s[1]
*25 out_s[2]
*26 out_s[3]
*27 out_s[4]
*28 out_s[5]
*29 out_s[6]
*30 out_s[7]
*31 out_s[8]
*32 out_s[9]
*33 BUF\[0\]
*34 BUF\[10\]
*35 BUF\[11\]
*36 BUF\[12\]
*37 BUF\[13\]
*38 BUF\[14\]
*39 BUF\[1\]
*40 BUF\[2\]
*41 BUF\[3\]
*42 BUF\[4\]
*43 BUF\[5\]
*44 BUF\[6\]
*45 BUF\[7\]
*46 BUF\[8\]
*47 BUF\[9\]
*48 FILLER_0_19
*49 FILLER_0_27
*50 FILLER_0_29
*51 FILLER_0_3
*52 FILLER_0_41
*53 FILLER_0_54
*54 FILLER_0_57
*55 FILLER_0_7
*56 FILLER_0_70
*57 FILLER_0_74
*58 FILLER_1_17
*59 FILLER_1_3
*60 FILLER_1_32
*61 FILLER_1_47
*62 FILLER_1_55
*63 FILLER_1_57
*64 FILLER_1_70
*65 FILLER_1_74
*66 FILLER_2_26
*67 FILLER_2_29
*68 FILLER_2_3
*69 FILLER_2_52
*70 FILLER_2_67
*71 FILLER_3_15
*72 FILLER_3_27
*73 FILLER_3_3
*74 FILLER_3_42
*75 FILLER_3_54
*76 FILLER_3_57
*77 FILLER_3_70
*78 FILLER_3_74
*79 FILLER_4_19
*80 FILLER_4_27
*81 FILLER_4_29
*82 FILLER_4_3
*83 FILLER_4_41
*84 FILLER_4_53
*85 FILLER_4_57
*86 FILLER_4_7
*87 FILLER_4_70
*88 FILLER_4_74
*89 PHY_0
*90 PHY_1
*91 PHY_2
*92 PHY_3
*93 PHY_4
*94 PHY_5
*95 PHY_6
*96 PHY_7
*97 PHY_8
*98 PHY_9
*99 TAP_10
*100 TAP_11
*101 TAP_12
*102 TAP_13
*103 TAP_14
*104 TAP_15
*105 TAP_16
*PORTS
in_n[0] I
in_n[10] I
in_n[11] I
in_n[1] I
in_n[2] I
in_n[3] I
in_n[4] I
in_n[5] I
in_n[6] I
in_n[7] I
in_n[8] I
in_n[9] I
in_s[0] I
in_s[1] I
in_s[2] I
out_n[0] O
out_n[1] O
out_n[2] O
out_s[0] O
out_s[10] O
out_s[11] O
out_s[1] O
out_s[2] O
out_s[3] O
out_s[4] O
out_s[5] O
out_s[6] O
out_s[7] O
out_s[8] O
out_s[9] O
*D_NET *3 0.000746189
*CONN
*P in_n[0] I
*I *41:A I *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 in_n[0] 0.000291118
2 *41:A 0.000291118
3 *41:A out_n[2] 0.000163953
4 *41:A *42:A 0
*RES
1 in_n[0] *41:A 20.5321
*END
*D_NET *4 0.000540091
*CONN
*P in_n[10] I
*I *37:A I *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 in_n[10] 0.00024161
2 *37:A 0.00024161
3 *37:A out_s[10] 5.68722e-05
4 *37:A *36:A 0
5 *37:A *38:A 0
*RES
1 in_n[10] *37:A 18.55
*END
*D_NET *5 0.00290352
*CONN
*P in_n[11] I
*I *38:A I *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 in_n[11] 0.00113707
2 *38:A 0.00113707
3 *38:A out_s[10] 0
4 *38:A out_s[11] 0.000304969
5 *38:A out_s[9] 0.000140933
6 *38:A *36:A 0.000183477
7 *37:A *38:A 0
*RES
1 in_n[11] *38:A 36.925
*END
*D_NET *6 0.00134243
*CONN
*P in_n[1] I
*I *42:A I *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 in_n[1] 0.000293149
2 *42:A 0.000293149
3 *42:A out_s[0] 7.58571e-05
4 *42:A *43:A 0.000680277
5 *41:A *42:A 0
*RES
1 in_n[1] *42:A 22.7464
*END
*D_NET *7 0.00200548
*CONN
*P in_n[2] I
*I *43:A I *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 in_n[2] 0.000625829
2 *43:A 0.000625829
3 *43:A out_s[0] 0
4 *43:A out_s[1] 6.74911e-05
5 *43:A out_s[2] 6.05161e-06
6 *43:A *44:A 0
7 *42:A *43:A 0.000680277
*RES
1 in_n[2] *43:A 27.5679
*END
*D_NET *8 0.000719992
*CONN
*P in_n[3] I
*I *44:A I *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 in_n[3] 0.000359996
2 *44:A 0.000359996
3 *44:A *45:A 0
4 *43:A *44:A 0
*RES
1 in_n[3] *44:A 20.5321
*END
*D_NET *9 0.00131838
*CONN
*P in_n[4] I
*I *45:A I *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 in_n[4] 0.000565243
2 *45:A 0.000565243
3 *45:A out_s[3] 0.000187893
4 *45:A *46:A 0
5 *44:A *45:A 0
*RES
1 in_n[4] *45:A 25.3893
*END
*D_NET *10 0.00105711
*CONN
*P in_n[5] I
*I *46:A I *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 in_n[5] 0.000528554
2 *46:A 0.000528554
3 *45:A *46:A 0
*RES
1 in_n[5] *46:A 23.5679
*END
*D_NET *11 0.00171215
*CONN
*P in_n[6] I
*I *47:A I *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 in_n[6] 0.000448575
2 *47:A 0.000448575
3 *47:A out_s[6] 0.000141554
4 *47:A *34:A 0.000673444
*RES
1 in_n[6] *47:A 25.3357
*END
*D_NET *12 0.00184731
*CONN
*P in_n[7] I
*I *34:A I *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 in_n[7] 0.000505756
2 *34:A 0.000505756
3 *34:A out_s[6] 3.85148e-05
4 *34:A out_s[7] 0.000123836
5 *34:A out_s[8] 0
6 *34:A *35:A 0
7 *47:A *34:A 0.000673444
*RES
1 in_n[7] *34:A 26.2107
*END
*D_NET *13 0.00083737
*CONN
*P in_n[8] I
*I *35:A I *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 in_n[8] 0.000415659
2 *35:A 0.000415659
3 *35:A out_s[8] 6.05161e-06
4 *35:A *36:A 0
5 *34:A *35:A 0
*RES
1 in_n[8] *35:A 21.1929
*END
*D_NET *14 0.00191759
*CONN
*P in_n[9] I
*I *36:A I *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 in_n[9] 0.000817106
2 *36:A 0.000817106
3 *36:A out_s[10] 0
4 *36:A out_s[11] 9.98961e-05
5 *35:A *36:A 0
6 *37:A *36:A 0
7 *38:A *36:A 0.000183477
*RES
1 in_n[9] *36:A 29.3714
*END
*D_NET *15 0.000565776
*CONN
*P in_s[0] I
*I *33:A I *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 in_s[0] 0.000232546
2 *33:A 0.000232546
3 *33:A out_n[0] 0.000100684
4 *33:A *39:A 0
*RES
1 in_s[0] *33:A 17.9071
*END
*D_NET *16 0.00194543
*CONN
*P in_s[1] I
*I *39:A I *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 in_s[1] 0.000603696
2 *39:A 0.000603696
3 *39:A out_n[0] 0.000738039
4 *39:A out_n[2] 0
5 *39:A *40:A 0
6 *33:A *39:A 0
*RES
1 in_s[1] *39:A 27.4607
*END
*D_NET *17 0.000720944
*CONN
*P in_s[2] I
*I *40:A I *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 in_s[2] 0.000360472
2 *40:A 0.000360472
3 *40:A out_s[0] 0
4 *39:A *40:A 0
*RES
1 in_s[2] *40:A 20.1214
*END
*D_NET *18 0.00251314
*CONN
*P out_n[0] O
*I *33:X O *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 out_n[0] 0.00083721
2 *33:X 0.00083721
3 out_n[0] out_n[1] 0
4 out_n[0] out_n[2] 0
5 *33:A out_n[0] 0.000100684
6 *39:A out_n[0] 0.000738039
*RES
1 *33:X out_n[0] 32.2464
*END
*D_NET *19 0.0008921
*CONN
*P out_n[1] O
*I *39:X O *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 out_n[1] 0.000313512
2 *39:X 0.000313512
3 out_n[1] out_n[2] 0.000265077
4 out_n[0] out_n[1] 0
*RES
1 *39:X out_n[1] 20.175
*END
*D_NET *20 0.00165991
*CONN
*P out_n[2] O
*I *40:X O *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 out_n[2] 0.000615442
2 *40:X 0.000615442
3 out_n[2] out_s[0] 0
4 out_n[0] out_n[2] 0
5 out_n[1] out_n[2] 0.000265077
6 *39:A out_n[2] 0
7 *41:A out_n[2] 0.000163953
*RES
1 *40:X out_n[2] 26.7464
*END
*D_NET *21 0.00149166
*CONN
*P out_s[0] O
*I *41:X O *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 out_s[0] 0.000551682
2 *41:X 0.000551682
3 out_s[0] out_s[1] 0.000312442
4 out_s[0] out_s[2] 0
5 out_n[2] out_s[0] 0
6 *40:A out_s[0] 0
7 *42:A out_s[0] 7.58571e-05
8 *43:A out_s[0] 0
*RES
1 *41:X out_s[0] 27.6214
*END
*D_NET *22 0.00205685
*CONN
*P out_s[10] O
*I *37:X O *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 out_s[10] 0.000999988
2 *37:X 0.000999988
3 out_s[10] out_s[11] 0
4 out_s[10] out_s[9] 0
5 *36:A out_s[10] 0
6 *37:A out_s[10] 5.68722e-05
7 *38:A out_s[10] 0
*RES
1 *37:X out_s[10] 30.4607
*END
*D_NET *23 0.00269979
*CONN
*P out_s[11] O
*I *38:X O *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 out_s[11] 0.001077
2 *38:X 0.001077
3 out_s[11] out_s[9] 0.000140933
4 out_s[10] out_s[11] 0
5 *36:A out_s[11] 9.98961e-05
6 *38:A out_s[11] 0.000304969
*RES
1 *38:X out_s[11] 28.3
*END
*D_NET *24 0.00141598
*CONN
*P out_s[1] O
*I *42:X O *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 out_s[1] 0.000407902
2 *42:X 0.000407902
3 out_s[1] out_s[2] 0.000220246
4 out_s[1] out_s[3] 0
5 out_s[0] out_s[1] 0.000312442
6 *43:A out_s[1] 6.74911e-05
*RES
1 *42:X out_s[1] 23.9964
*END
*D_NET *25 0.000977116
*CONN
*P out_s[2] O
*I *43:X O *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 out_s[2] 0.000375409
2 *43:X 0.000375409
3 out_s[2] out_s[3] 0
4 out_s[0] out_s[2] 0
5 out_s[1] out_s[2] 0.000220246
6 *43:A out_s[2] 6.05161e-06
*RES
1 *43:X out_s[2] 23.175
*END
*D_NET *26 0.00144163
*CONN
*P out_s[3] O
*I *44:X O *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 out_s[3] 0.000626868
2 *44:X 0.000626868
3 out_s[3] out_s[4] 0
4 out_s[3] out_s[5] 0
5 out_s[1] out_s[3] 0
6 out_s[2] out_s[3] 0
7 *45:A out_s[3] 0.000187893
*RES
1 *44:X out_s[3] 25.9071
*END
*D_NET *27 0.000857812
*CONN
*P out_s[4] O
*I *45:X O *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 out_s[4] 0.00037039
2 *45:X 0.00037039
3 out_s[4] out_s[5] 0.000117033
4 out_s[3] out_s[4] 0
*RES
1 *45:X out_s[4] 21.3
*END
*D_NET *28 0.0011436
*CONN
*P out_s[5] O
*I *46:X O *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 out_s[5] 0.000513285
2 *46:X 0.000513285
3 out_s[5] out_s[6] 0
4 out_s[3] out_s[5] 0
5 out_s[4] out_s[5] 0.000117033
*RES
1 *46:X out_s[5] 23.175
*END
*D_NET *29 0.00186776
*CONN
*P out_s[6] O
*I *47:X O *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 out_s[6] 0.000801981
2 *47:X 0.000801981
3 out_s[6] out_s[7] 8.37335e-05
4 out_s[5] out_s[6] 0
5 *34:A out_s[6] 3.85148e-05
6 *47:A out_s[6] 0.000141554
*RES
1 *47:X out_s[6] 27.5321
*END
*D_NET *30 0.00134038
*CONN
*P out_s[7] O
*I *34:X O *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 out_s[7] 0.000566407
2 *34:X 0.000566407
3 out_s[7] out_s[8] 0
4 out_s[6] out_s[7] 8.37335e-05
5 *34:A out_s[7] 0.000123836
*RES
1 *34:X out_s[7] 24.3357
*END
*D_NET *31 0.00161835
*CONN
*P out_s[8] O
*I *35:X O *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 out_s[8] 0.000784339
2 *35:X 0.000784339
3 out_s[8] out_s[9] 4.36202e-05
4 out_s[7] out_s[8] 0
5 *34:A out_s[8] 0
6 *35:A out_s[8] 6.05161e-06
*RES
1 *35:X out_s[8] 27.3893
*END
*D_NET *32 0.000618171
*CONN
*P out_s[9] O
*I *36:X O *D sky130_fd_sc_hd__clkbuf_8
*CAP
1 out_s[9] 0.000146343
2 *36:X 0.000146343
3 out_s[10] out_s[9] 0
4 out_s[11] out_s[9] 0.000140933
5 out_s[8] out_s[9] 4.36202e-05
6 *38:A out_s[9] 0.000140933
*RES
1 *36:X out_s[9] 17.4964
*END

101
verilog/gl/buff_flash_clkrst.nl.v Normal file
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@ -0,0 +1,101 @@
// This is the unpowered netlist.
module buff_flash_clkrst (in_n,
in_s,
out_n,
out_s);
input [11:0] in_n;
input [2:0] in_s;
output [2:0] out_n;
output [11:0] out_s;
sky130_fd_sc_hd__clkbuf_8 \BUF[0] (.A(in_s[0]),
.X(out_n[0]));
sky130_fd_sc_hd__clkbuf_8 \BUF[10] (.A(in_n[7]),
.X(out_s[7]));
sky130_fd_sc_hd__clkbuf_8 \BUF[11] (.A(in_n[8]),
.X(out_s[8]));
sky130_fd_sc_hd__clkbuf_8 \BUF[12] (.A(in_n[9]),
.X(out_s[9]));
sky130_fd_sc_hd__clkbuf_8 \BUF[13] (.A(in_n[10]),
.X(out_s[10]));
sky130_fd_sc_hd__clkbuf_8 \BUF[14] (.A(in_n[11]),
.X(out_s[11]));
sky130_fd_sc_hd__clkbuf_8 \BUF[1] (.A(in_s[1]),
.X(out_n[1]));
sky130_fd_sc_hd__clkbuf_8 \BUF[2] (.A(in_s[2]),
.X(out_n[2]));
sky130_fd_sc_hd__clkbuf_8 \BUF[3] (.A(in_n[0]),
.X(out_s[0]));
sky130_fd_sc_hd__clkbuf_8 \BUF[4] (.A(in_n[1]),
.X(out_s[1]));
sky130_fd_sc_hd__clkbuf_8 \BUF[5] (.A(in_n[2]),
.X(out_s[2]));
sky130_fd_sc_hd__clkbuf_8 \BUF[6] (.A(in_n[3]),
.X(out_s[3]));
sky130_fd_sc_hd__clkbuf_8 \BUF[7] (.A(in_n[4]),
.X(out_s[4]));
sky130_fd_sc_hd__clkbuf_8 \BUF[8] (.A(in_n[5]),
.X(out_s[5]));
sky130_fd_sc_hd__clkbuf_8 \BUF[9] (.A(in_n[6]),
.X(out_s[6]));
sky130_fd_sc_hd__decap_3 PHY_0 ();
sky130_fd_sc_hd__decap_3 PHY_1 ();
sky130_fd_sc_hd__decap_3 PHY_2 ();
sky130_fd_sc_hd__decap_3 PHY_3 ();
sky130_fd_sc_hd__decap_3 PHY_4 ();
sky130_fd_sc_hd__decap_3 PHY_5 ();
sky130_fd_sc_hd__decap_3 PHY_6 ();
sky130_fd_sc_hd__decap_3 PHY_7 ();
sky130_fd_sc_hd__decap_3 PHY_8 ();
sky130_fd_sc_hd__decap_3 PHY_9 ();
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_10 ();
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_11 ();
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_12 ();
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_13 ();
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_14 ();
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_15 ();
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_16 ();
sky130_fd_sc_hd__decap_4 FILLER_0_3 ();
sky130_fd_sc_hd__fill_1 FILLER_0_7 ();
sky130_fd_sc_hd__decap_8 FILLER_0_19 ();
sky130_fd_sc_hd__fill_1 FILLER_0_27 ();
sky130_ef_sc_hd__decap_12 FILLER_0_29 ();
sky130_fd_sc_hd__fill_2 FILLER_0_41 ();
sky130_fd_sc_hd__fill_2 FILLER_0_54 ();
sky130_fd_sc_hd__fill_2 FILLER_0_57 ();
sky130_fd_sc_hd__decap_4 FILLER_0_70 ();
sky130_fd_sc_hd__fill_1 FILLER_0_74 ();
sky130_fd_sc_hd__decap_3 FILLER_1_3 ();
sky130_fd_sc_hd__decap_4 FILLER_1_17 ();
sky130_fd_sc_hd__decap_4 FILLER_1_32 ();
sky130_fd_sc_hd__decap_8 FILLER_1_47 ();
sky130_fd_sc_hd__fill_1 FILLER_1_55 ();
sky130_fd_sc_hd__fill_2 FILLER_1_57 ();
sky130_fd_sc_hd__decap_4 FILLER_1_70 ();
sky130_fd_sc_hd__fill_1 FILLER_1_74 ();
sky130_ef_sc_hd__decap_12 FILLER_2_3 ();
sky130_fd_sc_hd__fill_2 FILLER_2_26 ();
sky130_ef_sc_hd__decap_12 FILLER_2_29 ();
sky130_fd_sc_hd__decap_4 FILLER_2_52 ();
sky130_fd_sc_hd__decap_8 FILLER_2_67 ();
sky130_ef_sc_hd__decap_12 FILLER_3_3 ();
sky130_fd_sc_hd__fill_1 FILLER_3_15 ();
sky130_fd_sc_hd__decap_4 FILLER_3_27 ();
sky130_ef_sc_hd__decap_12 FILLER_3_42 ();
sky130_fd_sc_hd__fill_2 FILLER_3_54 ();
sky130_fd_sc_hd__fill_2 FILLER_3_57 ();
sky130_fd_sc_hd__decap_4 FILLER_3_70 ();
sky130_fd_sc_hd__fill_1 FILLER_3_74 ();
sky130_fd_sc_hd__decap_4 FILLER_4_3 ();
sky130_fd_sc_hd__fill_1 FILLER_4_7 ();
sky130_fd_sc_hd__decap_8 FILLER_4_19 ();
sky130_fd_sc_hd__fill_1 FILLER_4_27 ();
sky130_ef_sc_hd__decap_12 FILLER_4_29 ();
sky130_ef_sc_hd__decap_12 FILLER_4_41 ();
sky130_fd_sc_hd__decap_3 FILLER_4_53 ();
sky130_fd_sc_hd__fill_2 FILLER_4_57 ();
sky130_fd_sc_hd__decap_4 FILLER_4_70 ();
sky130_fd_sc_hd__fill_1 FILLER_4_74 ();
endmodule

323
verilog/gl/buff_flash_clkrst.v Normal file
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@ -0,0 +1,323 @@
module buff_flash_clkrst (VPWR,
VGND,
in_n,
in_s,
out_n,
out_s);
input VPWR;
input VGND;
input [11:0] in_n;
input [2:0] in_s;
output [2:0] out_n;
output [11:0] out_s;
sky130_fd_sc_hd__clkbuf_8 \BUF[0] (.A(in_s[0]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(out_n[0]));
sky130_fd_sc_hd__clkbuf_8 \BUF[10] (.A(in_n[7]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(out_s[7]));
sky130_fd_sc_hd__clkbuf_8 \BUF[11] (.A(in_n[8]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(out_s[8]));
sky130_fd_sc_hd__clkbuf_8 \BUF[12] (.A(in_n[9]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(out_s[9]));
sky130_fd_sc_hd__clkbuf_8 \BUF[13] (.A(in_n[10]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(out_s[10]));
sky130_fd_sc_hd__clkbuf_8 \BUF[14] (.A(in_n[11]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(out_s[11]));
sky130_fd_sc_hd__clkbuf_8 \BUF[1] (.A(in_s[1]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(out_n[1]));
sky130_fd_sc_hd__clkbuf_8 \BUF[2] (.A(in_s[2]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(out_n[2]));
sky130_fd_sc_hd__clkbuf_8 \BUF[3] (.A(in_n[0]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(out_s[0]));
sky130_fd_sc_hd__clkbuf_8 \BUF[4] (.A(in_n[1]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(out_s[1]));
sky130_fd_sc_hd__clkbuf_8 \BUF[5] (.A(in_n[2]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(out_s[2]));
sky130_fd_sc_hd__clkbuf_8 \BUF[6] (.A(in_n[3]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(out_s[3]));
sky130_fd_sc_hd__clkbuf_8 \BUF[7] (.A(in_n[4]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(out_s[4]));
sky130_fd_sc_hd__clkbuf_8 \BUF[8] (.A(in_n[5]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(out_s[5]));
sky130_fd_sc_hd__clkbuf_8 \BUF[9] (.A(in_n[6]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR),
.X(out_s[6]));
sky130_fd_sc_hd__decap_3 PHY_0 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_1 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_2 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_3 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_4 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_5 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_6 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_7 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_8 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_9 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_10 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_11 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_12 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_13 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_14 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_15 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_16 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_4 FILLER_0_3 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__fill_1 FILLER_0_7 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_8 FILLER_0_19 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__fill_1 FILLER_0_27 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_ef_sc_hd__decap_12 FILLER_0_29 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__fill_2 FILLER_0_41 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__fill_2 FILLER_0_54 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__fill_2 FILLER_0_57 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_4 FILLER_0_70 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__fill_1 FILLER_0_74 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 FILLER_1_3 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_4 FILLER_1_17 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_4 FILLER_1_32 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_8 FILLER_1_47 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__fill_1 FILLER_1_55 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__fill_2 FILLER_1_57 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_4 FILLER_1_70 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__fill_1 FILLER_1_74 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_ef_sc_hd__decap_12 FILLER_2_3 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__fill_2 FILLER_2_26 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_ef_sc_hd__decap_12 FILLER_2_29 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_4 FILLER_2_52 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_8 FILLER_2_67 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_ef_sc_hd__decap_12 FILLER_3_3 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__fill_1 FILLER_3_15 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_4 FILLER_3_27 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_ef_sc_hd__decap_12 FILLER_3_42 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__fill_2 FILLER_3_54 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__fill_2 FILLER_3_57 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_4 FILLER_3_70 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__fill_1 FILLER_3_74 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_4 FILLER_4_3 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__fill_1 FILLER_4_7 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_8 FILLER_4_19 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__fill_1 FILLER_4_27 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_ef_sc_hd__decap_12 FILLER_4_29 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_ef_sc_hd__decap_12 FILLER_4_41 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 FILLER_4_53 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__fill_2 FILLER_4_57 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_4 FILLER_4_70 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__fill_1 FILLER_4_74 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
endmodule

5
verilog/rtl/buff_flash_clkrst.v Normal file
View File

@ -0,0 +1,5 @@
module buff_flash_clkrst (input[11:0] in_n, input[2:0] in_s, output[11:0] out_s, output[2:0] out_n);
sky130_fd_sc_hd__clkbuf_8 BUF[14:0] (.A({in_n, in_s}), .X({out_s, out_n}) );
endmodule