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[DATA] Update gpio_control_block pin order to fix shorts at the top level

This commit is contained in:
manarabdelaty 2021-11-19 13:13:24 +02:00
parent 581a22de6a
commit bf6ad67934
8 changed files with 9354 additions and 9669 deletions
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BIN
gds/gpio_control_block.gds.gz
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Binary file not shown.

12
lef/gpio_control_block.lef
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@ -116,7 +116,7 @@ MACRO gpio_control_block
USE SIGNAL ;
PORT
LAYER met3 ;
RECT 70.000 6.160 170.000 6.760 ;
RECT 70.000 4.120 170.000 4.720 ;
END
END mgmt_gpio_in
PIN mgmt_gpio_oeb
@ -140,7 +140,7 @@ MACRO gpio_control_block
USE SIGNAL ;
PORT
LAYER met3 ;
RECT 70.000 4.120 170.000 4.720 ;
RECT 70.000 6.160 170.000 6.760 ;
END
END one
PIN pad_gpio_ana_en
@ -455,9 +455,9 @@ MACRO gpio_control_block
LAYER li1 ;
RECT 3.825 5.355 49.995 57.205 ;
LAYER met1 ;
RECT 3.750 4.120 110.790 59.800 ;
RECT 3.765 5.200 107.110 60.820 ;
LAYER met2 ;
RECT 3.780 60.720 4.410 61.725 ;
RECT 4.230 60.720 4.410 61.725 ;
RECT 5.250 60.720 6.710 61.725 ;
RECT 7.550 60.720 9.010 61.725 ;
RECT 9.850 60.720 11.310 61.725 ;
@ -470,8 +470,8 @@ MACRO gpio_control_block
RECT 25.950 60.720 27.410 61.725 ;
RECT 28.250 60.720 29.710 61.725 ;
RECT 30.550 60.720 32.010 61.725 ;
RECT 32.850 60.720 110.770 61.725 ;
RECT 3.780 2.195 110.770 60.720 ;
RECT 32.850 60.720 107.090 61.725 ;
RECT 4.230 2.195 107.090 60.720 ;
LAYER met3 ;
RECT 4.205 58.160 70.000 58.305 ;
RECT 4.205 56.760 69.600 58.160 ;

18848
mag/gpio_control_block.mag
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File diff suppressed because it is too large Load Diff

4
openlane/gpio_control_block/io_place.tcl
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@ -63,8 +63,8 @@ set_io_pin_constraint -pin_names {pad_gpio_ana_pol} -region right:14-16
set_io_pin_constraint -pin_names {pad_gpio_ana_en} -region right:12-14
set_io_pin_constraint -pin_names {mgmt_gpio_out} -region right:10-12
set_io_pin_constraint -pin_names {mgmt_gpio_oeb} -region right:8-10
set_io_pin_constraint -pin_names {mgmt_gpio_in} -region right:6-8
set_io_pin_constraint -pin_names {one} -region right:4-6
set_io_pin_constraint -pin_names {one} -region right:6-8
set_io_pin_constraint -pin_names {mgmt_gpio_in} -region right:4-6
set_io_pin_constraint -pin_names {zero} -region right:2-4
# North pins

2
signoff/gpio_control_block/OPENLANE_VERSION
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@ -1 +1 @@
openlane 2021.09.09_03.00.48-53-g97579eb
openlane 2021.09.09_03.00.48-66-gbdb1b56

9
signoff/gpio_control_block/PDK_SOURCES
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@ -1,6 +1,3 @@
-ne openlane
e6ba5d36a9b32a9f87626d49bf3c80cf3964ebeb
-ne skywater-pdk
c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
-ne open_pdks
f90a86bdd133bd629251d59eebb1aee8452c0f5c
openlane cbb562bd43c5c410b1b498604803c3dd88a44856
skywater-pdk c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
open_pdks c5730b574461889c82858b08d12ba42423d9c2cb

2
signoff/gpio_control_block/final_summary_report.csv
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@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
0,/project/openlane/gpio_control_block,gpio_control_block,gpio_control_block,flow_completed,0h2m41s,-1,22624.434389140275,0.01105,11312.217194570138,70.3,514.11,125,0,0,0,0,0,0,0,0,0,-1,-1,6876,1332,0.0,0.0,-1,0.0,-1,0.0,0.0,-1,0.0,-1,3826992.0,0.0,16.75,22.73,14.82,-1,17.94,81,109,48,76,0,0,0,66,0,0,0,0,0,0,0,4,24,44,4,38,28,0,66,19.607843137254903,51,50,AREA 0,5,50,1,15.5,16.9,0.91,0.05,sky130_fd_sc_hd,0,4
0,/home/ma/ef/caravel_openframe/openlane/gpio_control_block,gpio_control_block,gpio_control_block,flow_completed,0h2m38s,-1,22624.434389140275,0.01105,11312.217194570138,70.3,516.54,125,0,0,0,0,0,0,0,0,0,-1,-1,6835,1291,0.0,0.0,-1,0.0,-1,0.0,0.0,-1,0.0,-1,3826095.0,0.0,14.52,23.35,16.53,-1,17.72,81,109,48,76,0,0,0,66,0,0,0,0,0,0,0,4,24,44,4,38,28,0,66,19.607843137254903,51,50,AREA 0,5,50,1,15.5,16.9,0.91,0.05,sky130_fd_sc_hd,0,4

1 design design_name config flow_status total_runtime routed_runtime (Cell/mm^2)/Core_Util DIEAREA_mm^2 CellPer_mm^2 OpenDP_Util Peak_Memory_Usage_MB cell_count tritonRoute_violations Short_violations MetSpc_violations OffGrid_violations MinHole_violations Other_violations Magic_violations antenna_violations lvs_total_errors cvc_total_errors klayout_violations wire_length vias wns pl_wns optimized_wns fastroute_wns spef_wns tns pl_tns optimized_tns fastroute_tns spef_tns HPWL routing_layer1_pct routing_layer2_pct routing_layer3_pct routing_layer4_pct routing_layer5_pct routing_layer6_pct wires_count wire_bits public_wires_count public_wire_bits memories_count memory_bits processes_count cells_pre_abc AND DFF NAND NOR OR XOR XNOR MUX inputs outputs level EndCaps TapCells Diodes Total_Physical_Cells suggested_clock_frequency suggested_clock_period CLOCK_PERIOD SYNTH_STRATEGY SYNTH_MAX_FANOUT FP_CORE_UTIL FP_ASPECT_RATIO FP_PDN_VPITCH FP_PDN_HPITCH PL_TARGET_DENSITY GLB_RT_ADJUSTMENT STD_CELL_LIBRARY CELL_PAD DIODE_INSERTION_STRATEGY
2 0 /project/openlane/gpio_control_block /home/ma/ef/caravel_openframe/openlane/gpio_control_block gpio_control_block gpio_control_block flow_completed 0h2m41s 0h2m38s -1 22624.434389140275 0.01105 11312.217194570138 70.3 514.11 516.54 125 0 0 0 0 0 0 0 0 0 -1 -1 6876 6835 1332 1291 0.0 0.0 -1 0.0 -1 0.0 0.0 -1 0.0 -1 3826992.0 3826095.0 0.0 16.75 14.52 22.73 23.35 14.82 16.53 -1 17.94 17.72 81 109 48 76 0 0 0 66 0 0 0 0 0 0 0 4 24 44 4 38 28 0 66 19.607843137254903 51 50 AREA 0 5 50 1 15.5 16.9 0.91 0.05 sky130_fd_sc_hd 0 4

146
verilog/gl/gpio_control_block.v
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@ -387,11 +387,11 @@ module gpio_control_block (mgmt_gpio_in,
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__decap_8 FILLER_0_42 (.VGND(vssd),
sky130_fd_sc_hd__decap_8 FILLER_0_41 (.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__fill_1 FILLER_0_50 (.VGND(vssd),
sky130_fd_sc_hd__fill_2 FILLER_0_49 (.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
@ -399,27 +399,15 @@ module gpio_control_block (mgmt_gpio_in,
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__decap_8 FILLER_0_64 (.VGND(vssd),
sky130_fd_sc_hd__decap_12 FILLER_0_64 (.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__decap_3 FILLER_0_72 (.VGND(vssd),
sky130_fd_sc_hd__decap_3 FILLER_0_76 (.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__fill_1 FILLER_0_83 (.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__fill_1 FILLER_0_93 (.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__fill_2 FILLER_10_3 (.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__fill_2 FILLER_11_16 (.VGND(vssd),
sky130_fd_sc_hd__fill_1 FILLER_0_90 (.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
@ -427,11 +415,11 @@ module gpio_control_block (mgmt_gpio_in,
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__fill_1 FILLER_11_93 (.VGND(vssd),
sky130_fd_sc_hd__fill_1 FILLER_11_83 (.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__fill_1 FILLER_12_37 (.VGND(vssd),
sky130_fd_sc_hd__fill_1 FILLER_11_93 (.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
@ -447,10 +435,6 @@ module gpio_control_block (mgmt_gpio_in,
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__fill_1 FILLER_14_19 (.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__fill_1 FILLER_14_3 (.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
@ -459,15 +443,23 @@ module gpio_control_block (mgmt_gpio_in,
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__fill_1 FILLER_15_45 (.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__fill_1 FILLER_16_29 (.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__fill_1 FILLER_17_27 (.VGND(vssd),
sky130_fd_sc_hd__fill_2 FILLER_16_3 (.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__fill_2 FILLER_17_49 (.VGND(vssd),
sky130_fd_sc_hd__fill_1 FILLER_17_3 (.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__fill_1 FILLER_17_30 (.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
@ -479,11 +471,15 @@ module gpio_control_block (mgmt_gpio_in,
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__fill_2 FILLER_18_46 (.VGND(vssd),
sky130_fd_sc_hd__fill_1 FILLER_18_34 (.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__fill_1 FILLER_18_57 (.VGND(vssd),
sky130_fd_sc_hd__fill_1 FILLER_18_41 (.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__fill_1 FILLER_18_63 (.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
@ -499,23 +495,35 @@ module gpio_control_block (mgmt_gpio_in,
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__decap_8 FILLER_1_65 (.VGND(vssd),
sky130_fd_sc_hd__decap_8 FILLER_1_62 (.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__fill_1 FILLER_1_89 (.VGND(vssd),
sky130_fd_sc_hd__fill_1 FILLER_1_70 (.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__fill_1 FILLER_2_63 (.VGND(vssd),
sky130_fd_sc_hd__fill_1 FILLER_1_80 (.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__fill_1 FILLER_3_35 (.VGND(vssd),
sky130_fd_sc_hd__fill_1 FILLER_2_46 (.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__fill_2 FILLER_3_62 (.VGND(vssd),
sky130_fd_sc_hd__fill_1 FILLER_2_50 (.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__fill_2 FILLER_2_61 (.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__fill_1 FILLER_3_63 (.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__fill_2 FILLER_3_77 (.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
@ -531,6 +539,10 @@ module gpio_control_block (mgmt_gpio_in,
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__fill_1 FILLER_5_55 (.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__fill_1 FILLER_5_93 (.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
@ -547,19 +559,7 @@ module gpio_control_block (mgmt_gpio_in,
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__fill_1 FILLER_6_93 (.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__fill_1 FILLER_7_46 (.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__fill_2 FILLER_7_92 (.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__fill_2 FILLER_8_3 (.VGND(vssd),
sky130_fd_sc_hd__fill_2 FILLER_7_46 (.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
@ -567,7 +567,7 @@ module gpio_control_block (mgmt_gpio_in,
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__fill_1 FILLER_8_57 (.VGND(vssd),
sky130_fd_sc_hd__fill_1 FILLER_8_63 (.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
@ -579,14 +579,6 @@ module gpio_control_block (mgmt_gpio_in,
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__fill_1 FILLER_9_44 (.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__fill_1 FILLER_9_63 (.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__decap_3 PHY_0 (.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
@ -1434,7 +1426,7 @@ module gpio_control_block (mgmt_gpio_in,
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__dfbbn_1 _198_ (.D(net56),
sky130_fd_sc_hd__dfbbn_1 _198_ (.D(net55),
.Q(mgmt_ena),
.Q_N(_090_),
.RESET_B(_006_),
@ -1444,7 +1436,7 @@ module gpio_control_block (mgmt_gpio_in,
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__dfbbn_1 _199_ (.D(net55),
sky130_fd_sc_hd__dfbbn_1 _199_ (.D(net56),
.Q(net28),
.Q_N(_091_),
.RESET_B(_009_),
@ -1464,7 +1456,7 @@ module gpio_control_block (mgmt_gpio_in,
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__dfbbn_1 _201_ (.D(net46),
sky130_fd_sc_hd__dfbbn_1 _201_ (.D(net45),
.Q(net34),
.Q_N(_093_),
.RESET_B(_015_),
@ -1484,7 +1476,7 @@ module gpio_control_block (mgmt_gpio_in,
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__dfbbn_1 _203_ (.D(net45),
sky130_fd_sc_hd__dfbbn_1 _203_ (.D(net46),
.Q(net29),
.Q_N(_095_),
.RESET_B(_021_),
@ -1494,7 +1486,7 @@ module gpio_control_block (mgmt_gpio_in,
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__dfbbn_1 _204_ (.D(net63),
sky130_fd_sc_hd__dfbbn_1 _204_ (.D(net62),
.Q(gpio_outenb),
.Q_N(_096_),
.RESET_B(_024_),
@ -1504,7 +1496,7 @@ module gpio_control_block (mgmt_gpio_in,
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__dfbbn_1 _205_ (.D(net52),
sky130_fd_sc_hd__dfbbn_1 _205_ (.D(net53),
.Q(net25),
.Q_N(_001_),
.RESET_B(_027_),
@ -1524,7 +1516,7 @@ module gpio_control_block (mgmt_gpio_in,
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__dfbbn_1 _207_ (.D(net62),
sky130_fd_sc_hd__dfbbn_1 _207_ (.D(net63),
.Q(net27),
.Q_N(_098_),
.RESET_B(_033_),
@ -1534,7 +1526,7 @@ module gpio_control_block (mgmt_gpio_in,
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__dfbbn_1 _208_ (.D(net66),
sky130_fd_sc_hd__dfbbn_1 _208_ (.D(net52),
.Q(net22),
.Q_N(_099_),
.RESET_B(_036_),
@ -1544,7 +1536,7 @@ module gpio_control_block (mgmt_gpio_in,
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__dfbbn_1 _209_ (.D(net57),
sky130_fd_sc_hd__dfbbn_1 _209_ (.D(net59),
.Q(net24),
.Q_N(_100_),
.RESET_B(_039_),
@ -1652,7 +1644,7 @@ module gpio_control_block (mgmt_gpio_in,
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__dfrtp_1 _222_ (.D(net65),
sky130_fd_sc_hd__dfrtp_1 _222_ (.D(\shift_register[10] ),
.Q(\shift_register[11] ),
.RESET_B(net17),
.CLK(clknet_1_0_0_serial_clock),
@ -1714,37 +1706,37 @@ module gpio_control_block (mgmt_gpio_in,
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__clkdlybuf4s25_1 hold11 (.A(\shift_register[2] ),
sky130_fd_sc_hd__clkdlybuf4s25_1 hold11 (.A(\shift_register[0] ),
.X(net55),
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__clkdlybuf4s25_1 hold12 (.A(\shift_register[0] ),
sky130_fd_sc_hd__clkdlybuf4s25_1 hold12 (.A(\shift_register[2] ),
.X(net56),
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__clkdlybuf4s25_1 hold13 (.A(\shift_register[6] ),
sky130_fd_sc_hd__clkdlybuf4s25_1 hold13 (.A(\shift_register[4] ),
.X(net57),
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__clkdlybuf4s25_1 hold14 (.A(\shift_register[4] ),
sky130_fd_sc_hd__clkdlybuf4s25_1 hold14 (.A(\shift_register[9] ),
.X(net58),
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__clkdlybuf4s25_1 hold15 (.A(\shift_register[8] ),
sky130_fd_sc_hd__clkdlybuf4s25_1 hold15 (.A(\shift_register[6] ),
.X(net59),
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__clkdlybuf4s25_1 hold16 (.A(\shift_register[9] ),
sky130_fd_sc_hd__clkdlybuf4s25_1 hold16 (.A(\shift_register[8] ),
.X(net60),
.VGND(vssd),
.VNB(vssd),
@ -1756,19 +1748,19 @@ module gpio_control_block (mgmt_gpio_in,
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__clkdlybuf4s25_1 hold18 (.A(net50),
sky130_fd_sc_hd__clkdlybuf4s25_1 hold18 (.A(net49),
.X(net62),
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__clkdlybuf4s25_1 hold19 (.A(net49),
sky130_fd_sc_hd__clkdlybuf4s25_1 hold19 (.A(net50),
.X(net63),
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__clkdlybuf4s25_1 hold2 (.A(net60),
sky130_fd_sc_hd__clkdlybuf4s25_1 hold2 (.A(net57),
.X(net46),
.VGND(vssd),
.VNB(vssd),
@ -1780,19 +1772,19 @@ module gpio_control_block (mgmt_gpio_in,
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__clkdlybuf4s50_1 hold21 (.A(\shift_register[10] ),
sky130_fd_sc_hd__clkdlybuf4s25_1 hold21 (.A(\shift_register[5] ),
.X(net65),
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__clkdlybuf4s25_1 hold22 (.A(net53),
sky130_fd_sc_hd__clkdlybuf4s25_1 hold22 (.A(\shift_register[10] ),
.X(net66),
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__clkdlybuf4s25_1 hold3 (.A(net59),
sky130_fd_sc_hd__clkdlybuf4s25_1 hold3 (.A(net60),
.X(net47),
.VGND(vssd),
.VNB(vssd),
@ -1828,7 +1820,7 @@ module gpio_control_block (mgmt_gpio_in,
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__clkdlybuf4s25_1 hold9 (.A(\shift_register[5] ),
sky130_fd_sc_hd__clkdlybuf4s25_1 hold9 (.A(net66),
.X(net53),
.VGND(vssd),
.VNB(vssd),