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Add gpio_defaults_block views

This commit is contained in:
manarabdelaty 2021-11-05 12:33:36 +02:00
parent 78ce7265c1
commit 53b09f43d1
12 changed files with 2300 additions and 0 deletions
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291
def/gpio_defaults_block.def Normal file
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VERSION 5.8 ;
DIVIDERCHAR "/" ;
BUSBITCHARS "[]" ;
DESIGN gpio_defaults_block ;
UNITS DISTANCE MICRONS 1000 ;
DIEAREA ( 0 0 ) ( 25000 11000 ) ;
ROW ROW_0 unithd 0 2720 N DO 54 BY 1 STEP 460 0 ;
ROW ROW_1 unithd 0 5440 FS DO 54 BY 1 STEP 460 0 ;
ROW ROW_2 unithd 0 8160 N DO 54 BY 1 STEP 460 0 ;
TRACKS X 230 DO 54 STEP 460 LAYER li1 ;
TRACKS Y 170 DO 32 STEP 340 LAYER li1 ;
TRACKS X 170 DO 74 STEP 340 LAYER met1 ;
TRACKS Y 170 DO 32 STEP 340 LAYER met1 ;
TRACKS X 230 DO 54 STEP 460 LAYER met2 ;
TRACKS Y 230 DO 24 STEP 460 LAYER met2 ;
TRACKS X 340 DO 37 STEP 680 LAYER met3 ;
TRACKS Y 340 DO 16 STEP 680 LAYER met3 ;
TRACKS X 460 DO 27 STEP 920 LAYER met4 ;
TRACKS Y 460 DO 12 STEP 920 LAYER met4 ;
TRACKS X 1700 DO 7 STEP 3400 LAYER met5 ;
TRACKS Y 1700 DO 3 STEP 3400 LAYER met5 ;
GCELLGRID X 0 DO 3 STEP 6900 ;
GCELLGRID Y 0 DO 2 STEP 6900 ;
VIAS 4 ;
- via4_1400x1600 + VIARULE M4M5_PR + CUTSIZE 800 800 + LAYERS met4 via4 met5 + CUTSPACING 800 800 + ENCLOSURE 300 400 310 400 ;
- via_1400x480 + VIARULE M1M2_PR + CUTSIZE 150 150 + LAYERS met1 via met2 + CUTSPACING 170 170 + ENCLOSURE 145 165 55 165 + ROWCOL 1 4 ;
- via2_1400x480 + VIARULE M2M3_PR + CUTSIZE 200 200 + LAYERS met2 via2 met3 + CUTSPACING 200 200 + ENCLOSURE 40 140 200 65 + ROWCOL 1 3 ;
- via3_1400x480 + VIARULE M3M4_PR + CUTSIZE 200 200 + LAYERS met3 via3 met4 + CUTSPACING 200 200 + ENCLOSURE 200 60 200 140 + ROWCOL 1 3 ;
END VIAS
COMPONENTS 38 ;
- FILLER_0_26 sky130_fd_sc_hd__fill_2 + PLACED ( 11960 2720 ) N ;
- FILLER_0_3 sky130_fd_sc_hd__decap_4 + PLACED ( 1380 2720 ) N ;
- FILLER_0_38 sky130_fd_sc_hd__fill_2 + PLACED ( 17480 2720 ) N ;
- FILLER_0_49 sky130_fd_sc_hd__fill_2 + PLACED ( 22540 2720 ) N ;
- FILLER_0_7 sky130_fd_sc_hd__fill_1 + PLACED ( 3220 2720 ) N ;
- FILLER_1_15 sky130_fd_sc_hd__decap_12 + PLACED ( 6900 5440 ) FS ;
- FILLER_1_27 sky130_fd_sc_hd__decap_8 + PLACED ( 12420 5440 ) FS ;
- FILLER_1_3 sky130_fd_sc_hd__decap_12 + PLACED ( 1380 5440 ) FS ;
- FILLER_1_35 sky130_fd_sc_hd__fill_2 + PLACED ( 16100 5440 ) FS ;
- FILLER_1_40 sky130_fd_sc_hd__decap_8 + PLACED ( 18400 5440 ) FS ;
- FILLER_1_48 sky130_fd_sc_hd__decap_3 + PLACED ( 22080 5440 ) FS ;
- FILLER_2_15 sky130_fd_sc_hd__decap_12 + PLACED ( 6900 8160 ) N ;
- FILLER_2_27 sky130_fd_sc_hd__fill_1 + PLACED ( 12420 8160 ) N ;
- FILLER_2_29 sky130_fd_sc_hd__decap_12 + PLACED ( 13340 8160 ) N ;
- FILLER_2_3 sky130_fd_sc_hd__decap_12 + PLACED ( 1380 8160 ) N ;
- FILLER_2_41 sky130_fd_sc_hd__decap_8 + PLACED ( 18860 8160 ) N ;
- FILLER_2_49 sky130_fd_sc_hd__fill_2 + PLACED ( 22540 8160 ) N ;
- PHY_0 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 0 2720 ) N ;
- PHY_1 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 23460 2720 ) FN ;
- PHY_2 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 0 5440 ) FS ;
- PHY_3 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 23460 5440 ) S ;
- PHY_4 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 0 8160 ) N ;
- PHY_5 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 23460 8160 ) FN ;
- TAP_6 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 12880 2720 ) N ;
- TAP_7 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 12880 8160 ) N ;
- gpio_default_value\[0\] sky130_fd_sc_hd__conb_1 + PLACED ( 3680 2720 ) FN ;
- gpio_default_value\[10\] sky130_fd_sc_hd__conb_1 + PLACED ( 19780 2720 ) N ;
- gpio_default_value\[11\] sky130_fd_sc_hd__conb_1 + PLACED ( 21160 2720 ) FN ;
- gpio_default_value\[12\] sky130_fd_sc_hd__conb_1 + PLACED ( 18400 2720 ) N ;
- gpio_default_value\[1\] sky130_fd_sc_hd__conb_1 + PLACED ( 5060 2720 ) N ;
- gpio_default_value\[2\] sky130_fd_sc_hd__conb_1 + PLACED ( 6440 2720 ) FN ;
- gpio_default_value\[3\] sky130_fd_sc_hd__conb_1 + PLACED ( 7820 2720 ) FN ;
- gpio_default_value\[4\] sky130_fd_sc_hd__conb_1 + PLACED ( 9200 2720 ) FN ;
- gpio_default_value\[5\] sky130_fd_sc_hd__conb_1 + PLACED ( 10580 2720 ) FN ;
- gpio_default_value\[6\] sky130_fd_sc_hd__conb_1 + PLACED ( 13340 2720 ) FN ;
- gpio_default_value\[7\] sky130_fd_sc_hd__conb_1 + PLACED ( 14720 2720 ) FN ;
- gpio_default_value\[8\] sky130_fd_sc_hd__conb_1 + PLACED ( 16100 2720 ) FN ;
- gpio_default_value\[9\] sky130_fd_sc_hd__conb_1 + PLACED ( 17020 5440 ) FS ;
END COMPONENTS
PINS 15 ;
- VGND + NET VGND + SPECIAL + DIRECTION INPUT + USE GROUND
+ PORT
+ LAYER met4 ( -700 -4320 ) ( 700 4320 )
+ LAYER met4 ( -7700 -4320 ) ( -6300 4320 )
+ LAYER met4 ( -14700 -4320 ) ( -13300 4320 )
+ LAYER met5 ( -18500 380 ) ( 6340 1980 )
+ FIXED ( 18500 6800 ) N ;
- VPWR + NET VPWR + SPECIAL + DIRECTION INPUT + USE POWER
+ PORT
+ LAYER met4 ( -700 -4320 ) ( 700 4320 )
+ LAYER met4 ( -7700 -4320 ) ( -6300 4320 )
+ LAYER met4 ( -14700 -4320 ) ( -13300 4320 )
+ LAYER met4 ( -21700 -4320 ) ( -20300 4320 )
+ LAYER met5 ( -22000 -3120 ) ( 2840 -1520 )
+ FIXED ( 22000 6800 ) N ;
- gpio_defaults[0] + NET gpio_defaults_low\[0\] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER met2 ( -140 -1000 ) ( 140 1000 )
+ PLACED ( 1150 1000 ) N ;
- gpio_defaults[10] + NET gpio_defaults_high\[10\] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER met2 ( -140 -1000 ) ( 140 1000 )
+ PLACED ( 20010 1000 ) N ;
- gpio_defaults[11] + NET gpio_defaults_low\[11\] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER met2 ( -140 -1000 ) ( 140 1000 )
+ PLACED ( 21850 1000 ) N ;
- gpio_defaults[12] + NET gpio_defaults_low\[12\] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER met2 ( -140 -1000 ) ( 140 1000 )
+ PLACED ( 23690 1000 ) N ;
- gpio_defaults[1] + NET gpio_defaults_high\[1\] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER met2 ( -140 -1000 ) ( 140 1000 )
+ PLACED ( 2990 1000 ) N ;
- gpio_defaults[2] + NET gpio_defaults_low\[2\] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER met2 ( -140 -1000 ) ( 140 1000 )
+ PLACED ( 4830 1000 ) N ;
- gpio_defaults[3] + NET gpio_defaults_low\[3\] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER met2 ( -140 -1000 ) ( 140 1000 )
+ PLACED ( 6670 1000 ) N ;
- gpio_defaults[4] + NET gpio_defaults_low\[4\] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER met2 ( -140 -1000 ) ( 140 1000 )
+ PLACED ( 8510 1000 ) N ;
- gpio_defaults[5] + NET gpio_defaults_low\[5\] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER met2 ( -140 -1000 ) ( 140 1000 )
+ PLACED ( 10350 1000 ) N ;
- gpio_defaults[6] + NET gpio_defaults_low\[6\] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER met2 ( -140 -1000 ) ( 140 1000 )
+ PLACED ( 12190 1000 ) N ;
- gpio_defaults[7] + NET gpio_defaults_low\[7\] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER met2 ( -140 -1000 ) ( 140 1000 )
+ PLACED ( 14490 1000 ) N ;
- gpio_defaults[8] + NET gpio_defaults_low\[8\] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER met2 ( -140 -1000 ) ( 140 1000 )
+ PLACED ( 16330 1000 ) N ;
- gpio_defaults[9] + NET gpio_defaults_low\[9\] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER met2 ( -140 -1000 ) ( 140 1000 )
+ PLACED ( 18170 1000 ) N ;
END PINS
BLOCKAGES 1 ;
- LAYER met5 RECT ( 0 0 ) ( 25000 11000 ) ;
END BLOCKAGES
SPECIALNETS 2 ;
- VGND ( PIN VGND ) ( * VNB ) ( * VGND ) + USE GROUND
+ ROUTED met3 0 + SHAPE STRIPE ( 18500 8160 ) via3_1400x480
NEW met2 0 + SHAPE STRIPE ( 18500 8160 ) via2_1400x480
NEW met1 0 + SHAPE STRIPE ( 18500 8160 ) via_1400x480
NEW met3 0 + SHAPE STRIPE ( 11500 8160 ) via3_1400x480
NEW met2 0 + SHAPE STRIPE ( 11500 8160 ) via2_1400x480
NEW met1 0 + SHAPE STRIPE ( 11500 8160 ) via_1400x480
NEW met3 0 + SHAPE STRIPE ( 4500 8160 ) via3_1400x480
NEW met2 0 + SHAPE STRIPE ( 4500 8160 ) via2_1400x480
NEW met1 0 + SHAPE STRIPE ( 4500 8160 ) via_1400x480
NEW met3 0 + SHAPE STRIPE ( 18500 2720 ) via3_1400x480
NEW met2 0 + SHAPE STRIPE ( 18500 2720 ) via2_1400x480
NEW met1 0 + SHAPE STRIPE ( 18500 2720 ) via_1400x480
NEW met3 0 + SHAPE STRIPE ( 11500 2720 ) via3_1400x480
NEW met2 0 + SHAPE STRIPE ( 11500 2720 ) via2_1400x480
NEW met1 0 + SHAPE STRIPE ( 11500 2720 ) via_1400x480
NEW met3 0 + SHAPE STRIPE ( 4500 2720 ) via3_1400x480
NEW met2 0 + SHAPE STRIPE ( 4500 2720 ) via2_1400x480
NEW met1 0 + SHAPE STRIPE ( 4500 2720 ) via_1400x480
NEW met4 0 + SHAPE STRIPE ( 18500 7980 ) via4_1400x1600
NEW met4 0 + SHAPE STRIPE ( 11500 7980 ) via4_1400x1600
NEW met4 0 + SHAPE STRIPE ( 4500 7980 ) via4_1400x1600
NEW met5 1600 + SHAPE STRIPE ( 0 7980 ) ( 24840 7980 )
NEW met4 1400 + SHAPE STRIPE ( 18500 2480 ) ( 18500 11120 )
NEW met4 1400 + SHAPE STRIPE ( 11500 2480 ) ( 11500 11120 )
NEW met4 1400 + SHAPE STRIPE ( 4500 2480 ) ( 4500 11120 )
NEW met1 480 + SHAPE FOLLOWPIN ( 0 8160 ) ( 24840 8160 )
NEW met1 480 + SHAPE FOLLOWPIN ( 0 2720 ) ( 24840 2720 ) ;
- VPWR ( PIN VPWR ) ( * VPB ) ( * VPWR ) + USE POWER
+ ROUTED met3 0 + SHAPE STRIPE ( 22000 10880 ) via3_1400x480
NEW met2 0 + SHAPE STRIPE ( 22000 10880 ) via2_1400x480
NEW met1 0 + SHAPE STRIPE ( 22000 10880 ) via_1400x480
NEW met3 0 + SHAPE STRIPE ( 15000 10880 ) via3_1400x480
NEW met2 0 + SHAPE STRIPE ( 15000 10880 ) via2_1400x480
NEW met1 0 + SHAPE STRIPE ( 15000 10880 ) via_1400x480
NEW met3 0 + SHAPE STRIPE ( 8000 10880 ) via3_1400x480
NEW met2 0 + SHAPE STRIPE ( 8000 10880 ) via2_1400x480
NEW met1 0 + SHAPE STRIPE ( 8000 10880 ) via_1400x480
NEW met3 0 + SHAPE STRIPE ( 1000 10880 ) via3_1400x480
NEW met2 0 + SHAPE STRIPE ( 1000 10880 ) via2_1400x480
NEW met1 0 + SHAPE STRIPE ( 1000 10880 ) via_1400x480
NEW met3 0 + SHAPE STRIPE ( 22000 5440 ) via3_1400x480
NEW met2 0 + SHAPE STRIPE ( 22000 5440 ) via2_1400x480
NEW met1 0 + SHAPE STRIPE ( 22000 5440 ) via_1400x480
NEW met3 0 + SHAPE STRIPE ( 15000 5440 ) via3_1400x480
NEW met2 0 + SHAPE STRIPE ( 15000 5440 ) via2_1400x480
NEW met1 0 + SHAPE STRIPE ( 15000 5440 ) via_1400x480
NEW met3 0 + SHAPE STRIPE ( 8000 5440 ) via3_1400x480
NEW met2 0 + SHAPE STRIPE ( 8000 5440 ) via2_1400x480
NEW met1 0 + SHAPE STRIPE ( 8000 5440 ) via_1400x480
NEW met3 0 + SHAPE STRIPE ( 1000 5440 ) via3_1400x480
NEW met2 0 + SHAPE STRIPE ( 1000 5440 ) via2_1400x480
NEW met1 0 + SHAPE STRIPE ( 1000 5440 ) via_1400x480
NEW met4 0 + SHAPE STRIPE ( 22000 4480 ) via4_1400x1600
NEW met4 0 + SHAPE STRIPE ( 15000 4480 ) via4_1400x1600
NEW met4 0 + SHAPE STRIPE ( 8000 4480 ) via4_1400x1600
NEW met4 0 + SHAPE STRIPE ( 1000 4480 ) via4_1400x1600
NEW met5 1600 + SHAPE STRIPE ( 0 4480 ) ( 24840 4480 )
NEW met4 1400 + SHAPE STRIPE ( 22000 2480 ) ( 22000 11120 )
NEW met4 1400 + SHAPE STRIPE ( 15000 2480 ) ( 15000 11120 )
NEW met4 1400 + SHAPE STRIPE ( 8000 2480 ) ( 8000 11120 )
NEW met4 1400 + SHAPE STRIPE ( 1000 2480 ) ( 1000 11120 )
NEW met1 480 + SHAPE FOLLOWPIN ( 0 10880 ) ( 24840 10880 )
NEW met1 480 + SHAPE FOLLOWPIN ( 0 5440 ) ( 24840 5440 ) ;
END SPECIALNETS
NETS 26 ;
- gpio_defaults_high\[0\] ( gpio_default_value\[0\] HI ) + USE SIGNAL ;
- gpio_defaults_high\[10\] ( PIN gpio_defaults[10] ) ( gpio_default_value\[10\] HI ) + USE SIGNAL
+ ROUTED met2 ( 20010 1700 0 ) ( * 3230 )
NEW li1 ( 20010 3230 ) L1M1_PR_MR
NEW met1 ( 20010 3230 ) M1M2_PR
NEW met1 ( 20010 3230 ) RECT ( -355 -70 0 70 ) ;
- gpio_defaults_high\[11\] ( gpio_default_value\[11\] HI ) + USE SIGNAL ;
- gpio_defaults_high\[12\] ( gpio_default_value\[12\] HI ) + USE SIGNAL ;
- gpio_defaults_high\[1\] ( PIN gpio_defaults[1] ) ( gpio_default_value\[1\] HI ) + USE SIGNAL
+ ROUTED met2 ( 2990 1700 0 ) ( * 3230 )
NEW met1 ( 2990 3230 ) ( 5290 * )
NEW met1 ( 2990 3230 ) M1M2_PR
NEW li1 ( 5290 3230 ) L1M1_PR_MR ;
- gpio_defaults_high\[2\] ( gpio_default_value\[2\] HI ) + USE SIGNAL ;
- gpio_defaults_high\[3\] ( gpio_default_value\[3\] HI ) + USE SIGNAL ;
- gpio_defaults_high\[4\] ( gpio_default_value\[4\] HI ) + USE SIGNAL ;
- gpio_defaults_high\[5\] ( gpio_default_value\[5\] HI ) + USE SIGNAL ;
- gpio_defaults_high\[6\] ( gpio_default_value\[6\] HI ) + USE SIGNAL ;
- gpio_defaults_high\[7\] ( gpio_default_value\[7\] HI ) + USE SIGNAL ;
- gpio_defaults_high\[8\] ( gpio_default_value\[8\] HI ) + USE SIGNAL ;
- gpio_defaults_high\[9\] ( gpio_default_value\[9\] HI ) + USE SIGNAL ;
- gpio_defaults_low\[0\] ( PIN gpio_defaults[0] ) ( gpio_default_value\[0\] LO ) + USE SIGNAL
+ ROUTED met2 ( 1150 1700 0 ) ( * 3910 )
NEW met1 ( 1150 3910 ) ( 3910 * )
NEW met1 ( 1150 3910 ) M1M2_PR
NEW li1 ( 3910 3910 ) L1M1_PR_MR ;
- gpio_defaults_low\[10\] ( gpio_default_value\[10\] LO ) + USE SIGNAL ;
- gpio_defaults_low\[11\] ( PIN gpio_defaults[11] ) ( gpio_default_value\[11\] LO ) + USE SIGNAL
+ ROUTED met2 ( 21850 1700 0 ) ( * 3910 )
NEW met1 ( 21390 3910 ) ( 21850 * )
NEW met1 ( 21850 3910 ) M1M2_PR
NEW li1 ( 21390 3910 ) L1M1_PR_MR ;
- gpio_defaults_low\[12\] ( PIN gpio_defaults[12] ) ( gpio_default_value\[12\] LO ) + USE SIGNAL
+ ROUTED met2 ( 23690 1700 0 ) ( * 4250 )
NEW met1 ( 19550 4250 ) ( 23690 * )
NEW met1 ( 23690 4250 ) M1M2_PR
NEW li1 ( 19550 4250 ) L1M1_PR_MR ;
- gpio_defaults_low\[1\] ( gpio_default_value\[1\] LO ) + USE SIGNAL ;
- gpio_defaults_low\[2\] ( PIN gpio_defaults[2] ) ( gpio_default_value\[2\] LO ) + USE SIGNAL
+ ROUTED met2 ( 4830 1700 0 ) ( 5750 * )
NEW met2 ( 5750 1700 ) ( * 3910 )
NEW met1 ( 5750 3910 ) ( 6670 * )
NEW met1 ( 5750 3910 ) M1M2_PR
NEW li1 ( 6670 3910 ) L1M1_PR_MR ;
- gpio_defaults_low\[3\] ( PIN gpio_defaults[3] ) ( gpio_default_value\[3\] LO ) + USE SIGNAL
+ ROUTED met2 ( 6670 1700 0 ) ( * 4590 )
NEW met1 ( 6670 4590 ) ( 8050 * )
NEW met1 ( 6670 4590 ) M1M2_PR
NEW li1 ( 8050 4590 ) L1M1_PR_MR ;
- gpio_defaults_low\[4\] ( PIN gpio_defaults[4] ) ( gpio_default_value\[4\] LO ) + USE SIGNAL
+ ROUTED met2 ( 8510 1700 0 ) ( * 3910 )
NEW met1 ( 8510 3910 ) ( 9430 * )
NEW met1 ( 8510 3910 ) M1M2_PR
NEW li1 ( 9430 3910 ) L1M1_PR_MR ;
- gpio_defaults_low\[5\] ( PIN gpio_defaults[5] ) ( gpio_default_value\[5\] LO ) + USE SIGNAL
+ ROUTED met2 ( 10350 1700 0 ) ( * 3910 )
NEW met1 ( 10350 3910 ) ( 10810 * )
NEW met1 ( 10350 3910 ) M1M2_PR
NEW li1 ( 10810 3910 ) L1M1_PR_MR ;
- gpio_defaults_low\[6\] ( PIN gpio_defaults[6] ) ( gpio_default_value\[6\] LO ) + USE SIGNAL
+ ROUTED met2 ( 12190 1700 0 ) ( 13570 * )
NEW met2 ( 13570 1700 ) ( * 3910 )
NEW li1 ( 13570 3910 ) L1M1_PR_MR
NEW met1 ( 13570 3910 ) M1M2_PR
NEW met1 ( 13570 3910 ) RECT ( -355 -70 0 70 ) ;
- gpio_defaults_low\[7\] ( PIN gpio_defaults[7] ) ( gpio_default_value\[7\] LO ) + USE SIGNAL
+ ROUTED met2 ( 14490 1700 0 ) ( * 3910 )
NEW met1 ( 14490 3910 ) ( 14950 * )
NEW met1 ( 14490 3910 ) M1M2_PR
NEW li1 ( 14950 3910 ) L1M1_PR_MR ;
- gpio_defaults_low\[8\] ( PIN gpio_defaults[8] ) ( gpio_default_value\[8\] LO ) + USE SIGNAL
+ ROUTED met2 ( 16330 1700 0 ) ( * 3910 )
NEW li1 ( 16330 3910 ) L1M1_PR_MR
NEW met1 ( 16330 3910 ) M1M2_PR
NEW met1 ( 16330 3910 ) RECT ( -355 -70 0 70 ) ;
- gpio_defaults_low\[9\] ( PIN gpio_defaults[9] ) ( gpio_default_value\[9\] LO ) + USE SIGNAL
+ ROUTED met2 ( 17250 1700 ) ( 18170 * 0 )
NEW met2 ( 17250 1700 ) ( * 5950 )
NEW met1 ( 17250 5950 ) ( 18170 * )
NEW met1 ( 17250 5950 ) M1M2_PR
NEW li1 ( 18170 5950 ) L1M1_PR_MR ;
END NETS
END DESIGN

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gds/gpio_defaults_block.gds.gz Normal file
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VERSION 5.7 ;
NOWIREEXTENSIONATPIN ON ;
DIVIDERCHAR "/" ;
BUSBITCHARS "[]" ;
MACRO gpio_defaults_block
CLASS BLOCK ;
FOREIGN gpio_defaults_block ;
ORIGIN 0.000 0.000 ;
SIZE 25.000 BY 11.000 ;
PIN VGND
DIRECTION INPUT ;
USE GROUND ;
PORT
LAYER met5 ;
RECT 0.000 7.180 24.840 8.780 ;
END
PORT
LAYER met4 ;
RECT 3.800 2.480 5.200 11.120 ;
END
PORT
LAYER met4 ;
RECT 10.800 2.480 12.200 11.120 ;
END
PORT
LAYER met4 ;
RECT 17.800 2.480 19.200 11.120 ;
END
END VGND
PIN VPWR
DIRECTION INPUT ;
USE POWER ;
PORT
LAYER met5 ;
RECT 0.000 3.680 24.840 5.280 ;
END
PORT
LAYER met4 ;
RECT 0.300 2.480 1.700 11.120 ;
END
PORT
LAYER met4 ;
RECT 7.300 2.480 8.700 11.120 ;
END
PORT
LAYER met4 ;
RECT 14.300 2.480 15.700 11.120 ;
END
PORT
LAYER met4 ;
RECT 21.300 2.480 22.700 11.120 ;
END
END VPWR
PIN gpio_defaults[0]
DIRECTION OUTPUT TRISTATE ;
USE SIGNAL ;
PORT
LAYER met2 ;
RECT 1.010 0.000 1.290 2.000 ;
END
END gpio_defaults[0]
PIN gpio_defaults[10]
DIRECTION OUTPUT TRISTATE ;
USE SIGNAL ;
PORT
LAYER met2 ;
RECT 19.870 0.000 20.150 2.000 ;
END
END gpio_defaults[10]
PIN gpio_defaults[11]
DIRECTION OUTPUT TRISTATE ;
USE SIGNAL ;
PORT
LAYER met2 ;
RECT 21.710 0.000 21.990 2.000 ;
END
END gpio_defaults[11]
PIN gpio_defaults[12]
DIRECTION OUTPUT TRISTATE ;
USE SIGNAL ;
PORT
LAYER met2 ;
RECT 23.550 0.000 23.830 2.000 ;
END
END gpio_defaults[12]
PIN gpio_defaults[1]
DIRECTION OUTPUT TRISTATE ;
USE SIGNAL ;
PORT
LAYER met2 ;
RECT 2.850 0.000 3.130 2.000 ;
END
END gpio_defaults[1]
PIN gpio_defaults[2]
DIRECTION OUTPUT TRISTATE ;
USE SIGNAL ;
PORT
LAYER met2 ;
RECT 4.690 0.000 4.970 2.000 ;
END
END gpio_defaults[2]
PIN gpio_defaults[3]
DIRECTION OUTPUT TRISTATE ;
USE SIGNAL ;
PORT
LAYER met2 ;
RECT 6.530 0.000 6.810 2.000 ;
END
END gpio_defaults[3]
PIN gpio_defaults[4]
DIRECTION OUTPUT TRISTATE ;
USE SIGNAL ;
PORT
LAYER met2 ;
RECT 8.370 0.000 8.650 2.000 ;
END
END gpio_defaults[4]
PIN gpio_defaults[5]
DIRECTION OUTPUT TRISTATE ;
USE SIGNAL ;
PORT
LAYER met2 ;
RECT 10.210 0.000 10.490 2.000 ;
END
END gpio_defaults[5]
PIN gpio_defaults[6]
DIRECTION OUTPUT TRISTATE ;
USE SIGNAL ;
PORT
LAYER met2 ;
RECT 12.050 0.000 12.330 2.000 ;
END
END gpio_defaults[6]
PIN gpio_defaults[7]
DIRECTION OUTPUT TRISTATE ;
USE SIGNAL ;
PORT
LAYER met2 ;
RECT 14.350 0.000 14.630 2.000 ;
END
END gpio_defaults[7]
PIN gpio_defaults[8]
DIRECTION OUTPUT TRISTATE ;
USE SIGNAL ;
PORT
LAYER met2 ;
RECT 16.190 0.000 16.470 2.000 ;
END
END gpio_defaults[8]
PIN gpio_defaults[9]
DIRECTION OUTPUT TRISTATE ;
USE SIGNAL ;
PORT
LAYER met2 ;
RECT 18.030 0.000 18.310 2.000 ;
END
END gpio_defaults[9]
OBS
LAYER nwell ;
RECT -0.190 9.465 25.030 11.070 ;
RECT -0.190 4.025 25.030 6.855 ;
LAYER li1 ;
RECT 0.000 2.635 24.840 10.965 ;
LAYER met1 ;
RECT 0.000 2.480 24.840 11.120 ;
LAYER met2 ;
RECT 0.390 11.000 1.610 11.120 ;
RECT 7.390 11.000 8.610 11.120 ;
RECT 14.390 11.000 15.610 11.120 ;
RECT 21.390 11.000 22.610 11.120 ;
RECT 0.390 2.280 23.820 11.000 ;
RECT 0.390 1.630 0.730 2.280 ;
RECT 1.570 1.630 2.570 2.280 ;
RECT 3.410 1.630 4.410 2.280 ;
RECT 5.250 1.630 6.250 2.280 ;
RECT 7.090 1.630 8.090 2.280 ;
RECT 8.930 1.630 9.930 2.280 ;
RECT 10.770 1.630 11.770 2.280 ;
RECT 12.610 1.630 14.070 2.280 ;
RECT 14.910 1.630 15.910 2.280 ;
RECT 16.750 1.630 17.750 2.280 ;
RECT 18.590 1.630 19.590 2.280 ;
RECT 20.430 1.630 21.430 2.280 ;
RECT 22.270 1.630 23.270 2.280 ;
LAYER met3 ;
RECT 0.300 11.000 1.700 11.045 ;
RECT 7.300 11.000 8.700 11.045 ;
RECT 14.300 11.000 15.700 11.045 ;
RECT 21.300 11.000 22.700 11.045 ;
RECT 0.300 2.555 22.700 11.000 ;
END
END gpio_defaults_block
END LIBRARY

1307
mag/gpio_defaults_block.mag Normal file
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File diff suppressed because it is too large Load Diff

115
maglef/gpio_defaults_block.mag Normal file
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@ -0,0 +1,115 @@
magic
tech sky130A
magscale 1 2
timestamp 1636108275
<< nwell >>
rect -38 1893 5006 2214
rect -38 805 5006 1371
<< obsli1 >>
rect 0 527 4968 2193
<< obsm1 >>
rect 0 496 4968 2224
<< metal2 >>
rect 202 0 258 400
rect 570 0 626 400
rect 938 0 994 400
rect 1306 0 1362 400
rect 1674 0 1730 400
rect 2042 0 2098 400
rect 2410 0 2466 400
rect 2870 0 2926 400
rect 3238 0 3294 400
rect 3606 0 3662 400
rect 3974 0 4030 400
rect 4342 0 4398 400
rect 4710 0 4766 400
<< obsm2 >>
rect 78 2200 322 2224
rect 1478 2200 1722 2224
rect 2878 2200 3122 2224
rect 4278 2200 4522 2224
rect 78 456 4764 2200
rect 78 326 146 456
rect 314 326 514 456
rect 682 326 882 456
rect 1050 326 1250 456
rect 1418 326 1618 456
rect 1786 326 1986 456
rect 2154 326 2354 456
rect 2522 326 2814 456
rect 2982 326 3182 456
rect 3350 326 3550 456
rect 3718 326 3918 456
rect 4086 326 4286 456
rect 4454 326 4654 456
<< obsm3 >>
rect 60 2200 340 2209
rect 1460 2200 1740 2209
rect 2860 2200 3140 2209
rect 4260 2200 4540 2209
rect 60 511 4540 2200
<< metal4 >>
rect 60 496 340 2224
rect 760 496 1040 2224
rect 1460 496 1740 2224
rect 2160 496 2440 2224
rect 2860 496 3140 2224
rect 3560 496 3840 2224
rect 4260 496 4540 2224
<< metal5 >>
rect 0 1436 4968 1756
rect 0 736 4968 1056
<< labels >>
rlabel metal5 s 0 1436 4968 1756 6 VGND
port 1 nsew ground input
rlabel metal4 s 760 496 1040 2224 6 VGND
port 1 nsew ground input
rlabel metal4 s 2160 496 2440 2224 6 VGND
port 1 nsew ground input
rlabel metal4 s 3560 496 3840 2224 6 VGND
port 1 nsew ground input
rlabel metal5 s 0 736 4968 1056 6 VPWR
port 2 nsew power input
rlabel metal4 s 60 496 340 2224 6 VPWR
port 2 nsew power input
rlabel metal4 s 1460 496 1740 2224 6 VPWR
port 2 nsew power input
rlabel metal4 s 2860 496 3140 2224 6 VPWR
port 2 nsew power input
rlabel metal4 s 4260 496 4540 2224 6 VPWR
port 2 nsew power input
rlabel metal2 s 202 0 258 400 6 gpio_defaults[0]
port 3 nsew signal output
rlabel metal2 s 3974 0 4030 400 6 gpio_defaults[10]
port 4 nsew signal output
rlabel metal2 s 4342 0 4398 400 6 gpio_defaults[11]
port 5 nsew signal output
rlabel metal2 s 4710 0 4766 400 6 gpio_defaults[12]
port 6 nsew signal output
rlabel metal2 s 570 0 626 400 6 gpio_defaults[1]
port 7 nsew signal output
rlabel metal2 s 938 0 994 400 6 gpio_defaults[2]
port 8 nsew signal output
rlabel metal2 s 1306 0 1362 400 6 gpio_defaults[3]
port 9 nsew signal output
rlabel metal2 s 1674 0 1730 400 6 gpio_defaults[4]
port 10 nsew signal output
rlabel metal2 s 2042 0 2098 400 6 gpio_defaults[5]
port 11 nsew signal output
rlabel metal2 s 2410 0 2466 400 6 gpio_defaults[6]
port 12 nsew signal output
rlabel metal2 s 2870 0 2926 400 6 gpio_defaults[7]
port 13 nsew signal output
rlabel metal2 s 3238 0 3294 400 6 gpio_defaults[8]
port 14 nsew signal output
rlabel metal2 s 3606 0 3662 400 6 gpio_defaults[9]
port 15 nsew signal output
<< properties >>
string LEFclass BLOCK
string FIXED_BBOX 0 0 5000 2200
string LEFview TRUE
string GDS_FILE ../gds/gpio_defaults_block.gds
string GDS_END 47838
string GDS_START 20982
<< end >>

70
openlane/gpio_defaults_block/config.tcl Normal file
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# SPDX-FileCopyrightText: 2020 Efabless Corporation
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
# SPDX-License-Identifier: Apache-2.0
set script_dir [file dirname [file normalize [info script]]]
set ::env(DESIGN_NAME) gpio_defaults_block
set ::env(DESIGN_IS_CORE) 1
set ::env(VERILOG_FILES) "\
$script_dir/../../verilog/rtl/defines.v\
$script_dir/../../verilog/rtl/gpio_defaults_block.v"
set ::env(CLOCK_PORT) ""
set ::env(CLOCK_TREE_SYNTH) 0
## Synthesis
set ::env(SYNTH_BUFFERING) 0
set ::env(SYNTH_READ_BLACKBOX_LIB) 1
set ::env(SYNTH_USE_PG_PINS_DEFINES) "USE_POWER_PINS"
## Floorplan
set ::env(DIE_AREA) "0 0 25 11"
set ::env(FP_SIZING) absolute
set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
set ::env(FP_IO_VLENGTH) "2"
set ::env(FP_IO_HLENGTH) "2"
set ::env(FP_HORIZONTAL_HALO) 0
set ::env(FP_VERTICAL_HALO) 0
set ::env(TOP_MARGIN_MULT) 0
set ::env(BOTTOM_MARGIN_MULT) 1
set ::env(LEFT_MARGIN_MULT) 0
set ::env(RIGHT_MARGIN_MULT) 0
set ::env(CELL_PAD) 0
## PDN Configuration
set ::env(FP_PDN_AUTO_ADJUST) 0
set ::env(FP_PDN_VWIDTH) 1.4
set ::env(FP_PDN_VOFFSET) 1
set ::env(FP_PDN_HOFFSET) 2
set ::env(FP_PDN_VPITCH) 7
set ::env(FP_PDN_HPITCH) 7
## Placement
set ::env(PL_TARGET_DENSITY) 0.92
set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 1
set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 0
set ::env(PL_RESZIER_REPIAR_TIE_FANOUT) 0
## Routing
set ::env(GLB_RT_MINLAYER) "2"
set ::env(GLB_RT_MAXLAYER) "5"
set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) 0

2
openlane/gpio_defaults_block/pin_order.cfg Normal file
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#S
gpio_defaults.*

1
signoff/gpio_defaults_block/OPENLANE_VERSION Normal file
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@ -0,0 +1 @@
openlane 2021.09.09_03.00.48-53-g97579eb

6
signoff/gpio_defaults_block/PDK_SOURCES Normal file
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@ -0,0 +1,6 @@
-ne openlane
e6ba5d36a9b32a9f87626d49bf3c80cf3964ebeb
-ne skywater-pdk
c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
-ne open_pdks
f90a86bdd133bd629251d59eebb1aee8452c0f5c

2
signoff/gpio_defaults_block/final_summary_report.csv Normal file
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@ -0,0 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
0,/project/openlane/gpio_defaults_block,gpio_defaults_block,gpio_defaults_block,flow_completed,0h1m12s,-1,94545.45454545453,0.000275,47272.727272727265,27.46,442.66,13,0,-1,-1,-1,-1,0,0,-1,0,0,-1,48,26,0.0,0.0,-1,0.0,-1,0.0,0.0,-1,0.0,-1,52604.0,0.0,3.85,0.0,0.0,0.0,-1,5,41,5,41,0,0,0,13,0,0,0,0,0,0,0,4,-1,-1,-1,6,2,0,8,90.9090909090909,11.0,10.0,AREA 0,5,50,1,7,7,0.92,0.0,sky130_fd_sc_hd,0,3
1 design design_name config flow_status total_runtime routed_runtime (Cell/mm^2)/Core_Util DIEAREA_mm^2 CellPer_mm^2 OpenDP_Util Peak_Memory_Usage_MB cell_count tritonRoute_violations Short_violations MetSpc_violations OffGrid_violations MinHole_violations Other_violations Magic_violations antenna_violations lvs_total_errors cvc_total_errors klayout_violations wire_length vias wns pl_wns optimized_wns fastroute_wns spef_wns tns pl_tns optimized_tns fastroute_tns spef_tns HPWL routing_layer1_pct routing_layer2_pct routing_layer3_pct routing_layer4_pct routing_layer5_pct routing_layer6_pct wires_count wire_bits public_wires_count public_wire_bits memories_count memory_bits processes_count cells_pre_abc AND DFF NAND NOR OR XOR XNOR MUX inputs outputs level EndCaps TapCells Diodes Total_Physical_Cells suggested_clock_frequency suggested_clock_period CLOCK_PERIOD SYNTH_STRATEGY SYNTH_MAX_FANOUT FP_CORE_UTIL FP_ASPECT_RATIO FP_PDN_VPITCH FP_PDN_HPITCH PL_TARGET_DENSITY GLB_RT_ADJUSTMENT STD_CELL_LIBRARY CELL_PAD DIODE_INSERTION_STRATEGY
2 0 /project/openlane/gpio_defaults_block gpio_defaults_block gpio_defaults_block flow_completed 0h1m12s -1 94545.45454545453 0.000275 47272.727272727265 27.46 442.66 13 0 -1 -1 -1 -1 0 0 -1 0 0 -1 48 26 0.0 0.0 -1 0.0 -1 0.0 0.0 -1 0.0 -1 52604.0 0.0 3.85 0.0 0.0 0.0 -1 5 41 5 41 0 0 0 13 0 0 0 0 0 0 0 4 -1 -1 -1 6 2 0 8 90.9090909090909 11.0 10.0 AREA 0 5 50 1 7 7 0.92 0.0 sky130_fd_sc_hd 0 3

90
spi/lvs/gpio_defaults_block.spice Normal file
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@ -0,0 +1,90 @@
* NGSPICE file created from gpio_defaults_block.ext - technology: sky130A
* Black-box entry subcircuit for sky130_fd_sc_hd__conb_1 abstract view
.subckt sky130_fd_sc_hd__conb_1 VGND VNB VPB VPWR HI LO
.ends
* Black-box entry subcircuit for sky130_fd_sc_hd__fill_2 abstract view
.subckt sky130_fd_sc_hd__fill_2 VGND VNB VPB VPWR
.ends
* Black-box entry subcircuit for sky130_fd_sc_hd__decap_12 abstract view
.subckt sky130_fd_sc_hd__decap_12 VGND VNB VPB VPWR
.ends
* Black-box entry subcircuit for sky130_fd_sc_hd__decap_8 abstract view
.subckt sky130_fd_sc_hd__decap_8 VGND VNB VPB VPWR
.ends
* Black-box entry subcircuit for sky130_fd_sc_hd__decap_3 abstract view
.subckt sky130_fd_sc_hd__decap_3 VGND VNB VPB VPWR
.ends
* Black-box entry subcircuit for sky130_fd_sc_hd__tapvpwrvgnd_1 abstract view
.subckt sky130_fd_sc_hd__tapvpwrvgnd_1 VGND VPWR
.ends
* Black-box entry subcircuit for sky130_fd_sc_hd__decap_4 abstract view
.subckt sky130_fd_sc_hd__decap_4 VGND VNB VPB VPWR
.ends
* Black-box entry subcircuit for sky130_fd_sc_hd__fill_1 abstract view
.subckt sky130_fd_sc_hd__fill_1 VGND VNB VPB VPWR
.ends
.subckt gpio_defaults_block VGND VPWR gpio_defaults[0] gpio_defaults[10] gpio_defaults[11]
+ gpio_defaults[12] gpio_defaults[1] gpio_defaults[2] gpio_defaults[3] gpio_defaults[4]
+ gpio_defaults[5] gpio_defaults[6] gpio_defaults[7] gpio_defaults[8] gpio_defaults[9]
Xgpio_default_value\[8\] VGND VGND VPWR VPWR gpio_default_value\[8\]/HI gpio_defaults[8]
+ sky130_fd_sc_hd__conb_1
XFILLER_0_26 VGND VGND VPWR VPWR sky130_fd_sc_hd__fill_2
XFILLER_0_49 VGND VGND VPWR VPWR sky130_fd_sc_hd__fill_2
XFILLER_0_38 VGND VGND VPWR VPWR sky130_fd_sc_hd__fill_2
Xgpio_default_value\[6\] VGND VGND VPWR VPWR gpio_default_value\[6\]/HI gpio_defaults[6]
+ sky130_fd_sc_hd__conb_1
XFILLER_1_3 VGND VGND VPWR VPWR sky130_fd_sc_hd__decap_12
XFILLER_1_40 VGND VGND VPWR VPWR sky130_fd_sc_hd__decap_8
XPHY_0 VGND VGND VPWR VPWR sky130_fd_sc_hd__decap_3
XPHY_1 VGND VGND VPWR VPWR sky130_fd_sc_hd__decap_3
Xgpio_default_value\[4\] VGND VGND VPWR VPWR gpio_default_value\[4\]/HI gpio_defaults[4]
+ sky130_fd_sc_hd__conb_1
XPHY_2 VGND VGND VPWR VPWR sky130_fd_sc_hd__decap_3
XPHY_4 VGND VGND VPWR VPWR sky130_fd_sc_hd__decap_3
XPHY_3 VGND VGND VPWR VPWR sky130_fd_sc_hd__decap_3
XPHY_5 VGND VGND VPWR VPWR sky130_fd_sc_hd__decap_3
Xgpio_default_value\[2\] VGND VGND VPWR VPWR gpio_default_value\[2\]/HI gpio_defaults[2]
+ sky130_fd_sc_hd__conb_1
Xgpio_default_value\[12\] VGND VGND VPWR VPWR gpio_default_value\[12\]/HI gpio_defaults[12]
+ sky130_fd_sc_hd__conb_1
XFILLER_1_35 VGND VGND VPWR VPWR sky130_fd_sc_hd__fill_2
Xgpio_default_value\[0\] VGND VGND VPWR VPWR gpio_default_value\[0\]/HI gpio_defaults[0]
+ sky130_fd_sc_hd__conb_1
XFILLER_1_48 VGND VGND VPWR VPWR sky130_fd_sc_hd__decap_3
XFILLER_1_27 VGND VGND VPWR VPWR sky130_fd_sc_hd__decap_8
XFILLER_1_15 VGND VGND VPWR VPWR sky130_fd_sc_hd__decap_12
Xgpio_default_value\[10\] VGND VGND VPWR VPWR gpio_defaults[10] gpio_default_value\[10\]/LO
+ sky130_fd_sc_hd__conb_1
Xgpio_default_value\[9\] VGND VGND VPWR VPWR gpio_default_value\[9\]/HI gpio_defaults[9]
+ sky130_fd_sc_hd__conb_1
XFILLER_2_41 VGND VGND VPWR VPWR sky130_fd_sc_hd__decap_8
Xgpio_default_value\[7\] VGND VGND VPWR VPWR gpio_default_value\[7\]/HI gpio_defaults[7]
+ sky130_fd_sc_hd__conb_1
XFILLER_2_3 VGND VGND VPWR VPWR sky130_fd_sc_hd__decap_12
XTAP_7 VGND VPWR sky130_fd_sc_hd__tapvpwrvgnd_1
XTAP_6 VGND VPWR sky130_fd_sc_hd__tapvpwrvgnd_1
Xgpio_default_value\[5\] VGND VGND VPWR VPWR gpio_default_value\[5\]/HI gpio_defaults[5]
+ sky130_fd_sc_hd__conb_1
XFILLER_0_3 VGND VGND VPWR VPWR sky130_fd_sc_hd__decap_4
XFILLER_2_15 VGND VGND VPWR VPWR sky130_fd_sc_hd__decap_12
XFILLER_2_49 VGND VGND VPWR VPWR sky130_fd_sc_hd__fill_2
XFILLER_2_27 VGND VGND VPWR VPWR sky130_fd_sc_hd__fill_1
Xgpio_default_value\[3\] VGND VGND VPWR VPWR gpio_default_value\[3\]/HI gpio_defaults[3]
+ sky130_fd_sc_hd__conb_1
XFILLER_0_7 VGND VGND VPWR VPWR sky130_fd_sc_hd__fill_1
XFILLER_2_29 VGND VGND VPWR VPWR sky130_fd_sc_hd__decap_12
Xgpio_default_value\[1\] VGND VGND VPWR VPWR gpio_defaults[1] gpio_default_value\[1\]/LO
+ sky130_fd_sc_hd__conb_1
Xgpio_default_value\[11\] VGND VGND VPWR VPWR gpio_default_value\[11\]/HI gpio_defaults[11]
+ sky130_fd_sc_hd__conb_1
.ends

222
verilog/gl/gpio_defaults_block.v Normal file
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@ -0,0 +1,222 @@
module gpio_defaults_block (VGND,
VPWR,
gpio_defaults);
input VGND;
input VPWR;
output [12:0] gpio_defaults;
wire \gpio_defaults_low[0] ;
wire \gpio_defaults_high[10] ;
wire \gpio_defaults_low[11] ;
wire \gpio_defaults_low[12] ;
wire \gpio_defaults_high[1] ;
wire \gpio_defaults_low[2] ;
wire \gpio_defaults_low[3] ;
wire \gpio_defaults_low[4] ;
wire \gpio_defaults_low[5] ;
wire \gpio_defaults_low[6] ;
wire \gpio_defaults_low[7] ;
wire \gpio_defaults_low[8] ;
wire \gpio_defaults_low[9] ;
wire \gpio_defaults_high[0] ;
wire \gpio_defaults_high[11] ;
wire \gpio_defaults_high[12] ;
wire \gpio_defaults_high[2] ;
wire \gpio_defaults_high[3] ;
wire \gpio_defaults_high[4] ;
wire \gpio_defaults_high[5] ;
wire \gpio_defaults_high[6] ;
wire \gpio_defaults_high[7] ;
wire \gpio_defaults_high[8] ;
wire \gpio_defaults_high[9] ;
wire \gpio_defaults_low[10] ;
wire \gpio_defaults_low[1] ;
sky130_fd_sc_hd__fill_2 FILLER_0_26 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_4 FILLER_0_3 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__fill_2 FILLER_0_38 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__fill_2 FILLER_0_49 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__fill_1 FILLER_0_7 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_12 FILLER_1_15 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_8 FILLER_1_27 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_12 FILLER_1_3 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__fill_2 FILLER_1_35 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_8 FILLER_1_40 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 FILLER_1_48 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_12 FILLER_2_15 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__fill_1 FILLER_2_27 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_12 FILLER_2_29 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_12 FILLER_2_3 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_8 FILLER_2_41 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__fill_2 FILLER_2_49 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_0 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_1 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_2 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_3 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_4 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_5 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_6 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_7 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__conb_1 \gpio_default_value[0] (.HI(\gpio_defaults_high[0] ),
.LO(\gpio_defaults_low[0] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__conb_1 \gpio_default_value[10] (.HI(\gpio_defaults_high[10] ),
.LO(\gpio_defaults_low[10] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__conb_1 \gpio_default_value[11] (.HI(\gpio_defaults_high[11] ),
.LO(\gpio_defaults_low[11] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__conb_1 \gpio_default_value[12] (.HI(\gpio_defaults_high[12] ),
.LO(\gpio_defaults_low[12] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__conb_1 \gpio_default_value[1] (.HI(\gpio_defaults_high[1] ),
.LO(\gpio_defaults_low[1] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__conb_1 \gpio_default_value[2] (.HI(\gpio_defaults_high[2] ),
.LO(\gpio_defaults_low[2] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__conb_1 \gpio_default_value[3] (.HI(\gpio_defaults_high[3] ),
.LO(\gpio_defaults_low[3] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__conb_1 \gpio_default_value[4] (.HI(\gpio_defaults_high[4] ),
.LO(\gpio_defaults_low[4] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__conb_1 \gpio_default_value[5] (.HI(\gpio_defaults_high[5] ),
.LO(\gpio_defaults_low[5] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__conb_1 \gpio_default_value[6] (.HI(\gpio_defaults_high[6] ),
.LO(\gpio_defaults_low[6] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__conb_1 \gpio_default_value[7] (.HI(\gpio_defaults_high[7] ),
.LO(\gpio_defaults_low[7] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__conb_1 \gpio_default_value[8] (.HI(\gpio_defaults_high[8] ),
.LO(\gpio_defaults_low[8] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__conb_1 \gpio_default_value[9] (.HI(\gpio_defaults_high[9] ),
.LO(\gpio_defaults_low[9] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
assign gpio_defaults[0] = \gpio_defaults_low[0] ;
assign gpio_defaults[10] = \gpio_defaults_high[10] ;
assign gpio_defaults[11] = \gpio_defaults_low[11] ;
assign gpio_defaults[12] = \gpio_defaults_low[12] ;
assign gpio_defaults[1] = \gpio_defaults_high[1] ;
assign gpio_defaults[2] = \gpio_defaults_low[2] ;
assign gpio_defaults[3] = \gpio_defaults_low[3] ;
assign gpio_defaults[4] = \gpio_defaults_low[4] ;
assign gpio_defaults[5] = \gpio_defaults_low[5] ;
assign gpio_defaults[6] = \gpio_defaults_low[6] ;
assign gpio_defaults[7] = \gpio_defaults_low[7] ;
assign gpio_defaults[8] = \gpio_defaults_low[8] ;
assign gpio_defaults[9] = \gpio_defaults_low[9] ;
endmodule